JP3764447B2 - Hardware simulation device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a CAD (computer aided design) system that supports hardware design, and more particularly, to a hardware simulation apparatus that simulates the operation of a specification model indicating the operation of the created hardware.
[0002]
[Prior art]
For example, a hardware simulation device that simulates the operation of hardware such as a logic circuit incorporated in an integrated circuit created by a CAD device reads each operation request described in the hardware specification model and executes it in order. To go.
[0003]
For example, when the hardware specification model is composed of a plurality of operation units (processes), the signal given to the first operation unit is input, and the output of this operation unit is changed. Next, the output signal in which the first operation unit is changed is input to the second operation unit, and each operation request included in the second operation unit is executed. Then, an output value of the second operation unit is obtained.
[0004]
The hardware designer advances the simulation time while stopping the simulation operation, referencing the internal state, and rewriting the internal state.
[0005]
[Problems to be solved by the invention]
However, the hardware simulation apparatus as described above has a technical problem that the validity cannot be known with respect to the range of values set in the signal. That is, no function is provided for storing a range of values actually taken by each signal during the simulation execution process and comparing the range of values given to the signal in the created specification model. Therefore, even if a certain signal can actually take only a certain range of values, but it is constructed to take a wide range of values on the specification model, there are also processing circuits for signal values that do not appear during actual operation. There is a problem of designing and designing a useless circuit.
[0006]
In addition, it is common to verify that the designed specification model operates normally using a plurality of test data. At this time, when paying attention to a certain signal, it is necessary to check whether the verification has been completed over the entire range of values that the signal can take as a criterion for determining whether the specification model is sufficiently verified. is there.
[0007]
However, in the simulation apparatus described above, the designer does not store the upper and lower limits of the values actually taken by the signal in the simulation execution process. It was difficult to judge the sufficiency of verification.
[0008]
The present invention has been made in view of such circumstances, and by storing and holding various histories such as signal values and execution times in a simulation execution process, a circuit for a designer to perform hardware simulation is stored. An object of the present invention is to provide a hardware simulation apparatus capable of improving the debugging work efficiency.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a request reading means for reading a signal processing request including each signal substitution request described in a specification model describing the operation of hardware, and each signal read by the request reading means. In a hardware simulation apparatus having a request storage means for storing a processing request and a request execution means for sequentially executing each signal processing request stored in the request storage means, a signal for one signal is actually received by the request execution means. Each time a processing request is executed, the signal value detecting means for detecting the maximum value and the minimum value of the corresponding signal up to that point, and the maximum value and the minimum value detected by the signal value detecting means are respectively set as upper limits. Signal limit value storage means for storing values and lower limit values, and each time a signal substitution request for a signal is actually executed by the request execution means, a signal substitution value and a signal limit value are stored. Comparing means for comparing the upper limit value and lower limit value stored in the stage, and when the signal substitution value is larger than the upper limit value, the upper limit value is updated to the substitution value, and when the signal substitution value is smaller than the lower limit value, the lower limit Signal limit value updating means for updating the value to the substitution value, and limit value display means for displaying the upper limit value and the lower limit value stored in the signal limit value storage means are provided.
[0010]
[Action]
In the hardware simulation apparatus configured as described above, every time a signal processing request for one signal is actually executed, the maximum value and the minimum value of the signal value of the corresponding signal up to that point are detected, and the upper limit is detected. Value and lower limit value. When the substitution value for this signal exceeds the upper limit value and the lower limit value, the upper limit value or the lower limit value is updated with this substitution value. These values are displayed when the designer requests to present the upper and lower limits of the signal.
[0011]
As a result, the designer has not yet verified that the created specification model is over spec compared to the size of the data that actually flows, or that all possible values are considered for a given signal. Etc. can be easily confirmed.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
FIG. 1 is a block diagram showing a schematic configuration of a hardware simulation apparatus according to the first embodiment. The hardware simulation apparatus is configured by an information processing apparatus such as a computer.
[0014]
For example, in the specification model 1a describing the operation of the hardware created by the CAD device, as shown in FIG. 2, a large number of operation requests and execution request times indicating the timing of executing each operation request are described. Yes.
[0015]
The operation request and execution request time described in the specification model 1 a are read by the request reading unit 2 and then temporarily registered in the request storage unit 3. The request storage unit 3 is executed in the process of sequentially registering each operation request read by the request reading unit 2 due to the relationship between the execution request times among the previously registered operation requests. If an operation request that cannot be performed occurs, the operation request is deleted. The request execution unit 4 actually executes each operation request stored in the request storage unit 3 when the execution request time specified in the operation request is reached.
[0016]
The deletion request detection unit 5 detects an operation request to be deleted in the request storage unit 3. The deletion operation request detected by the deletion request detection unit 5 is displayed on the display 7 configured by a CRT display device or the like by the display output unit 6.
[0017]
A specific operation of the hardware simulation apparatus configured as described above will be described by taking as an example a case where the specification model 1a describing the hardware operation shown in FIG. 2 is simulated.
[0018]
FIG. 2 is a specification model in which the operation content of the module E1 is written in the operation description of B1. That is, the operation of the specification model 1a is composed of two operation units (processes) P0 and P1. The first operation unit P0 inverts the signal CLK every 3 ns as described in the operation request in the seventh row. In the second operation unit P0, as described in each operation request on the 8th to 11th rows, when the signal CLK changes, 5 is assigned to the signal A after 1 ns, and 10 is assigned after 6 ns. Generate a request.
[0019]
In the specification model 1a represented by such a description, the processing of the second operation unit P1 is started every time the CLK signal value changes with the first operation unit P0 (line 8). Two signal substitution requests (lines 10 and 11) described in the operation unit P1 are reserved and registered.
[0020]
However, before the second signal substitution (11th line) is executed, the value of the signal CLK is always changed (7th line), the operation unit P1 is executed, and the next signal substitution (10th line). Eye) is reserved. At this time, since the reservation for substitution at an earlier time than the scheduled execution time of the remaining second signal substitution reservation (line 11) is made, the remaining signal substitution reservation is deleted (cancelled). .
[0021]
That is, in the case of the hardware specification model 1a shown in FIG. 2, the second signal substitution request (11th line) described in the operation unit P1 is not executed at all. This indicates that there is a bug in the delay time for signal substitution and the timing of the change in the sensitivity list signal. Such a description of an operation request is not a grammatical error, so this bug cannot be found only by statically analyzing a description representing such a circuit, and can only be found while executing a simulation.
[0022]
However, in the embodiment apparatus shown in FIG. 1, when the signal substitution request is deleted (cancelled), the deletion request detection unit 5 detects the signal substitution request deletion, and the display output unit 6 displays on the display 7. Output. As a result, the designer can know that there is a possibility that a timing bug is included in the corresponding part of the description, and it is possible to eliminate such a bug at an early stage of the simulation.
[0023]
In order to specify each operation request such as signal substitution, for each operation request name, the target signal and the module to which the signal belongs, and where in the description of the specification model 1a correspond (if it is a file of the drawing It is necessary to have a method that includes information such as the file name and the position where the corresponding signal is drawn, and the file name and the line number of the assignment statement if written in a hardware description language.
[0024]
For example, in the example, the 11th row of the module E1 for the second substitution reservation, and for the internal signal A of the module E1, is stored in the request storage unit 3 for information relating to the signal substitution request. The designer can correct the design by paying attention to the corresponding part of these descriptions.
[0025]
FIG. 3 is a block diagram showing a schematic configuration of the hardware simulation apparatus according to the second embodiment. The same parts as those in the embodiment apparatus shown in FIG. Therefore, the detailed description of the overlapping part is omitted.
[0026]
In this embodiment apparatus, the signal processing request such as the signal substitution request described in the specification model 1b and the execution request time are read by the request reading unit 2 and temporarily registered in the request storage unit 3. Thereafter, the request execution unit 4 actually executes the request. Then, as shown in FIG. 4, the request display unit 8 displays each signal processing request registered in the request storage unit 3 on the display unit 7 when the corresponding execution request time arrives. Further, the signal display unit 9 displays the signal value after the signal processing request actually executed by the request execution unit 4 on the same screen as the previous signal processing request.
[0027]
Thus, as shown in FIG. 4, the designer displays the signal processing request described in the specification model 1b and the signal state after actually executed on the same screen of the display unit 7, thereby allowing the designer to Although there was a processing request, it can be easily grasped that the signal processing request was not actually executed.
[0028]
It is very easy to understand if the signal value is displayed as a waveform as shown in FIG. Also, as shown in the figure, execution and non-execution of each signal processing request becomes clearer by marking and displaying the deleted signal processing request. Furthermore, numbers can be displayed so that the order in which signal processing requests are generated can be easily understood. In this case, the value can be known without displaying the signal value after the signal processing request actually executed.
[0029]
FIG. 5 is a block diagram showing the configuration of the hardware simulation apparatus according to the third embodiment. The same parts as those in the embodiment apparatus shown in FIG. Therefore, the detailed description of the overlapping part is omitted.
[0030]
In this embodiment apparatus, an operation request such as a signal substitution request described in the specification model 1 c and an execution request time are read by the request reading unit 2 and temporarily registered in the request storage unit 3. Thereafter, the request execution unit 4 actually executes the request. The signal time storage unit 10a as the final execution time detection unit stores the execution time when each operation request included in each operation unit such as a signal substitution request is actually executed in the request execution unit 4. The determination unit 11 determines whether or not each execution time stored in the signal time storage unit 10a falls within the time range specified for the corresponding operation unit. The operation request display unit 12 displays an operation request that falls within a designated time range in the corresponding operation unit on the display unit 7.
[0031]
A specific operation of the hardware simulation apparatus configured as described above will be described by taking as an example a case where the specification model 1c describing the hardware operation shown in FIG. 6 is simulated.
[0032]
The module E1 whose operation is described in B1 in the specification model 1c shown in FIG. 6 includes two operation units P0 and P1. As shown in the 19th row, the first operation unit P1 increases the signal CASENUM by 1 every 3 ns. In the second operation unit P0, when the signal CASENUM changes (7th line), as shown in the 10th to 16th lines, the signal CASENUM is 0, 1,. When the delay time of 60 ns to 10 ns elapses in the signal A every time it changes to 5, 0, 1,. Substitute the value of 5.
[0033]
In such a specification model 1c, the processing of the operation unit P0 is started each time the signal value of the signal CASENUM changes, and the signal substitution described in the operation unit P0 is required. Before the start time +60 ns when the first signal substitution (10th line) is executed, the value of the signal CASENUM changes again at the start time +3 ns. As a result, a second (11th row) signal substitution request (start time + 53 ns) is generated. At this time, since the second signal substitution reservation is a reservation for substitution at an earlier time than the scheduled execution time of the remaining first signal substitution reservation, the remaining first (10th line) signal substitution is reserved. The reservation is deleted (cancelled).
[0034]
That is, in the case of the specification model 1c described as shown in FIG. 6, the first substitution request written in the operation unit P0 is not executed at all. Similarly, the second to sixth signal substitution requests are not executed. That is, the signal A does not change until 63 ns has elapsed from the simulation start time. Since such a description is not a grammatical error, this bug cannot be found only by analyzing the description of the specification model 1c representing the hardware, and can only be found in the process of executing the simulation.
[0035]
Therefore, in the embodiment device, the time of the last signal substitution executed for each signal is stored in the signal time storage unit 10a. Then, in the case of the specification model 1c described above, the simulation start time remains stored in the time storage unit corresponding to the signal A until 62 ns have elapsed from the start of the simulation. The determination unit 11 determines that the value of the signal time storage unit 10a for the signal A has not changed. The operation request display unit 12 displays on the display 7 that no signal substitution request for the signal A has been executed. As a result, the designer can find a description of an operation request that is not reflected in the operation of the circuit at an early stage of the simulation.
[0036]
In addition to the time, what is stored in the signal time storage unit 10a may be a simulation cycle.
[0037]
Further, as in the specification model 1a of FIG. 2 described above, it is difficult to determine a description in which a part of the signal substitution request is not executed from the time stored in the signal time storage unit 10a. The number of substitution reservations and the number of substitution executions are recorded in each signal instead of storing the signal, and by determining the ratio, an operation request description that is not reflected in the operation of the circuit at an early stage of the simulation is displayed on the display 7. Can be displayed.
[0038]
Furthermore, in the embodiment apparatus, an operation request that falls within a specified time range is displayed, but an operation request that is out of the range can also be displayed.
[0039]
FIG. 7 is a block diagram showing a schematic configuration of a hardware simulation apparatus according to the fourth embodiment. The same parts as those in the embodiment apparatus shown in FIG. Therefore, the detailed description of the overlapping part is omitted.
[0040]
In this embodiment apparatus, a parallel operation storage section 10b is incorporated in place of the signal time storage section 10a of the embodiment apparatus of FIG. The parallel operation storage unit 10b stores the time at each time when the parallel operation is started in the simulation execution process in the request execution unit 4. The determination unit 11 determines whether or not the time stored in the parallel operation storage unit 10b falls within the specified time range. The operation request display unit 12 displays the parallel operation units that fall within the specified time range on the display unit 7.
[0041]
A specific operation of the hardware simulation apparatus configured as described above will be described by taking as an example a case where the specification model 1d describing the hardware operation shown in FIG. 8 is simulated.
[0042]
In the specification model 1d represented by the description shown in FIG. 8, since the signal B does not change at all, the parallel operation unit P0 is not executed. Thus, since the parallel operation unit P0 that is not activated at all is not an error in terms of grammar, this bug cannot be found unless it is a simulation process.
[0043]
In the embodiment apparatus, a parallel operation time storage unit 10b for storing the latest simulation cycle executed for each parallel operation unit is provided. Therefore, the simulation start time is always stored in the parallel operation time storage unit 10b for the parallel operation unit P0. When the determination unit 11 determines the parallel operation unit whose simulation start time is stored in the parallel operation time storage unit 10b, the operation request display unit 12 enters the time at which the parallel operation unit P0 is designated, so To display.
[0044]
The designer can remove the description bug by looking at the display contents and paying attention to the signal B for starting the operation unit and the signal B for the operation unit P0.
[0045]
Next, the case where the specification model 1e including a large number of parallel operation units as shown in FIG. 9 is simulated will be described.
[0046]
This specification model 1e includes 101 operation units for determining the value of each element of the array signal T having 101 elements, and 101 unit operations of P0 to P100 that operate according to changes in the respective signal values. And a total of 202 operation units. For the sake of simplicity, the description is omitted.
[0047]
In this specification model 1e, there are many parallel operation units, but there are few operation units that operate at the same time. In the general circuit, the parallel operation unit activated at the same time as in the specification model 1e is a part. It is assumed that an abnormal operation appears in the circuit during the simulation operation process of the specification model 1e. In this case, it is difficult to identify the operation unit that caused the abnormal operation among all these operation units, and a very long debugging time is required.
[0048]
However, if only the parallel operation unit activated at a certain time is displayed on the display unit 7 as in the embodiment apparatus, the operation unit causing the abnormal operation may be limited among them. For example, if the operation unit P49 causes an abnormal operation, the operation units activated at the same time are a small part of all the operation units, and therefore it can be easily found that the operation unit P49 is the cause. In this way, the time for investigating the cause of the abnormal operation can be shortened.
[0049]
FIG. 10 is a block diagram showing a schematic configuration of a hardware simulation apparatus according to the fifth embodiment. The same parts as those in the embodiment apparatus shown in FIG. Therefore, the detailed description of the overlapping part is omitted.
[0050]
In this embodiment apparatus, an operation request such as a signal processing request described in the specification model 1 f and an execution request time are read by the request reading unit 2 and temporarily registered in the request storage unit 3. Thereafter, the request execution unit 4 actually executes the request.
[0051]
Each time the request execution unit 4 actually executes a signal processing request for one signal, the signal value detection unit 13 detects the maximum value and the minimum value of the signal value of the corresponding signal up to that point. The signal limit value storage unit 14 stores the maximum value and the minimum value detected by the signal value detection unit 13 as an upper limit value and a lower limit value, respectively. The comparison unit 15 compares the signal substitution value with each of the upper limit value and the lower limit value stored in the signal limit value storage unit 14 every time the signal execution request for the signal is actually executed by the request execution unit 4. The signal limit value updating unit 16 updates the upper limit value to the substituted value when the signal substituted value is larger than the upper limit value, and updates the lower limit value to the substituted value when the signal substituted value is smaller than the lower limit value. Furthermore, the limit value display unit 17 displays the upper limit value and the lower limit value stored in the signal limit value storage unit 14 on the display unit 7 in response to, for example, a designer's display request.
[0052]
A specific operation of the hardware simulation apparatus configured as described above will be described by taking as an example a case where the specification model 1f describing the hardware operation shown in FIG. 11 is simulated.
[0053]
In the specification model 1f represented by the description shown in FIG. 11, every time the value of the signal CASENUM input from the outside to the input port of the module E1 changes (line 6), the signal CASENUM value at that time and other values are changed. The value of the output port MBA is calculated from the value of the input port TBL and output. For example, when the input signal CASENUM value is 2, the value of the output port MBA is a value obtained by multiplying the value of the input port TBL by 2 (line 10).
[0054]
As a condition for executing simulation by substituting multiple types of test data for the input signal CASENUM for such a specification model 1f, the lower limit value of the input signal CASENUM is 4, and the upper limit value is 7. Assume that there was. In this case, the simulation is not executed when the signal CASENUM value in the 9th to 11th lines is 1 to 3 and when the signal CASENUM value is 8 or more in the 16th line.
[0055]
in this case,
(A) In fact, the tests in those cases must also be performed, and the simulations currently performed do not have a sufficiently wide range of tests.
(B) Although the signal CASENUM can only take a value of 4 or more due to the nature of the hardware to be simulated, the specification motel 1f is a description that takes into consideration other cases, and is wasteful.
Two possibilities are conceivable. In the former case, if this is not noticed, hardware that has not been fully verified may be already verified, and both design time and cost may be lost.
[0056]
In the latter case, when designing a logic circuit with reference to the description, there is a possibility that a useless circuit that is not actually used may be designed, which is influenced by the area of the chip.
[0057]
In the embodiment apparatus, after executing simulation when the input signal CASENUM value is changed to a plurality of types, the signal limit including the upper limit value and the lower limit value of the input signal CASENUM is displayed on the display unit 7. Therefore, the designer can determine whether or not a sufficiently wide simulation has been completed for the values that the signal can take by reading the display information on the display device 7.
[0058]
In addition, it is possible to easily determine whether or not a useless operation request considering the possibility of taking a wide range of values for a signal that can only take a certain range of values is described.
[0059]
Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.
[0060]
【The invention's effect】
As described above, in the hardware simulation apparatus of the present invention, various histories such as signal values and execution times in the simulation execution process are stored and held. Information on this is displayed and output as necessary. Therefore, it is possible to improve the debugging work efficiency in the hardware circuit when the designer performs the hardware simulation.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a hardware simulation apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing a hardware specification model simulated by the apparatus of the embodiment.
FIG. 3 is a block diagram showing a schematic configuration of a hardware simulation apparatus according to another embodiment of the present invention.
FIG. 4 is an output diagram of signal waveforms and signal processing requests obtained by the apparatus of the embodiment.
FIG. 5 is a block diagram showing a schematic configuration of a hardware simulation apparatus according to still another embodiment of the present invention.
FIG. 6 is a diagram showing a hardware specification model simulated by the apparatus of the embodiment.
FIG. 7 is a block diagram showing a schematic configuration of a hardware simulation apparatus according to still another embodiment of the present invention.
FIG. 8 is a diagram showing a hardware specification model simulated by the apparatus of the embodiment.
FIG. 9 is a diagram showing a hardware specification model simulated by the apparatus of the embodiment.
FIG. 10 is a block diagram showing a schematic configuration of a hardware simulation apparatus according to still another embodiment of the present invention.
FIG. 11 is an exemplary diagram showing a hardware specification model simulated by the apparatus of the embodiment.
[Explanation of symbols]
1a, 1b, 1c, 1d, 1e, 1f ... specification model, 2 ... request reading unit, 3 ... request storage unit, 4 ... request execution unit, 5 ... deletion request detection unit, 6 ... display output unit, 7 ... indicator , 8 ... request display section, 9 ... signal display section, 10a ... signal time storage section, 10b ... parallel operation time storage section, 11 ... determination section, 12 ... operation request display section, 13 ... signal value detection section, 14 ... signal Limit value storage unit, 15 ... comparison unit, 16 ... signal limit value update unit, 17 ... limit value display unit.

Claims (1)

Request reading means for reading a signal processing request including each signal substitution request described in the specification model describing the operation of the hardware, request storing means for storing each signal processing request read by the request reading means, In a hardware simulation apparatus having request execution means for sequentially executing each signal processing request stored in the request storage means,
Each time a signal processing request for one signal is actually executed by the request execution means, a signal value detection means for detecting a maximum value and a minimum value of the signal value of the corresponding signal up to that point;
Signal limit value storage means for storing the maximum value and the minimum value detected by the signal value detection means as an upper limit value and a lower limit value, respectively;
Comparison means for comparing the signal substitution value with each of the upper limit value and the lower limit value stored in the signal limit value storage means each time a signal substitution request for the signal is actually executed by the request execution means,
When the signal substitution value is larger than the upper limit value, the upper limit value is updated to the substitution value, and when the signal substitution value is smaller than the lower limit value, a signal limit value updating means for updating the lower limit value to the substitution value;
A hardware simulation device comprising limit value display means for displaying an upper limit value and a lower limit value stored in the signal limit value storage means.

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