JP3760614B2 - Semiconductor device and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate field effect transistor having a plurality of control gates capable of configuring a general-purpose logic circuit capable of performing logical operations of all Boolean functions, for example, and a control signal generation for applying a control signal to the insulated gate field effect transistor And a control method thereof. Specifically, the present invention provides, for example, a control signal in which the control signal generator obtains a desired solution from a logic circuit autonomously by a so-called genetic algorithm even when the logic circuit cannot obtain a correct solution. A configuration suitable for self-evolution that allows complex logic calculations to be executed accurately in a short time by generating logic and operating logic circuits correctly, and by adding means for connecting between multiple logic circuits and further learning functions The present invention relates to a semiconductor device and a control method thereof.
[0002]
[Prior art]
In the field of computer science and the like, “evolving computers” and “evolving hardware” have recently attracted attention. These are related to “genetic algorithm”, “artificial life”, and “complexity” which has become a popular buzzword recently, and it seems to develop in conjunction with these ideas.
"Evolving hardware" is a genetic algorithm that applies variability and programmability to the hardware of a system that had previously been assumed to have fixed functions, and applied an evolutionary system for life. (Genetic Algorithms, hereinafter abbreviated as GA) is used to adapt hardware functions to the environment and evolve them.
[0003]
Fundamental research and development of “evolving hardware” has been carried out by several research institutions. Among them, typical GA applications include FPGA (Field Programmable Gate Array) and PLD (Programmabl Logic Device). ) Etc.
Hereinafter, what uses PLD shown by the following literature (1) is demonstrated.
[0004]
Reference (1): Tetsuya Higuchi et al .: “Basic Experiments of Hardware Evolution by Genetic Learning”, “Genetic Algorithm”, Chapter 10, Industrial Books, 1993.
[0005]
This document describes a method of obtaining a desired combinational circuit and sequential circuit by using a genetic algorithm (GA) for PLD logic determination. It is also stated that such means will become the basis of large-scale evolution systems in the future.
[0006]
The PLD shown in the document (1) is called GAL16V8, and is general and simple. FIG. 13 shows a configuration diagram of this PLD. A PLD is composed of connection patterns and logic macrocells arranged in an array, and by specifying the presence / absence of connection and the selection of logic functions by a combination of control bit strings, a logic circuit, that is, a logic device having a desired function is designated. Obtainable. The array pattern in the previous stage where the input signal is input is provided with a program element such as a fuse or EEPROM at each intersection, and by programming these, the AND logic for the input signal can be selected. Each ANDed line is input to the logic macrocell, passed through the OR logic, and then output through a selected circuit such as a flip-flop. That is, the PLD is based on an additive standard form composed of AND and OR logic, and a desired combinational circuit, sequential circuit, and the like are formed.
[0007]
Document (1) proposes to construct a “evolving hardware” system by using a genetic algorithm (GA) to determine the logical function of the PLD.
Specifically, first, a control bit string for determining the logic of the PLD is regarded as a chromosome from an analogy with a gene, and a large number of these chromosomes are prepared at random. Then, the correspondence between the input pattern and the output is examined for the logic circuit determined by each chromosome (bit string), the respective output results are compared with the desired output value, and the fitness of the chromosome is determined according to the degree of coincidence. If the degree of coincidence is high, the fitness is increased, and if it is low, it is decreased. Then, select chromosomes with a probability proportional to the fitness level (natural selection), perform bit crossover (mating) and bit data conversion (mutation) on them, and compare the logic output and evaluate the fitness again. Do. This cycle (generation change) is repeated many times, and finally a fitness bit 100, that is, a control bit string whose logic completely matches the desired one is obtained. If the environment changes and different functions are required, the system can repeat the same method and change the logic autonomously and evolve.
[0008]
Reference (1) introduces logic confirmation by GA of 6 multiplexers as an example of the above system. Using 108-bit long chromosome expression, accurate evaluation is performed by 2000 generations of fitness evaluation and crossover. Is obtained.
[0009]
[Problems to be solved by the invention]
The “evolving hardware” system using the PLD described in the above prior art has several problems.
[0010]
As pointed out in the literature (1), the current PLD uses program elements such as EPROM and EEPROM, but the guaranteed number of rewrites is about 100 times. It is impossible to realize 2000 cycles of GA operation and further long-term evolution process operation. For this reason, in the example of the document (1), the system is not verified using the real device (PLD), but the GA operation of the control bit string is merely simulated on the computer.
[0011]
Also, rewriting of devices such as EPROM, EEPROM, etc. requires a very long time when performing GA operation because it is necessary to enter a special rewrite mode even with ultraviolet erasure or on-board. Therefore, it is impossible to construct a self-adaptive system that adapts to the environment in real time.
[0012]
Furthermore, as described above, the PLD is basically based on the additive standard form constructed by the product-sum logic. However, the additive standard form is generally not the most efficient logical expression. Redundant parts are likely to occur. The fact that the circuit is redundant means that the length of the chromosome is increased in the GA operation, and the efficiency of the GA operation is deteriorated. On the other hand, if the chromosome length is fixed, it means that the flexibility in change is low.
[0013]
Also, the following document (2) proposes a technique for applying the GA to the VLSI design language HDL and evolutionally changing the LSI design, like the concept described above.
[0014]
Reference (2): Hitoshi Henmi et al .: “Evolution of Behavioral Hardware”, “Genetic Algorithm”, Chapter 8, Industrial Books, 1995.
[0015]
However, this is also a simulation experiment, and there is no mention of how to actually change the actual device.
[0016]
The ideas currently proposed for realizing “evolving hardware” in this way are those using existing devices such as FPGA and PLD, and hardware description language (HDL). It is still at the simulation level, and it remains limited to software research while targeting hardware.
As described above, in realizing an actual “evolving hardware system”, there are many problems and issues described above. In particular, as a device that actually configures the system, a more suitable device that replaces the PLD at present is required.
[0017]
The present invention has been made in view of such circumstances, proposes an application of a device that can fully exploit the possibility of system evolution by a genetic algorithm, and proposes an efficient control method for this application. An object of the present invention is to newly provide a semiconductor device that is practical and realizable as hardware that evolves and a logic determination method thereof.
[0018]
[Means for Solving the Problems]
In order to solve the above-mentioned problems of the prior art and achieve the above object, in the semiconductor device of the present invention, a MISFET having a plurality of control gates constituting a general-purpose logic circuit capable of changing an arithmetic logic is a so-called evolution. It is used as a basic device for hardware.
[0019]
That is, in the semiconductor device of the present invention, as means for generating an insulated gate field effect transistor having a plurality of control gates and a control signal to be applied to the control gate in order to obtain a desired output from the insulated gate field effect transistor, When a desired output is obtained when each voltage level of the prepared voltage level group is input to the insulated gate field effect transistor, a voltage level at which the desired output is obtained is output as the control signal, When the output cannot be obtained, the voltage level is selected and / or changed based on the output result, and the selection and / or change is repeated until the desired output is obtained to converge the voltage level group. A control signal generation unit that outputs a voltage level at which the output is obtained as the control signal.
[0020]
In addition, an input conversion unit that converts a plurality of input signals into a voltage that takes a plurality of levels according to the combination of the logic and outputs the voltage, and the insulated gate field effect transistor, the control gate for the control signal input A determination signal generation unit that generates a logic determination signal based on the applied control signal and the converted input signal applied from the input conversion unit to another control gate; and the output of the input conversion unit is input to the signal input. Connected, and the output of the deterministic signal generation unit is connected to the control input, and a logical operation of a predetermined function determined according to the logic deterministic signal received by the control input is performed on the input signal converted by the input conversion unit A logic circuit including a variable arithmetic unit to be executed is connected to the control signal generation unit.
[0021]
In this case, the control signal generation unit preferably includes a comparison unit that compares a calculation result obtained by inputting a plurality of voltage levels prepared in advance to the logic circuit with a desired calculation result, and the comparison result. A selection unit that newly selects a plurality of voltage levels with an occurrence probability according to the degree of coincidence of the calculation results, a change unit that changes the selected voltage level, and controls these comparison unit, selection unit, and change unit, A control unit that specifies a voltage level at which a desired logic determination signal can be obtained while repeating the calculation, comparison, selection, and change, and outputs the voltage level to the determination signal generation unit as the control signal.
[0022]
These input conversion unit, deterministic signal generation unit, and variable calculation unit can be constructed by so-called νMOS.
In other words, the input conversion unit, the deterministic signal generation unit, and the variable calculation unit include two insulated gate field effect transistors of a p-type channel and an n-type channel connected in series between the first power supply voltage and the second power supply voltage. The two transistors include a floating gate extending on a gate insulating film formed on a semiconductor channel formation region and commonly connected between the two transistors, and the floating gate or the floating gate. A plurality of control gates which are arranged on the connecting portion via an insulating film and which control the potential of the floating gate in multiple stages by a combination of applied voltages to set the output voltage level or change the threshold voltage; .
[0023]
The input conversion unit has a source follower connection in which an output is taken from a series connection point where the sources of two transistors are connected to each other. On the other hand, the deterministic signal generation unit and the variable calculation unit may be connected as a source follower, or may be connected as an inverter that extracts an output from a series connection point where the drains of two transistors are connected to each other.
[0024]
The semiconductor device of the present invention, which is preferable for constructing a complicated circuit, can program a plurality of logic circuits capable of changing the arithmetic logic, connection between the plurality of logic circuits, and selection of input signals depending on the presence / absence of wiring connection. Wiring array. This connection array can also be controlled by a control signal generator. In this case, each of the voltage levels used in the control signal generation unit has a magnitude necessary for collectively determining the control signals of a plurality of logic circuits and determining the logic of the wiring connection in the wiring array. It consists of a bit string.
[0025]
In the wiring array, floating gates and control gates are sequentially stacked on a semiconductor channel formation region with an insulating film interposed between the channel formation region and the gate as a program element for determining the presence or absence of wiring connection. A plurality of non-volatile memory elements. A nonvolatile memory element such as a flash memory having the floating gate (FG) can be formed simultaneously with the above-described νMOS, and is preferable from the viewpoint of commonality of manufacturing processes.
[0026]
In addition, the threshold voltage of the inverter or the like that constitutes the deterministic signal generation unit described above is changed by controlling the amount of charge injected into the floating gate instead of using the control signal or in addition to the control using the control signal. be able to.
In this type of semiconductor device of the present invention, at least the transistors constituting the logic determining variable threshold voltage inverter have an insulating film interposed between the channel forming region and the gate, respectively, on the semiconductor channel forming region. The nonvolatile memory element is formed by sequentially stacking a floating gate and a control gate. Further, in this case, the control signal generation unit changes the threshold voltage of the inverter by injecting and extracting charges from the floating gates of the transistors forming the variable threshold voltage inverter constituting the deterministic signal generation unit. A threshold voltage control unit is included.
[0027]
A method for controlling a semiconductor device according to the present invention is a method for controlling a semiconductor device including an insulated gate field effect transistor having a plurality of control gates, wherein a plurality of voltage levels prepared in advance are input to the insulated gate field effect transistor. The obtained output is compared with the desired output, and the voltage level is selected and / or changed with the probability of occurrence according to the degree of coincidence of the output from the result of the comparison, and the comparison, selection and / or change is repeated and desired. The voltage level for obtaining the output is specified and output as the control signal to the insulated gate field effect transistor.
[0028]
Preferably, when there are a plurality of logic circuits capable of changing the operation logic including the insulated gate field effect transistor in the deterministic signal generation unit, and the entire logic circuit is configured thereby, the voltage level prepared in advance is A bit string corresponding to the number of logic circuits and having a size necessary for connection and input selection between the logic circuits is used.
[0029]
In the logic determination method of the present invention, it is preferable that learning can be achieved by combining several controls shown below alone or in combination.
(1) The threshold signal storage type inverter that can hold the threshold voltage once set even when no voltage is applied is used as the deterministic signal generation unit, and the threshold voltage of the threshold voltage storage type inverter is calculated. Then, the voltage level is specified while repeating the calculation, comparison, selection and / or change.
(2) After the logic of the logic circuit is determined, the threshold voltage of the threshold voltage storage type inverter is set in advance to an optimum value for a logic operation to be performed next time.
(3) The threshold voltage setting of the threshold voltage storage type inverter that is performed in preparation for the next logical operation after the logic determination is as many as possible combinations of voltage levels suitable for the logical operation obtained in the subsequent logic determination. Do as follows.
(4) Every time the logic is determined, the voltage level specified by the logic determination is stored, and when the logic is newly determined, the threshold voltage of the threshold voltage storage type inverter to be performed prior to this is determined. In the setting, a threshold voltage is set such that a voltage level that achieves the most frequently used logical operation among the voltage level group stored in advance is obtained.
(5) Every time the logic is determined, the voltage level specified by the logic determination is stored, and when the logic is newly determined, the voltage level that is used most frequently among the previously stored voltage levels. In order, the calculation, comparison, selection and change are performed.
[0030]
Further, it is preferable that at least the converted input signal, the internal signal of the logic determination signal, and the signal indicating the voltage level are multi-valued to three or more values or an analog signal because efficiency can be further improved.
[0031]
The semiconductor device of the present invention described above is not a simulation but a semiconductor device that is embodied so as to be actually realizable and to which the GA technique is applied by means.
As an object to which the GA technique is applied, the semiconductor device of the present invention has a νMOS or a logic circuit with a simple configuration that can change an arithmetic logic using the νMOS. When the application target is a logic circuit, the GA method is applied to generation of a control signal for obtaining a desired logic operation. Specifically, the control signal generation unit performs an autonomous process based on an actual operation result. Generate a control signal.
[0032]
A combination of this logic circuit and logic control by the GA technique makes it possible to realize a large-scale IC whose function is changed / expanded according to the application. This is because the function is fixed in a normal logic circuit, and design elements such as optimal wiring are added to it, so if the function is changed, the optimal design point will go wrong, leading to a malfunction. In the logic determination according to (1), normal operation is reliably guaranteed at the individual logic circuit level, and the operation accuracy is remarkably high.
In the application example of the conventional GA technique, the GA technique is used only for accurately operating a function in a predetermined program state. In the present invention, in addition to ensuring normal operation, the function itself is changed. The GA method is used for the above, so the flexibility and diversity in the operation of the genetic algorithm is high.
[0033]
When this logic determination method is applied to inter-logic circuit control including connection and input selection between a plurality of logic circuits, the operation accuracy is increased and the efficiency is increased in the entire block composed of the plurality of logic circuits or the entire integrated circuit. . Further, a simple circuit (logic circuit) is used, and the connection array for connection is also simple.
In addition, since the logic circuit is versatile, it can be used by replacing a logic circuit that is defective and inoperable with another unused logic circuit while changing its function as necessary. There is a characteristic in which a defective portion is not automatically used, that is, self-defect avoidance, which is impossible with a conventional logic IC having a fixed function. It should be noted that conventional devices capable of changing functions, such as PLDs, rely on large-scale arrays for function changes, and it takes time to change functions, so self-defect avoidance is impossible.
Further, when there is a change in the surrounding environment, such as a temperature change, input signal deterioration or noise environment deterioration, a control signal capable of obtaining a desired calculation result in that environment is given to each logic circuit. Therefore, it can adapt autonomously without malfunctioning, that is, has environmental adaptability. For example, due to these environmental changes, even if there is no operation margin in the conventional configuration, or even if the logic of NAND and AND reverses, for example, the present invention controls the logic circuit so that a correct solution can be obtained. The probability of malfunction is drastically reduced.
Furthermore, the addition of some of the learning functions listed above and some of the controls that increase the efficiency can simplify the circuit itself and also add preliminary parallel processing to change the control signal range. Therefore, the processing speed is naturally improved while repeating the same logical operation. This creates room for expansion of function or performance.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor device and the control method thereof according to the present invention are different from those having functions changed by software such as a conventional computer, or function changes depending on a memory array, such as PLD. For example, by changing the function (logic) of the unit logic circuit itself, the system (semiconductor device and its control method) more optimal in terms of speeding up the processing speed and functionality due to the parallelism of the operation Realization is possible.
[0035]
The present invention proposes a system optimal for “evolving hardware” from the level of the structure of a semiconductor device and its control method. That is, the semiconductor device of the present invention has a hardware configuration incorporating a logic circuit composed of νMOS, νMOS or the like and capable of changing the arithmetic logic, and its operation means. In the control method of the present invention, for example, in addition to the logic determination operation method of the logic circuit, the improvement and control method of νMOS that can further improve the efficiency of the operation, the control method that can achieve high efficiency, or the control with self-learning A new method is proposed.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, a method for controlling a semiconductor device according to the present invention will be described by taking as an example a case where logic determination of a logic circuit is controlled using a control means provided therein. However, the control method of the present invention is not limited to logic determination control, but can be widely applied to νMOS characteristic control (for example, threshold voltage setting / change control), and is limited to control by internal means. In addition, the case of controlling from the outside of the semiconductor device is also included.
[0036]
First embodiment
FIG. 1 is a configuration diagram showing a main part of the semiconductor device according to the present embodiment.
The semiconductor device 1 includes a logic circuit 10, a GA operation unit 20 (corresponding to a “control signal generation unit” of the present invention), and a memory unit 30.
[0037]
In this embodiment, as a basic device (logic circuit 10) for constructing an evolution system, a νMOS described in the following document and published by Tohoku University, and a logic circuit (software / hardware circuit, hereinafter referred to as SH) using the νMOS are described. (Abbreviated as a circuit).
[0038]
Reference (3): Shibata, T. and T. Ohmi, “An Intelligent MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations,” IEDM, 1991.
Reference (4): Naoshi Shibata, “A new concept MOS transistor, realizing a neuron function by itself”, Nikkei Microdevice, January 1992, p101.
Reference (5): Shibata, T., T. Ohmi, “Real-Time Rconfigurable Logic Circuits Using Neuron MOS Transistor”, ISSCC, p236, 1993.
[0039]
[ΝMOS]
FIG. 2 shows a cross-sectional structure of the νMOS.
In the νMOS, a gate electrode of a normal MOS transistor is in an electrically floating state (hereinafter referred to as a floating gate or simply FG), and a plurality of control gates (hereinafter referred to as control gate or simply CG) capacitively coupled thereto. ). In FIG. 2, reference numeral 100 denotes a semiconductor substrate, 102 denotes a source impurity region, 104 denotes a drain impurity region, 106 denotes a gate insulating film, and 108 denotes an inter-gate insulating film.
In accordance with a signal applied to the control gate CG, the potential φf of the floating gate FG rises due to capacitive coupling, and the transistor is turned on when the potential φf exceeds a certain gate threshold voltage.
At this time, the floating gate potential φf is represented by the sum of values obtained by weighting the control gate application voltages V1 to Vn according to the capacitance ratio, as shown by an equation in FIG. By utilizing this characteristic and combining a νMOS transistor with an nMOS and a pMOS, a circuit having various functions such as a DA converter and a variable threshold voltage inverter can be easily configured.
[0040]
[SH circuit (software / hardware circuit)]
1 is a logical operation circuit that outputs Vout in response to 2-bit binary input signals I1 and I2, and AND, OR, NAND, and SH in accordance with control signals Va, Vb, and Vc. All 16 Boolean functions such as NOR can be calculated.
[0041]
The circuit configuration of the present embodiment includes a 2-bit DA converter that constitutes an “input converter 2” (input unit), and a 4-input variable threshold voltage inverter (calculation) that constitutes a “variable arithmetic unit 6” (output unit). The variable threshold voltage inverter 8) and the two-input variable threshold voltage inverters A to C constituting the “determining signal generator 4” are roughly divided. Each part uses the above-mentioned νMOS transistor in the configuration as shown in FIG.
The D-A converter at the input section is connected to the power supply voltage V_ddThe nMOS 2a and the pMOS 2b are connected in series between the ground potential GND and the ground potential GND. The floating gate FG2 is common, and the control gates CG21 to CG23 are arranged in three pieces. Input signals I1 and I2 are applied to the first and second control gates CG21 and CG22, respectively, and the third control gate CG23 is grounded.
[0043]
In the DA converter having such a configuration, the area ratio of the first and second control gates CG21 and CG22 is 1: 2, and the output is taken out from the commonly connected source of the nMOS 2a and the pMOS 2b. Since it is a source follower connection, a combination of input signals I1 and I2 (binary signals) (0, V_dd/ 4,2V_dd/ 4, 3V_dd/ 4).
[0044]
The two-input variable threshold voltage inverters A to C each have a power supply voltage V as shown by the inverter A in FIG._ddThe pMOS 4a and the nMOS 4b are connected in series between the ground potential GND and the ground potential GND. The floating gate FG4 is common, and two control gates CG41 and CG42 are arranged. The first control gate CG41 is applied with the output of the DA converter (input changing unit 2) (the input signal after conversion), and the control gate CG42 has the GA operation unit for each of the inverters A, B, and C. Control signals Va, Vb and Vc from 20 are input.
[0045]
The two-input variable threshold voltage inverters A to C having such a configuration are inverters in which the floating gate FG4 (corresponding to a normal gate electrode) is commonly connected and the output is taken out from the commonly connected drains of the pMOS 4a and the nMOS 4b. Connected. Also, since the area ratio of the first and second control gates CG41 and CG42 is 1: 1, the inverted voltages Vinv (a) to Vinv (c) of the two-input variable threshold voltage inverters A to C are For example, in inverter A, Vinv (a) = V_ddIt is designed to be −Va or the like. Therefore, in accordance with the combination of the threshold voltage determined by the values of the control signals Va, Vb, and Vc and the voltage level of the input signal (multilevel signal) after DA conversion, the two-input variable threshold voltage inverters A to The output voltages of C (hereinafter also referred to as logic determination signals) V2, V3, and V4 are 0 or V, respectively._ddTakes the value of
[0046]
On the other hand, as shown in FIG._ddThe pMOS 8a and the nMOS 8b are connected in series between the ground potential GND and the ground potential GND. The floating gate FG8 is common, and the control gates are CG (1), CG (2), CG (3), CG (4). The four νMOS configurations are arranged. The output voltage V1 (converted input signal) of the DA converter (input changing unit 2) is applied to the first control gate CG (1), and the control gates CG (2) to (4) Logic decision signals V2, V3, and V4 of two-input variable threshold voltage inverters A, B, and C are applied, respectively.
[0047]
The four-input variable threshold voltage inverter 8 has an inverter connection in which the floating gate FG8 is connected in common and the output is taken out from the commonly connected drains of the pMOS 8a and the nMOS 8b. In addition, since the area ratio of the first to fourth control gates CG (1) to CG (4) is 4: 2: 1: 1, the coupling capacitances C1 to C4 of the respective gates are the total capacitance. Can be expressed as C1 = Ctot / 2, C2 = Ctot / 4, and C3 = C4 = Ctot / 8, respectively. With the control gates CG (2) to CG (4), the threshold voltage Vinv (8) of the four-input variable threshold voltage inverter 8 is eight combinations, and the capacity ratio is 0, Ctot / 8, 2Ctot / 8 , 3Ctot / 8, 4Ctot / 8, and the value is given by the following equation (1).
[0048]
[Expression 1]
Vinv (8) = V_dd-2 (V2 / 4 + V3 / 8 + V4 / 8) (1)
[0049]
Depending on the combination of the threshold voltage Vinv (8), which is determined by these voltages V2 to V4 and can take 5 values, and the voltage level V1 of the input signal (multilevel signal) after DA conversion, the 4 inputs can be varied. ON / OFF of the threshold voltage inverter 8 is controlled. The output of the 4-input variable threshold voltage inverter 8 is taken out as an output signal Vout through the inverter 12.
[0050]
In this 4-input variable threshold voltage inverter 8, the operation logic is determined by the combination of logic determination signals V2 to V4 generated by the values of the control signals Va, Vb, Vc applied from the GA operation unit 20, and the input signals I1, I2 For the combination of the two values (“1” and “0”), the power supply voltage V that matches the calculation result based on a predetermined logic from the output signal Vout._ddA combination of (corresponding to “1”) and ground potential (corresponding to “0”) is obtained.
[0051]
For example, in the relationship between the input signal (I1, I2) and the output signal Vout shown in FIG. 4A, the control signals (Va, Vb, Vc) are (0, 0, V)._dd) Is entered.
When the control signal Va is 0, the converted input signal V1 is (0, V_dd/ 4,2V_dd/ 4, 3V_dd/ 4), the logic determination signals V2 to V4 are all V_ddIt becomes. Further, the control signal Va is V_ddWhen the converted input signal V1 is (0, V_dd/ 4,2V_dd/ 4, 3V_dd/ 4), the logic determination signals V2 to V4 are all 0. That is, the input signal V1 is (0, V_dd/ 4,2V_dd/ 4, 3V_dd/ 4), the logic determination signal (V2, V3, V4) is still (V_dd, V_dd, 0), and the threshold voltage Vinv (8) of the 4-input variable threshold voltage inverter 8 shown in the above equation (1) is V_ddNo change at / 4.
As a result, when the input signal V1 is “0”, the inverter 8 is not inverted, so that Vout becomes “0”, but V1 is (V_dd/ 4,2V_dd/ 4, 3V_ddIn all cases, the inverter 8 is inverted and Vout becomes “1”. That is, the output signal Vout is “0” only when the input signals (I1, I2) are (0, 0), and the output signal Vout is “1” (V_ddOR logic output is obtained.
[0052]
Similarly, (Va, Vb, Vc) = (V_dd/ 4, V_dd/ 4, V_dd) XOR logic, (Va, Vb, Vc) = (V_dd, V_dd, 0) is AND logic. FIG. 4B collectively shows the relationship between the combinations of (Va, Vb, Vc) thus obtained and Vout at that time.
In this way, in the binary 2-input (4-value) logic circuit 10 (SH circuit), the variable threshold voltage inverter 8 for operation is constituted by a 4-input νMOS inverter, and each of them has a 5-value control signal (Va, By generating a binary signal (logic determination signal) from Vb, Vc) and thereby driving the three threshold voltage control electrodes of the 4-input νMOS inverter, an output expressing all 16 functions can be obtained. it can.
[0053]
Similarly, if the logic circuit is configured to support binary 3 inputs (8 values), 256 functions can be arbitrarily specified, and if it supports binary 4 inputs (16 values), 25536 functions can be specified arbitrarily. Can be computed.
[0054]
[GA operation unit (control signal generator)]
Next, a specific configuration example of the GA operation unit 20 in FIG. 1 and its operation (GA operation) will be described.
FIG. 5 is a block diagram illustrating a specific configuration example of the GA operation unit 20.
The GA operation unit 20 of this example determines the control signals Va to Vc to values suitable for an actual logic circuit. From the comparison unit 21, the selection unit 22, the change unit 23, the control unit 24 and the output unit 25. It is configured.
The GA operation unit 20 performs reselection and change of the numerical sequence based on the result obtained when the numerical sequence selected from the prepared numerical sequence group is input to the logic circuit 10 of FIG. The numerical sequence group is autonomously converged repeatedly until the control signals Va to Vc from which the calculation results are obtained are generated. In the name of GA operation, when a series of these operations considers a numerical sequence as a gene, the fitness of the DNA sequence is evaluated (comparison), and the numerical sequence is selected with the probability of occurrence according to the fitness. (Selection), the DNA sequence (bit string) is crossed or mutated (changed), recombined with the gene again, and similar to the process of genetic evolution in which the above procedure is repeated again.
The detailed operation of each component will be described in the following GA operation.
[0055]
[GA operation]
FIG. 6 is a flowchart showing a procedure for determining the logic of the SH circuit by using a single SH circuit and a genetic algorithm (GA) in order to explain the operation method of the evolution system using νMOS. is there. Here, as an example, derivation of an OR circuit is described.
[0056]
In the 2-bit input SH circuit 10 shown in FIG. 1, each of Va, Vb, and Vc has (0, V_dd/ 4,2V_dd/ 4, 3V_dd/ 4, V_dd) Is added. If this is replaced with a binary value, each control signal has 3 bits (provided that there is redundancy for 3 values), and a total of 9 bits of information are required.
[0057]
In this example, 9 bits that determine this logic are regarded as chromosomes in GA. That is, the values (0, V) that the control signals Va, Vb, Vc can take._dd/ 4,2V_dd/ 4, 3V_dd/ 4, V_dd) Correspond to (000, 001, 010, 011, 100), respectively, and the sequence (aaa, bbb, ccc) for these three terminals is a chromosome. Here, a to c are “0” or “1”, and the control signals are represented by Va = (aaa), Vb = (bbb), and Vc = (ccc).
In step ST1 of FIG. 6, several types of these chromosomes are prepared as an initial state (only four types are illustrated in FIG. 6). In the configuration example of FIG. 5, this chromosome extraction is achieved, for example, by controlling the memory unit 30 and the output unit 25 by the control unit 24 and sequentially performing output control of a numerical sequence (chromosome).
[0058]
In step ST2, the fitness S of the prepared chromosome (control signal) is evaluated. Specifically, in the example of FIG. 5, a numerical sequence (chromosomes) sequentially output from the output unit 25 is divided into control signals Va, Vb, and Vc into the logic circuit 10 and input to each control terminal, and the output signal Vout at that time Is fed back to the comparison unit 21. In addition, a desired calculation result (output signal Vout ′) is sent from the memory unit 30 to the comparison unit 21 under the control of the control unit 24.
The comparison unit 21 compares the two output signals Vout and Vout ′, and determines the degree of coincidence for each of the output signals D1 to D4 (see FIG. 4) corresponding to the combination of the input signals. At this time, if all the output signals D1 to D4 match, the fitness is 4, and if they do not all match, the fitness is 0.
For example, in the first chromosome 1 exemplified in FIG. 6, (Va, Vb, Vc) = (001, 011, 011), and referring to the truth table in FIG. Since this is an output, the desired OR and the output signals D1 to D4 do not match, so the fitness S is determined to be “0”. Similarly, chromosome 2 in FIG. 6 is determined to have a fitness of 1 with 1 output matched, fitness 2 with 2 outputs matched to fitness 2, and chromosome 3 matched with 3 outputs to fitness 3.
[0059]
If there is even one chromosome with fitness level 4, this chromosome is determined as a correct control signal in order to obtain a desired calculation result in the actual logic circuit 10, and the flow ends.
[0060]
If the fitness level 4 does not exist, the flow proceeds to step 3 and a set of chromosomes is selected with a probability corresponding to the obtained fitness level S. This selection is executed by the selection unit 22 that has received the fitness information via the control unit of FIG. For example, in the example of FIG. 6, a pair of chromosome 4 having the highest fitness and a chromosome 3 having the next highest fitness is selected with a probability of 1/2, and a pair of chromosome 2 and chromosome 2 having the third highest fitness is selected. The pair of chromosomes 2 and 3 is selected with a probability of 1/4. The selected chromosome set is sent to the changing unit 23. As a result of this chromosome manipulation, the lower the fitness, the more natural the selection will be missed, and the higher the fitness, the higher the existence probability.
[0061]
In step ST4, for example, in the changing unit 23 in FIG. 5, bit crossover or data mutation is executed on the selected chromosome set. “Bit crossing in this example” means that if there is a different bit between each chromosome set, only one bit is exchanged for each of Va to Vc. Although not specifically implemented in the example of FIG. 6, “data variation” refers to, for example, inverting only one arbitrary bit of a newly created new chromosome for each of Va to Vc.
A new chromosome is generated by bit crossover or data variation, and this is sent to the output unit 25 of FIG.
[0062]
In step ST5, for example, in the output unit 25 of FIG. 5, the old chromosome group is replaced with a new chromosome group, and the first generation change is completed. Next, the flow returns to step ST2 again, and the cycle (generation change) of fitness S evaluation (ST2), chromosome set selection (ST3), bit crossover or data mutation (ST4) is changed to 100% fitness (Fig. In example 6, the procedure is repeated until a chromosome with fitness 4) is obtained.
A chromosome having a fitness of 100% is stored in the memory unit 30 and used as a control signal for the operation of the logic circuit as necessary.
[0063]
The above explanation is an example of GA application, and an optimal means is selected for the initial number of chromosomes, fitness evaluation method, chromosome selection method, and bit cross data conversion method according to the use situation.
Further, the change of the function of the logic circuit is easily achieved by simply changing the desired calculation result read out from the memory unit 30 by the control unit 24 and executing the above-described procedure.
Further, when the logic determination is repeated for the same logic circuit and the same logic circuit is often used in the same logic function, when preparing a numerical sequence in step ST1, a chromosome is selected from the one with the highest use frequency. By doing so, it is possible to specify a desired numerical sequence at a stage where the number of cycles of generation change is small. That is, it is possible to improve efficiency by providing a learning function for the numeric string selection.
[0064]
The semiconductor device of the present embodiment is a semiconductor device to which the GA technique is applied by means that are actualized not by simulation but by actual means. The logic circuit of the present semiconductor device has a simpler configuration than that of a conventional PLD or the like, for example, in which the arithmetic logic can be changed. In addition, since the operation logic can be determined only by changing the control signal, it is possible to operate while changing the logic in real time.
In the present embodiment, the GA technique is applied to determine the control signal, and the GA operation unit (control signal generation unit) is an autonomous process based on the actual calculation result, and the control signal adapted to the actual logic circuit. Is generated. In normal logic circuits, functions are fixed, and design elements such as optimal wiring are added to them. Therefore, if the functions are changed, the optimal point of the design goes wrong, leading to malfunctions. In the confirmation, the normal operation is reliably ensured at the individual logic circuit level, and the operation accuracy is remarkably high.
In addition, when there is a change in the surrounding environment, such as a temperature change, input signal deterioration, or noise environment deterioration, a control signal that can obtain a desired calculation result in that environment is given to the logic circuit. , It can adapt autonomously without malfunction, that is, it has environmental adaptability. For example, due to these environmental changes, even if there is no operation margin in the conventional configuration, or even if the logic of NAND and AND reverses, for example, the present invention controls the logic circuit so that a correct solution can be obtained. The probability of malfunction is drastically reduced. In addition, in this embodiment, since the GA method can be applied to the change of the function itself, the flexibility and diversity in genetic algorithm operation is extremely high.
[0065]
Second embodiment
In the first embodiment described above, attention is focused on one SH circuit for the main purpose of explaining a method of applying GA to the SH circuit. In this case, there is an advantage of high operation accuracy with respect to design, process factors, and environmental factors. However, when there is no fear of malfunction due to these factors, the bit string that actually determines the logic of one SH circuit is the truth. Since it is easily understood in accordance with the value obtained from the value table, the advantage of using the GA for the logic determination is thin. However, when a large-scale circuit is formed using a plurality of SH circuits, it is not easy to obtain all bit strings for determining a desired circuit, and therefore a logic determination method by GA becomes more important.
[0066]
In the present embodiment, a semiconductor device using a combination of a plurality of SH circuits and wiring connection means, and a method for automatically constructing the combination circuit using GA will be described. At this time, a multiplexer circuit is illustrated as a simple combinational circuit, and the configuration and generation (including automatic construction) operation will be described.
[0067]
FIG. 7 is a diagram showing a multiplexer as an example of the logic circuit of the present embodiment. FIG. 8 is an equivalent circuit diagram of the multiplexer of FIG.
As shown in FIG. 7, the multiplexer 40 of this example selectively outputs any one of four data I1 to I4 input to four input terminals by a combination of two address bits A1 and A2. 6 input multiplexers (6 multiplexers). The 6 multiplexer 40 has six inverters INV1 to INV6 for inverting the input signals A1, A2 and I1 to I4, respectively, at the first stage on the equivalent circuit. The outputs of the inverters INV1 to INV6 are connected to four AND circuits AND1 to AND4 that input three signals among the control signals A1 and A2, their inverted signals A1_ and A2_, and the inverted signals of the input signals I1 to I4. . A1_, A2, I3_ are input to the AND circuit AND1, A1_, A2_, I4_ are input to the AND circuit AND2, A1, A2, I1_ are input to the AND circuit AND3, and A1, A2_, I2_ are input to the AND circuit AND4. Is done. The outputs of these AND circuits AND1 to AND4 are connected to the NOR circuit NOR at the final stage.
[0068]
In the multiplexer 40 having such a configuration, when (A1, A2) = (0, 0), it is only the AND circuit AND2 that the output of the four AND circuits may become 1, and therefore, the input The output of the multiplexer 40 changes according to the logic state of the signal I4. That is, when (A1, A2) = (0, 0), the input signal I4 is selected and output.
Similarly, the input signal I2 is selected when (A1, A2) = (1, 0), the input signal I3 is selected when (A1, A2) = (0, 1), and (A1, A2) = ( 1, 1), the input signal I1 is selected and output.
[0069]
FIG. 9 shows an arrangement pattern serving as a base of the combination of SH circuits, taking the 6 multiplexer 40 shown in FIGS. 7 and 8 as an example.
In FIG. 9, SH1 to SH3 are logic circuits (SH circuits) similar to those shown in FIG. 1, and these SH circuits SH1 to SH3 constitute the NOR circuit NOR at the final stage in FIG. That is, two 2-input OR circuits are provided in parallel for SH1 and SH2, and a single 2-input NOR circuit having the outputs of the 2-input OR circuit as inputs is realized by SH3.
For such an arrangement of a plurality of SH circuits, there is a connection array for selecting a pin to be input to each SH circuit. The connection array can specify its connection pattern for each intersection of the matrix of data input pins and SH circuit input pins, and the input signal to the SH circuit is the AND logic of the pins connected on the SH circuit input pins. That is, this connection array implements the four AND circuits AND1 to AND4 in FIG. 8 and their input selection.
Furthermore, in order to connect each SH circuit, the feedback from the output of any SH circuit can be connected to the input pin of each SH circuit, and this can also be specified in a matrix as described above.
In addition to these inputs, there is a matrix for designating control signals (Va, Vb, Vc) to be input to the control terminals of the respective SH circuits. As described in the first embodiment, this matrix is obtained by controlling the control voltage value (0, V by the GA operation unit 20 (not shown)._dd/ 4,2V_dd/ 4, 3V_dd/ 4, V_dd), An optimum voltage can be selected in order to obtain a desired calculation result (here, the circuit logic of FIG. 8) by the logic determination method using GA, thereby determining the logic of the SH circuit. FIG. 9 exemplifies a case where each SH circuit can operate with a normal logic determination result according to the truth table. However, in FIG. 9, the connection point of the control voltage is not provided with a means for actually setting the connection, but merely shows a control voltage selection pattern by the GA operation unit 20. On the other hand, means for setting the connection is actually provided at the connection point between the data input pin and, in some cases, the feedback control pin.
[0070]
Several means for connecting these matrices are conceivable, but in consideration of frequent circuit rewriting, a flash memory element type switch is desirable. Since the flash memory element has a floating gate type MOS structure similar to the νMOS shown in FIG. 2, it can be formed at the same time as the νMOS constituting the SH circuit in manufacturing the device. This is extremely advantageous.
Although it depends on the rewriting method, the number of rewrites is also 1 × 10.⁶This is advantageous in this respect.
[0071]
In the circuit having such an arrangement, the connection information of each array and the control voltage information of the SH circuit may be confirmed by a separately provided GA operation unit. However, when the two pieces of information are regarded as one chromosome, Thus, it is possible to determine the wiring connection and the logic function at the same time with one GA operation unit.
In the case of this example, that is, in the construction of 6 multiplexers, 3 SH circuit blocks (SH1 to SH3) are used. Thus, the number of chromosomes is 72 bits for the connection array of data input pins, 24 bits for the feedback array, The total number of bits is 123, including 27 specified bits. The designation of the control voltage is not determined by the presence or absence of connection of each matrix, but, as in the first embodiment, 3 bits per control terminal, 9 bits for each SH circuit, and a total of 3 SH circuits. Determined by 27 bits.
[0072]
A plurality of chromosomes having such a size are prepared, and GA operation is performed on these chromosomes in the procedure shown in FIG. 6 as in the first embodiment. As a result, a circuit that finally connects the black dots in FIG. 9 is obtained as a solution.
[0073]
By using the above method, it is possible to construct a large-scale evolution system. That is, when a device (functional circuit block) that performs an optimal response in response to changes in the external environment is required, the device portion that needs to determine the logic in real time is realized by several SH circuits. If the result of the logic determination unit such as the GA operation unit that evaluates the fitness based on the block output is externally given to each SH circuit, the entire functional circuit block autonomously searches for the optimal circuit configuration and output. Can come. In the case of having a connection array, the matrix setting can be achieved by control of writing / erasing a normal nonvolatile memory element or the like, and thus the description thereof is omitted here.
[0074]
The semiconductor device according to this embodiment described above has the following advantages over the conventional example.
First, comparing this example (FIG. 9) and the configuration of the PLD (FIG. 13), the place where an AND array is used for the input unit is the same, but the circuit configuration shown in this embodiment is the logic of the PLD. A configuration corresponding to a macro is replaced with an SH circuit.
In general, PLD programming is based on an additive standard form in which a circuit is configured by a combination of AND logic and OR logic. The logic macro part is used when OR logic, XOR, or a sequential circuit is configured. A circuit such as a flip-flop is included. Therefore, even a simple circuit configuration such as a 6 multiplexer requires a large-scale circuit group such as a logic macro.
However, in the circuit configuration shown in the present embodiment, the logic macro part is replaced with an SH circuit, and the gate scale of the device can be kept small.
[0075]
In this embodiment, since the SH circuit can set an arbitrary Boolean function, the entire circuit configuration is not limited to the additive standard form. Therefore, the final overall circuit configuration is simplified compared to the case of PLD. In addition, when a genetic algorithm is used, it means that a desired circuit can be formed with a smaller number of chromosomes, and an evolution system with high flexibility and diversity can be constructed.
[0076]
In this embodiment, since the power supply switching circuit is simply used for switching the control voltage, it is possible to perform switching at a much higher speed than the change in the connection of the PLD. In an evolution system using PLD, it is difficult to construct a system that changes in real time because it is difficult to perform high-speed programming. However, in this embodiment, hardware programming can be performed at high speed, and the system changes in real time. It is possible to build a system that does this.
[0077]
Finally, some points that can be changed in this embodiment will be pointed out.
[0078]
First, in the above description, 9 bits (a total of 27 bits for three SH circuits) are used for designating the control voltage of one SH circuit as in the first embodiment. If one is selected, 4 bits for each SH circuit, 12 bits in total are sufficient. This point is the same in the first embodiment.
Further, in the circuit configuration example of FIG. 9, a 2-input SH circuit is used. However, if a multi-input type SH circuit having a large number of input terminals such as 3 terminals or 4 terminals is used, the circuit is further simplified. It is possible to build a highly flexible and diverse system.
[0079]
In the circuit configuration shown in the present embodiment (FIG. 9), an AND array is used for the input unit, but a configuration in which an external input is directly connected to the SH circuit without using them is also possible. In the above description, each AND circuit in FIG. 8 is realized by a connection array. However, this can be replaced by, for example, a plurality of SH circuits that are function-designated as a multi-input AND. Further, in principle, the feedback control can be replaced by a plurality of SH circuits.
[0080]
In the above description, only the combinational circuit is mentioned. However, if a circuit such as a flip-flop is further combined with the circuit configuration of FIG. 9, a sequential circuit configuration is also possible.
Further, the circuit configuration of FIG. 9 can be used as a programmable device similar to a PLD or FPGA by selecting a connection array and selecting a control voltage.
[0081]
Third embodiment
In the previous first (and second) embodiment, the threshold voltages of the two-input variable threshold voltage inverters A to C are set / changed by the control voltages Va to Vc (FIG. 3). In this embodiment, the threshold voltage can be stored not as an external state but as an internal state by injecting a charge into the floating gate FG constituting the variable threshold voltage inverter or by extracting the charge from the FG.
The method of holding the memory by the charge amount of the floating gate is in principle the same as the data storage / erasing method of flash memory and EEPROM currently in practical use.
[0082]
FIG. 10A is a plan view of a two-input variable threshold voltage inverter according to this embodiment, and FIG. 10B is a cross-sectional view thereof.
In this two-input variable threshold voltage inverter 50, an element isolation insulating film 53 is formed on the surface portion of the n-well 52 formed in the p-type semiconductor substrate 51 and the other p-type semiconductor substrate regions. Gate insulating films 54p and 54n are formed around the element isolation insulating film (pMOS active region) in the n well 52 and around the element isolation insulating film (nMOS active region) in the p-type semiconductor substrate, respectively. Yes. A common floating gate FG is stacked on the gate insulating films 54p and 54n and on the element isolation region 53 therebetween.
[0083]
This νMOS transistor does not require an external threshold voltage control signal, and therefore does not have the Va terminal shown in FIG. Instead, on the floating gate FG, a charge injection control gate CG for controlling the amount of injected charge._{W / E}Are stacked via the inter-gate insulating film 55, and the control gate CG to which the input signal after conversion from the DA converter is applied along with the inter-gate insulating film 55 forms the inter-gate insulating film 56 on the floating gate FG. Is arranged through. In the normal νMOS transistor used in the first and second embodiments, the thickness of the gate insulating film under the floating gate is normally set to a thick film of about 10 nm to 20 nm. As in the flash memory, a thin oxide film having a thickness of 10 nm or less is used.
[0084]
In the two-input variable threshold voltage inverter 50 having such a structure, the substrate is kept at 0V and the charge injection control gate CG is maintained._{W / E}When a positive high voltage (for example, about 18V) is applied to, electrons are injected from the substrate into the floating gate FG. When electrons are injected into the floating gate FG, this is negatively charged, and the apparent threshold voltage of the inverter viewed from the signal input terminal from the DA converter increases. Conversely, the charge injection control gate CG_{W / E}By applying a negative voltage to the substrate and extracting electrons from the substrate or injecting holes (positive charges) from the substrate to positively charge the floating gate FG, the apparent threshold voltage is lowered. Therefore, by controlling the charge injection amount and setting the threshold voltage in five stages, a two-input variable threshold voltage inverter that does not require an external signal can be configured. This threshold voltage becomes non-volatile so that the state does not disappear even when the power supply voltage of the chip is turned off.
Therefore, if such a threshold voltage writing operation is performed at the logic decision stage of the SH circuit, the threshold voltage, that is, the decision logic can be held as an internal state. The erasing operation is performed in the same manner as in the case of the above writing, with the direction of the electric field applied to the gate insulating film being reversed.
FIG. 11 shows a threshold voltage write / erase means, that is, a threshold voltage control means 57 together with a threshold voltage storage type two-input variable threshold voltage inverter 50.
[0085]
In the present embodiment, when the same logical function is used continuously in determining a normal logical function, the state can be maintained once the logical function is determined. Therefore, this state is common to many SH circuits. The writing / erasing control means 57 is provided, and control for rewriting a logical function at a necessary location can be performed, so that time efficiency can be improved. Further, for example, when it is desired to fix a logical function after determining a logical function capable of obtaining a desired operation result by the SH circuit by using a GA operation unit (not shown), it is possible to perform control using the write / erase control means 57.
[0086]
Fourth embodiment
In the present embodiment, the threshold voltage setting by adjusting the charge injection amount shown in the third embodiment is used together with the application of the control voltage shown in the first and second embodiments to determine the logic function. A case where control is performed will be described.
[0087]
The variable threshold voltage inverter of this embodiment is basically the same as the structure shown in FIG. However, the charge injection control gate CG shown in FIG._{W / E}Is also used as an input control gate for a threshold voltage control signal (hereinafter referred to as a shared control gate). This switching is performed by switching the switch for each operation.
In the two-input variable threshold voltage inverter of the first and second embodiments, the threshold voltage viewed from the terminal to which the converted input signal is input from the DA converter (input conversion unit 2) is controlled only by the control voltage. However, in the present embodiment, as in the third embodiment, charge injection into the floating gate is performed to increase the threshold voltage setting parameter. In this way, it is possible to limit the threshold voltage that can be controlled by the control voltage. In other words, the threshold voltage change due to the control voltage can be made insensitive or sensitive.
[0088]
For example, the threshold voltage Vinv of a two-input variable threshold voltage inverter is Vinv = V_dd−Va, the threshold voltage is reduced (for example, V_ddUsually, the control voltage Va is increased (3 V)_ddSet to / 4). However, if electrons are pre-injected into the floating gate FG, the threshold voltage is even higher even in the same bias state (for example, 2V_dd/ 4 or 3V_dd/ 4). Conversely, if holes are injected into the floating gate FG, the threshold voltage becomes lower for the same bias state.
[0089]
The charge injection into the floating gate FG and the GA operation for determining the control voltage Va are performed independently. When performing the GA operation, the dual control gate is used as a signal application terminal for controlling the threshold voltage, and the same operation as in the first or second embodiment is performed. On the other hand, when the charge is injected into the floating gate FG, the dual control gate is used as a charge injection control terminal, and a positive high voltage is applied to the control terminal for electron injection and a negative high voltage for hole injection. To do.
[0090]
By using the above method, a learning function can be added to a semiconductor device as “evolving hardware” using an SH circuit.
Hereinafter, the operation when the learning function is added will be described by taking the 6 multiplexer circuit shown in the third embodiment as an example.
[0091]
In the 6 multiplexer circuit (FIG. 9) obtained by the GA operation, finally, SH1 and SH2 become OR logic, and SH3 becomes NOR logic. Taking the OR logic in the SH circuit as an example, this logic is usually a combination of control voltages (Va, Vb, Vc) = (0, 0, V_dd). On the other hand, for example, electrons are injected into the floating gate FG of the two-input variable threshold voltage inverter A by the above method, and the threshold voltage as an internal state is set to V_ddIf the shift is made higher by / 4, the OR logic becomes (Va, Vb, Vc) = (0, 0, V_dd) Or (Va, Vb, Vc) = (V_dd/ 4, 0, V_dd) Can be achieved by combining two types of control voltages. Also, the internal state is 2V_ddIf it is shifted higher by / 4, (Va, Vb, Vc) = (2V_dd/ 4, 0, V_dd) Combination. Then, the internal state threshold voltage is further shifted to the higher side to + V_ddIf it is made above, it becomes OR logic for any Va value, and Va does not contribute to logic determination.
The same is true for the two-input variable threshold voltage inverter B, and for C, the threshold voltage is set to V_ddBy doing so, the contribution of Vc can be eliminated.
Therefore, the threshold voltages of the two-input variable threshold voltage inverters A, B, and C are set to + V_dd, + V_dd, + V_ddIf the shift is performed in advance, the SH circuit is determined to be OR logic regardless of the control voltage.
[0092]
As described above, when the GA operation shown in FIG. 6 is performed while the threshold voltage of the internal state is shifted, the number of combinations of chromosomes constituting the OR logic and the like increases, and the number of GA cycles until the logic is determined is reduced. It becomes possible.
Therefore, when the above method is applied to “evolving hardware” using GA, the learning process can be given to the hardware evolution process.
[0093]
In “Evolving hardware”, GA operations are repeated in response to external environmental changes, and optimal hardware logic is built. At this time, if the GA operation takes time, it becomes impossible to cope with the rapidly changing external environment. The conventional 6-multiplexer circuit that does not use the SH circuit described in the document (1) requires about 2000 cycles of GA operation, and therefore cannot cope with the external environment.
[0094]
In contrast, in the present embodiment, as described above, when the logic is determined by the GA operation, the threshold voltage as the internal state is changed in advance in the determined signal generation unit in the SH circuit according to the result. be able to. For this reason, by the GA operation after the next time, it is possible to increase the probability of configuring the logic and to increase the number of chromosomes forming the same logic. In other words, for frequently used logic, the degree of logic fixation can be increased according to the frequency, thereby reducing the time required for the GA operation.
[0095]
In the 6 multiplexer circuit, the threshold voltage of the two-input variable threshold voltage inverters A and B is set to V_dd/ 4,2V_dd/ 4 or 3V_ddBy shifting to a higher position by / 4, the circuit can be determined with a smaller number of cycles than normal.
Further, in FIG. 9, the threshold voltages of the two-input variable threshold voltage inverters A, B, and C of SH1 and SH2 are set to + V_dd, + V_dd, + V_ddAre set to OR logic. Therefore, only the SH3 two-input variable threshold voltage inverter needs to determine the NOR theoretical value by applying a normal control voltage, and the number of chromosome bits in the GA operation can be reduced to 1/3. Further, if SH3 is OR logic with the internal threshold voltage adjusted and the output after passing through the inverter is obtained, all logic can be determined as the internal state of the variable threshold voltage inverter. In this case, the GA operation is performed only by wiring connection, and the GA operation time becomes extremely short. Further, with respect to these wiring connections, if a floating gate type cell is used as in a normal PLD and held as a nonvolatile memory, the entire 6 multiplexer circuit can be determined as a nonvolatile state.
[0096]
Fifth embodiment
Up to the first to fourth embodiments described above, input / output to the SH circuit is binary, and inside the SH circuit is a quaternary signal (0, V_dd/ 4,2V_dd/ 4, 3V_dd/ 4), and the relationship between the input and the output is limited to the range expressed by the Boolean function. On the other hand, in the SH circuit of FIG. 1, if the variable threshold voltage inverter that constitutes the deterministic signal generation unit 4 is configured by a DA converter similar to the input conversion unit 2, All signals (internal) between the input conversion unit 2 and the variable calculation unit 6 including the signal route are configured as multi-values. Further, when the variable calculation unit 6 is also configured by a DA converter, all signals including input / output signals are multivalued.
[0097]
At this time, a terminal for changing the output level of the DA converter is used as the control signal. When the input voltage to this terminal is changed, the output signal of the DA converter becomes 0V and V_ddThe number of voltage levels is 4 (number of input signal levels after conversion) × n (number of control signal change steps). Therefore, such a configuration can increase the variety of voltage levels applied to the gate of the output unit. In the configuration in which the two-input variable threshold voltage inverter is changed to a D / A converter, the output of the D / A converter is multi-valued. Therefore, the variable threshold voltage for logic operation is changed as in the configuration of FIG. Not only can the control electrodes (2) to (4) of the inverter 8 be unified, but depending on the degree of multi-leveling, only one DA converter needs to be provided, and the configuration can be simplified. There is.
[0098]
Further, when the νMOS inverter (the variable threshold voltage inverter 8 for logic operation) of the variable operation unit 6 of the SH circuit is configured by a DA converter, the output becomes multivalued. When such a multi-value output SH circuit is applied to the system shown in FIG. 9, input / output between the SH circuits becomes a multi-value signal, and a circuit network having a very high degree of freedom can be constructed in the entire system. .
Further, if the signal in the SH circuit or the entire system is handled as analog as a means on the extension line for increasing the multi-value level, the degree of freedom of the circuit configuration is theoretically infinite. This means that diversity similar to signal processing in a living organism can be constructed, and this technology enables an evolutionary system close to that of an organism.
[0099]
Sixth embodiment
In the present embodiment, a case where “evolving hardware” is built on a semiconductor chip by integrating the first to fifth embodiments described above is shown.
[0100]
The semiconductor device (one-chip IC) of this embodiment is shown in FIG.
The semiconductor device 60 is mainly composed of three parts. The evolution hardware unit 61 using the νMOS of the first to fifth embodiments, and the GA operation unit 62 for controlling the evolution hardware unit 61 by the GA (FIG. 1). Corresponding to the GA operation unit 20) and a memory unit 63.
[0101]
The evolution hardware unit 61 is composed of a circuit group of an SH circuit and a connection array shown in the above-described embodiment, and actually exhibits autonomous adaptability (environment adaptability, self-defect avoidance, or learnability) and changes logic. It is a part that evolves while.
The GA operation unit 62 performs a series of GA operations described in detail in the first embodiment, such as chromosome fitness evaluation, chromosome selection, bit crossover, and data conversion. The GA operation unit 62 generally includes an MCU, a CPU, a dedicated DSP, or the like as means for controlling the GA operation (for example, the control unit 24 in FIG. 5).
The memory unit 63 stores chromosome data for performing GA operation, a calculation result table serving as a criterion for fitness determination, an operation program, and the like. The stored operation program can be changed from the outside. Further, in the present embodiment, threshold voltage control means for rewriting data in the memory area of the memory unit 63 or rewriting a storage element that performs connection control of the νMOS or connection array in the evolution hardware unit 61 includes The memory unit 63 is provided as a peripheral circuit.
[0102]
If a flash memory is used as the memory element constituting the memory unit 63, it can be formed simultaneously with the flash memory used for the switch in the νMOS floating gate structure and the connection array, which is advantageous in terms of manufacturing cost.
Further, the peripheral circuit of the GA operation unit 62 and the memory unit 63 can be constructed by the SH circuit and the connection array similarly to the evolution hardware unit 61. In this case, for example, control of the SH circuit that randomly changes its logic in the long term or configures the GA operation unit or the like can be achieved by operating the SH circuit other than the evolution hardware unit from the outside. At this time, not only the evolution hardware unit 61 but also the entire IC functions as “evolving hardware”, and the functions can be changed evolutionarily. Thus, what advances the whole IC autonomously or with learning ability can be called “evolving semiconductor chip”. If the analog operation shown in the fifth embodiment is applied to the evolution operation in the semiconductor chip, the degree of freedom of change becomes infinite. This means that the entire semiconductor chip behaves like a living body, and can be a central device for constructing future “computers with creativity” and “systems close to living bodies”.
[0103]
【The invention's effect】
According to the semiconductor device and the logic determination method of the present invention, it is possible to realize a variable logic circuit that does not malfunction even when a manufacturing or design margin is insufficient or an environmental change occurs. Particularly, since the logic function of the variable logic circuit is determined by generating and inputting the control signal, it is possible to follow the environmental change in real time. When this variable logic circuit is constituted by a so-called νMOS, process consistency with a non-volatile memory element having a normal floating gate is good, and the circuit configuration is simplified.
In addition, by combining a plurality of variable logic circuits, a general-purpose logic IC that changes the function according to the application while avoiding self-defects can be realized. A variable logic circuit (so-called SH circuit) having a νMOS configuration can change a logic function by inputting a control signal, so that the function can be changed at a higher speed than a case where the function is changed by a program for a conventional nonvolatile memory element.
In the semiconductor device of the present invention, by adding a learning function and further multi-leveling the signal, the control signal used (for example, the number of bits) and the circuit configuration are simplified, the efficiency is improved, and the speed is increased autonomously. Can work. As a result, the semiconductor device of the present invention can be expanded in real time in combination with the high-speed function change described above.
[0104]
In the application example of the conventional GA technique, the GA technique is used only for accurately operating the function in a predetermined program state, whereas the logic determination method of the semiconductor device of the present invention ensures the normal operation. In addition, the GA method is used to change the function itself. In addition, it is desirable that the numerical sequence (gene) given first is simple because it is a control that increases the probability of occurrence of the solution to be obtained. However, if the semiconductor device is multi-valued by adding a learning function, the logic determination cycle is accelerated. In this sense, the flexibility and diversity of genetic algorithm operations are high.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing a main part of a semiconductor device according to a first embodiment of the present invention.
2 is a cross-sectional structure diagram of a νMOS used in the semiconductor device of FIG. 1 and an explanatory diagram of a floating gate potential.
3 is a circuit diagram of a two-input variable threshold voltage inverter A provided in the semiconductor device of FIG. 1;
FIG. 4 is a table showing the input / output relationship of the SH circuit (the logic circuit in FIG. 1) and the combinations of control signals and outputs.
FIG. 5 is a block diagram illustrating a specific configuration example of a GA operation unit in FIG. 1;
FIG. 6 shows a procedure for determining the logic of an SH circuit by a genetic algorithm (GA) using one SH circuit when determining the logic of the semiconductor device according to the first embodiment of the present invention; FIG.
FIG. 7 is a diagram illustrating a multiplexer as an example of a logic circuit in a semiconductor device according to a second embodiment of the present invention.
FIG. 8 is an equivalent circuit diagram of the multiplexer of FIG.
9 is a circuit diagram illustrating an arrangement pattern serving as a base of the combination of the SH circuits of FIG. 7 using the 6 multiplexer 40 shown in FIGS. 7 and 8 as an example;
FIG. 10 is a plan view and a cross-sectional view of a two-input variable threshold voltage inverter in a semiconductor device according to a third embodiment of the present invention.
11 is a diagram showing a state in which the threshold voltage control means is connected to the two-input variable threshold voltage inverter of FIG.
FIG. 12 is a block plan view showing a schematic configuration of a semiconductor device (one-chip IC) according to a sixth embodiment of the invention.
FIG. 13 is a diagram showing a configuration of a PLD as an application example of a conventional genetic algorithm.
[Explanation of symbols]
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1,60 ... Semiconductor device, 2 ... Input conversion part, 4 ... Deterministic signal generation part, 6 ... Variable calculating part, 8, 50 ... Two-input variable threshold voltage inverter, 10 ... Logic circuit (SH circuit), 12 ... Inverter , 20, 62 ... GA operation unit (control signal generation unit), 21 ... comparison unit, 22 ... selection unit, 23 ... change unit, 24 ... control unit, 25 ... output unit, 30, 63 ... memory unit, 40 ... 6 Multiplexer, 51, 100 ... Semiconductor substrate, 52 ... n well, 53 ... Element isolation insulating film, 54n, 54p ... Gate insulating film, 55, 56 ... Inter-gate insulating film, 57 ... Threshold voltage control means, 61 ... Evolution hardware Wear part, 102 ... Drain impurity region, 104 ... Source impurity region, 106 ... Gate insulating film, 108 ... Inter-gate insulating film, FG ... Floating gate, CG ... Control gate, Va to Vc ... Control signal (Or a control voltage having a predetermined voltage level), I1, I2... Input signal, D1 to D4, Vout... Output signal, V1... Converted input signal, V2 to V4. ... Floating gate potential.

Claims (25)

An insulated gate field effect transistor having a plurality of control gates;
As means for generating a control signal to be applied to the control gate in order to obtain a desired output from the insulated gate field effect transistor, it is desired when each voltage level of the prepared voltage level group is input to the insulated gate field effect transistor. When the desired output is obtained, the voltage level at which the desired output is obtained is output as the control signal. When the desired output is not obtained, the voltage level is selected and / or changed based on the output result. And a control signal generation unit that repeats this selection and / or change until a desired output is obtained, converges the voltage level group, and outputs a voltage level at which the desired output is obtained as the control signal. apparatus. The insulated gate field effect transistor has a floating gate whose potential is determined according to an applied voltage of the plurality of control gates,
A threshold voltage control unit connected to a control gate of the insulated gate field effect transistor and configured to set or change a threshold voltage of the insulated gate field effect transistor by controlling charge injection or extraction of the floating gate; The semiconductor device according to claim 1. An input converter that converts a plurality of input signals into a voltage that takes a plurality of levels according to a combination of the logic, and outputs the converted voltage;
Including the insulated gate field effect transistor, and a logic determination signal based on a control signal applied to a control gate for inputting the control signal and a converted input signal applied to the other control gate from the input conversion unit. A deterministic signal generator to generate,
The output of the input conversion unit is connected to a signal input, the output of the determination signal generation unit is connected to a control input, and a logical operation of a predetermined function determined according to the logic determination signal received at the control input is the input conversion The semiconductor device according to claim 1, wherein a logic circuit including a variable arithmetic unit that executes the input signal after conversion by the unit is connected to the control signal generation unit. The control signal generation unit compares a calculation result obtained by inputting a plurality of voltage levels prepared in advance into the logic circuit with a desired calculation result; and
A selection unit that newly selects a plurality of voltage levels with an occurrence probability according to the degree of coincidence of the calculation results from the result of the comparison;
A change section for changing the selected voltage level;
By controlling the comparison unit, the selection unit, and the change unit, the voltage level at which the desired logic decision signal can be obtained while repeating the calculation, comparison, selection, and change is specified, and the decision signal is generated as the control signal. The semiconductor device according to claim 3, further comprising a control unit that outputs the signal toward the unit. The deterministic signal generating unit includes the insulated gate field effect transistor, and includes a logic threshold variable threshold voltage inverter that inverts at a threshold voltage determined according to the control signal and the converted input signal,
The variable arithmetic unit sets a predetermined logic function by changing the threshold voltage to any one of a plurality of stages according to the input logic determination signal, and whether to invert according to the converted input signal. 4. The semiconductor device according to claim 3, further comprising a variable threshold voltage inverter for calculation that outputs a desired calculation result or an inverted output thereof. The two variable threshold voltage inverters for calculation and logic determination and the input conversion unit are divided into two types, a p-type channel and an n-type channel, connected in series between a first power supply voltage and a second power supply voltage. Consists of insulated gate field effect transistors,
The two transistors include a floating gate that extends on a gate insulating film formed on a channel formation region of the semiconductor and is commonly connected between the two transistors,
The floating gate or the connecting portion of the floating gate is disposed through an insulating film, and the potential of the floating gate is controlled in multiple stages by a combination of applied voltages to set the output voltage level or change the threshold voltage. A plurality of control gates,
The two transistors of the input conversion unit are connected to a source follower that takes out an output from a series connection point where the sources are connected to each other.
The semiconductor device according to claim 5, wherein the two variable threshold voltage inverters for calculation and logic determination are connected to each other by taking out an output from a series connection point where drains are connected to each other. The deterministic signal generation unit, the variable calculation unit, and the input conversion unit include two insulated gate field effect transistors of a p-type channel and an n-type channel connected in series between the first power supply voltage and the second power supply voltage. Consisting of
The two transistors include a floating gate that extends on a gate insulating film formed on a channel formation region of the semiconductor and is commonly connected between the two transistors,
The floating gate or the connecting portion of the floating gate is disposed through an insulating film, and the potential of the floating gate is controlled in multiple stages by a combination of applied voltages to set the output voltage level or change the threshold voltage. A plurality of control gates,
Source follower connection is made in which at least one of the input conversion unit, the deterministic signal generation unit, and the variable calculation unit takes an output from a series connection point where sources are connected,
4. The semiconductor device according to claim 3, wherein the deterministic signal generation unit or the variable calculation unit that is not connected to a source follower is connected to an inverter that extracts an output from a series connection point where drains are connected to each other. A semiconductor device having a plurality of logic circuits, and a wiring array in which connection between at least the plurality of logic circuits and selection of an input signal can be programmed depending on the presence or absence of wiring connections,
Each of the plurality of logic circuits converts an input signal into a voltage having a plurality of levels corresponding to a combination of the logic, and outputs the converted voltage.
A confirmation signal generation unit that generates a logic determination signal based on a control signal applied to the control input and a converted input signal applied to the signal input from the input conversion unit;
The output of the input conversion unit is connected to a signal input, the output of the determination signal generation unit is connected to a control input, and a logical operation of a predetermined function determined according to the logic determination signal received at the control input is the input conversion A semiconductor device comprising: a variable arithmetic unit that executes the input signal after conversion by the unit. The insulated gate field effect transistor constituting the logic circuit has a floating gate whose potential is determined according to the applied voltage of a plurality of control gates,
A threshold voltage control unit connected to the control gate of the insulated gate field effect transistor and configured to set or change a threshold voltage of the insulated gate field effect transistor by controlling charge injection or extraction of the floating gate; The semiconductor device according to claim 8. In the wiring array, floating gates and control gates are sequentially stacked on a semiconductor channel formation region with an insulating film interposed between the channel formation region and the gate as a program element for determining the presence or absence of wiring connection. The semiconductor memory device according to claim 8, comprising a plurality of nonvolatile memory elements. The semiconductor device according to claim 8, wherein the connection array includes a region for programming logic determination of a predetermined function for each logic circuit depending on presence / absence of wiring connection. As a means for generating the control signal to be applied to the logic circuit, when a desired output is obtained when each voltage level of the prepared voltage level group is input to the deterministic signal generator, the desired output is obtained. Is output as the control signal, and when a desired output cannot be obtained, the voltage level is selected and / or changed based on the output result, and this selection and / or change is output as desired. The semiconductor device according to claim 8, further comprising: a control signal generation unit that repeatedly converges the voltage level group until a desired output is obtained and outputs a voltage level at which a desired output is obtained as the control signal. Each of the voltage levels used in the control signal generation unit performs a determination of control signals for a plurality of logic circuits at once, and a bit string having a size necessary for determining a logic of wiring connection in the wiring array. The semiconductor device according to claim 12, comprising: The voltage level group to be prepared by the control signal generation unit, and a memory unit that stores at least the selection or change criteria.
13. The semiconductor memory according to claim 12, wherein when at least one of the memory unit and the control signal generation unit has a logic circuit therein, the logic circuit portion is configured by a logic circuit capable of changing the arithmetic logic. apparatus. The voltage level group to be prepared by the control signal generation unit, and a memory unit that stores at least the selection or change criteria.
The semiconductor memory device according to claim 12, wherein the memory unit, the control signal generation unit, the plurality of logic circuits, and the connection array are integrated on a single semiconductor substrate. A method of controlling a semiconductor device including an insulated gate field effect transistor having a plurality of control gates,
The output obtained when a plurality of voltage levels prepared in advance are input to the insulated gate field effect transistor is compared with a desired output,
The voltage level is selected and / or changed with the occurrence probability according to the degree of coincidence of the output from the result of the comparison,
A method for controlling a semiconductor device, wherein a voltage level for obtaining a desired output is identified while repeating the comparison, selection and / or change, and is output to the insulated gate field effect transistor as the control signal. An input converter that converts a plurality of input signals into a voltage that takes a plurality of levels according to a combination of the logic, and outputs the converted voltage;
Including the insulated gate field effect transistor, and a logic determination signal based on a control signal applied to a control gate for inputting the control signal and a converted input signal applied to the other control gate from the input conversion unit. A deterministic signal generator to generate,
The output of the input conversion unit is connected to a signal input, the output of the determination signal generation unit is connected to a control input, and a logical operation of a predetermined function determined according to the logic determination signal received at the control input is the input conversion 17. The method for controlling a semiconductor device according to claim 16, further comprising: a logic circuit configured by a variable arithmetic unit that executes the input signal after conversion by the unit in the semiconductor device. When a plurality of logic circuits are present and the entire logic circuit is configured, the voltage level prepared in advance corresponds to the number of logic circuits and is necessary for connection between the logic circuits and for input selection. 18. The method of controlling a semiconductor device according to claim 17, wherein a bit string of As the deterministic signal generation unit, using a threshold voltage storage type inverter that can hold a threshold voltage once set even when no voltage is applied,
After setting the threshold voltage of the threshold voltage storage type inverter to a value suitable for the logic to be calculated,
18. The method of controlling a semiconductor device according to claim 17, wherein the voltage level is specified while repeating the calculation, comparison, selection and / or change. 20. The method of controlling a semiconductor device according to claim 19, wherein after the logic of the logic circuit is determined, a threshold voltage of the threshold voltage storage type inverter is set in advance to an optimum value for a logic operation to be performed after the next time. The threshold voltage setting of the threshold voltage storage type inverter that is performed in preparation for the next logical operation after the logic determination is performed so that combinations of voltage levels suitable for the logical operation obtained in the subsequent logic determination are increased as much as possible. 21. A method for controlling a semiconductor device according to claim 20. For each logic determination, the voltage level specified by the logic determination is stored,
In the threshold voltage setting of the threshold voltage storage type inverter that is performed prior to the new logic determination, the voltage level that realizes the most frequently used logic operation among the voltage level groups stored in advance. 20. The method for controlling a semiconductor device according to claim 19, wherein a threshold voltage is set so as to obtain For each logic determination, the voltage level specified by the logic determination is stored,
18. The method of controlling a semiconductor device according to claim 17, wherein, when a new logic is determined, the calculation, comparison, selection and change are performed in order from the most frequently used voltage level stored in advance. 18. The method of controlling a semiconductor device according to claim 17, wherein at least the converted input signal, the internal signal of the logic determination signal, and the signal indicating the voltage level are multivalued to three or more values. 18. The method of controlling a semiconductor device according to claim 17, wherein an analog signal is used as at least the input signal after conversion, an internal signal of a logic determination signal, and a signal indicating the voltage level.

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