JP3759398B2 - コンピュータ・プログラムのハザードを検出するシステム - Google Patents

コンピュータ・プログラムのハザードを検出するシステム Download PDF

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Publication number
JP3759398B2
JP3759398B2 JP2000310362A JP2000310362A JP3759398B2 JP 3759398 B2 JP3759398 B2 JP 3759398B2 JP 2000310362 A JP2000310362 A JP 2000310362A JP 2000310362 A JP2000310362 A JP 2000310362A JP 3759398 B2 JP3759398 B2 JP 3759398B2
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Japan
Prior art keywords
instruction
instructions
data
write
memory
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Expired - Fee Related
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JP2000310362A
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Japanese (ja)
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JP2001134442A5 (enExample
JP2001134442A (ja
Inventor
ドナルド・チャールズ・ソルティス・ジュニア
ロニー・リー・アーノルド
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP2000310362A 1999-10-14 2000-10-11 コンピュータ・プログラムのハザードを検出するシステム Expired - Fee Related JP3759398B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/418286 1999-10-14
US09/418,286 US6651164B1 (en) 1999-10-14 1999-10-14 System and method for detecting an erroneous data hazard between instructions of an instruction group and resulting from a compiler grouping error

Publications (3)

Publication Number Publication Date
JP2001134442A JP2001134442A (ja) 2001-05-18
JP2001134442A5 JP2001134442A5 (enExample) 2005-06-02
JP3759398B2 true JP3759398B2 (ja) 2006-03-22

Family

ID=23657475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000310362A Expired - Fee Related JP3759398B2 (ja) 1999-10-14 2000-10-11 コンピュータ・プログラムのハザードを検出するシステム

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Country Link
US (1) US6651164B1 (enExample)
JP (1) JP3759398B2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101412885B1 (ko) * 2012-03-26 2014-06-26 서울대학교산학협력단 모드 설정 및 구분자를 이용하여 저장 매체에서의 영속화를 제어하는 방법 및 그 스토리지 시스템

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6948162B2 (en) * 2002-01-09 2005-09-20 Sun Microsystems, Inc. Enhanced parallelism in trace scheduling by using renaming
JPWO2006134693A1 (ja) * 2005-06-15 2009-01-08 松下電器産業株式会社 プロセッサ
US20090055636A1 (en) * 2007-08-22 2009-02-26 Heisig Stephen J Method for generating and applying a model to predict hardware performance hazards in a machine instruction sequence
US8635501B2 (en) 2011-07-25 2014-01-21 Microsoft Corporation Detecting memory hazards in parallel computing
US9372695B2 (en) 2013-06-28 2016-06-21 Globalfoundries Inc. Optimization of instruction groups across group boundaries
US9348596B2 (en) 2013-06-28 2016-05-24 International Business Machines Corporation Forming instruction groups based on decode time instruction optimization
US9766895B2 (en) * 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Opportunity multithreading in a multithreaded processor with instruction chaining capability

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5148536A (en) * 1988-07-25 1992-09-15 Digital Equipment Corporation Pipeline having an integral cache which processes cache misses and loads data in parallel
EP1102166B1 (en) * 1993-11-05 2003-05-21 Intergraph Corporation Software scheduled superscalar computer architecture
US5958042A (en) * 1996-06-11 1999-09-28 Sun Microsystems, Inc. Grouping logic circuit in a pipelined superscalar processor
US6065105A (en) * 1997-01-08 2000-05-16 Intel Corporation Dependency matrix
US5918033A (en) * 1997-01-08 1999-06-29 Intel Corporation Method and apparatus for dynamic location and control of processor resources to increase resolution of data dependency stalls
US5765017A (en) * 1997-01-13 1998-06-09 International Business Machines Corporation Method and system in a data processing system for efficient management of an indication of a status of each of multiple registers
US6237077B1 (en) * 1997-10-13 2001-05-22 Idea Corporation Instruction template for efficient processing clustered branch instructions
US6260189B1 (en) * 1998-09-14 2001-07-10 Lucent Technologies Inc. Compiler-controlled dynamic instruction dispatch in pipelined processors
US6378063B2 (en) * 1998-12-23 2002-04-23 Intel Corporation Method and apparatus for efficiently routing dependent instructions to clustered execution units
US6219781B1 (en) * 1998-12-30 2001-04-17 Intel Corporation Method and apparatus for performing register hazard detection

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101412885B1 (ko) * 2012-03-26 2014-06-26 서울대학교산학협력단 모드 설정 및 구분자를 이용하여 저장 매체에서의 영속화를 제어하는 방법 및 그 스토리지 시스템

Also Published As

Publication number Publication date
JP2001134442A (ja) 2001-05-18
US6651164B1 (en) 2003-11-18

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