JP3759051B2 - Asynchronous circuit verification method and program thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for verifying an asynchronous circuit and a program thereof, and in particular, when performing verification of an asynchronous circuit by language-level functional simulation, output data of a plurality of sequential circuits having different clock signal cycles are transmitted via a combinational circuit or the like. The present invention relates to a method for verifying an asynchronous circuit and a program for improving the method of verifying the operation of a circuit configuration that is mutually input data of sequential circuits.
[0002]
[Prior art]
In recent years, with the advancement of semiconductor element miniaturization technology, semiconductor devices (LSIs) composed of the semiconductor elements are also increasing in scale, and at the logic level as a logic operation and timing verification tool when designing logic circuits in the semiconductor devices. Functional simulation is applied.
[0003]
The method for verifying an asynchronous circuit according to the present invention is used to verify the operation of a circuit configuration in which output data of a plurality of sequential circuits having different clock signal cycles become input data of the sequential circuit via a combinational circuit or the like. Is. Such an asynchronous circuit verification method is generally performed by using a gate-level netlist and verifying the setup and hold timing by a logic simulation in consideration of timing, for example, a simulation called an event-driven method. .
[0004]
In the event-driven method, a change in the logic level of a clock signal, a data signal, or the like is registered in the storage means as an event that affects the logic state of the circuit, and the contents of the data are updated while sequentially reading these events.
[0005]
An arithmetic process is performed on the circuit to be verified with this data as an input, and if there is a change in the output signal, it is sequentially registered as an event in consideration of the delay amount, and a simulation is executed.
[0006]
On the other hand, since circuit design is performed from functional design in a language such as HDL, it is required to perform asynchronous verification in language level functional simulation.
[0007]
Referring to FIG. 9 showing a flowchart of an example of a conventional asynchronous circuit verification method for meeting this requirement, after detecting an active edge of the clock signal in step S61, a change in input data is detected in step S62, and further processing is performed. In step S63, the metastable state is detected. If the metastable state is detected, the metastable flag is set to false in step S64, the input data is held in step S65, and the metastable state is generated in step S66. To output metastable status.
[0008]
If the metastable state is not detected in step 63, the metastable state flag is set to true in step S68. If no change in input data is detected in step S62, the metastable state flag is set to false in step S69. In step S70, the input data is held, and in step S71, the held data is output.
[0009]
If the active edge of the clock signal is not detected in process S61, the metastable state flag is set to false in process S72, and the process proceeds to process S71.
[0010]
By performing these processes, in the operation of the sequential circuit, the process of defining the metastable and the process of outputting the value of the metastable state for a certain period depending on whether the input data when the clock signal is active or not are performed. ing.
[0011]
By the above-described processing, the sequential circuit is forced to generate a metastable state every time the active edge of the clock signal is detected, so that the malfunction of the sequential circuit that occurs in the asynchronous circuit can be detected by the cycle and phase of each clock signal. This can be verified by reproducing in the same manner as the simulation considering the timing without changing the conditions of the above.
[0012]
The meta-stable state means that the output signal becomes unstable when the setup time and hold time are not observed in the input signal of the latch or flip-flop. When an asynchronous signal is synchronized by a flip-flop, it is not possible to prevent the occurrence of metastable because the input signal does not know where it changes. However, in view of the occurrence phenomenon of metastable, it is possible to make a circuit configuration in which metastable may occur.
[0013]
[Problems to be solved by the invention]
The conventional verification method described above has the following drawbacks. That is, in the case of a circuit configuration as shown in FIG. 3 showing an example circuit diagram to which the verification method of the present invention to be described later is applied, the output value of the flip-flop FF1, which is an internal array element constituting the sequential circuit, is set to the same clock signal. Between sequential circuits (relationship between FF2 and FF3) that are the same data signals triggered by (CLK2) (relationship between FF2 and FF3), the respective data inputs D2 and D3 from the output Q1 of the FF1 in the simulation considering the timing using the gate level netlist. Up to this point, a delay time difference in signal transmission is provided.
[0014]
The timing problem between the input data signal and the clock signal (CLK2) generated between the sequential circuits of FF2 and FF3 due to the delay time difference, that is, the problem that the values held in the sequential circuits of FF2 and FF3 are different is asynchronous. This occurs as a malfunction of the sequential circuit in the circuit.
[0015]
In the prior art verification method of FIG. 9, the sequential circuit of FF2 and FF3 always holds the value of the same data signal as the output Q1 of FF1, so that a malfunction operation between the sequential circuits of FF2 and FF3 is detected. There was a fault that could not be done.
[0016]
The object of the present invention has been made in view of the above-mentioned conventional drawbacks, and the output value of the flip-flop FF1 of the internal array element constituting the sequential circuit of the asynchronous circuit is the same triggered by the same clock signal (CLK2). A timing problem due to a signal transmission delay time difference between the input data signal and the clock signal (CLK2) generated between the sequential circuits as data signals, that is, a malfunction in which the values held in the sequential circuits of FF2 and FF3 are different is detected. The purpose is to provide a verification method.
[0017]
[Means for Solving the Problems]
The feature of the asynchronous circuit verification of the present invention is that a value of input data is held for a plurality of times in an asynchronous circuit verification method performed using a language-level functional simulation apparatus for an asynchronous circuit configured by a sequential circuit to be verified. In order to the sequential circuit Correspondingly to the storage means of the functional simulation device Input data is temporarily stored for each event occurrence time within one clock cycle for the internal array element provided in advance, and when the active edge of the clock signal is detected, the input data is compared to the value one time before the active edge detection. If it has changed, it is defined as a metastable state, and the value of the metastable state is generated and output. After the next time, input at any one time among the input data temporarily stored at each event occurrence time It is to output data.
[0018]
Further, a value of the metastable state is output for a certain period when the active edge of the clock signal is detected, and a value taken in as the input data is set to a value at an arbitrary time within one cycle of the clock signal.
[0019]
Another feature of the asynchronous circuit verification method of the present invention is that, in the asynchronous circuit verification method using a language-level function simulation device for an asynchronous circuit configured by a sequential circuit to be verified, the value of input data is set at a plurality of times. Said sequential circuit to hold minutes Corresponding to the storage means of the functional simulation device A process for holding an input data value generated at an event time within one cycle of a clock signal for an internal array element provided in advance, and the input data value is A process that defines a metastable state when the output data is different from the value held in the array element, a process that generates the metastable state, and whether or not the input data changes when the clock signal is an active edge And a timing verification processing step including a process of outputting input data of the held internal array element at an arbitrary time and a process of outputting the value of the metastable state for a certain period.
[0020]
Further, the timing verification processing step is applied to the sequential circuit having a configuration in which the same data signal is commonly given from at least one internal array element to the other plurality of internal array elements in synchronization with the same clock timing. Can do.
[0021]
Further, the output data is given to each of a plurality of other internal array elements that commonly input the output data of the internal array elements with different transmission delay times, and values temporarily stored between the plurality of internal array elements are respectively stored. It is also possible to forcibly make a different state and to cause the internal array element triggered at the same clock timing to malfunction in a pseudo manner, and to perform preliminary verification of the defective portion based on the timing.
[0022]
Furthermore, verification of the asynchronous circuit using the verification operation of the sequential circuit can be performed by functional simulation.
[0023]
Still another feature of the asynchronous circuit verification method of the present invention is that the asynchronous circuit verification method is performed using a language-level function simulation apparatus for an asynchronous circuit configured by a sequential circuit to be verified, and within one cycle of a clock signal. N (n <(number of events in the clock cycle)) time in order to hold the input data for a plurality of times in the sequential circuit Correspondingly to the storage means of the functional simulation device A first process for temporarily storing in a plurality of internal array elements provided in advance; a second process for detecting an active edge of the clock signal; and a third process for detecting a change in the input data when the active edge is detected. , A fourth process for detecting a metastable state that is an output data state when the value of the input data is different from a value temporarily stored in the internal array element one time ago, and a flag for the metastable state And the input data at any time m (m is any time up to n time) Provided in the storage means A sixth process for temporarily storing the first variable and a value indicating the metastable state; Provided in the storage means A seventh process for generating a metastable state temporarily stored in a second variable; an eighth process for outputting a value indicating the metastable state stored in the second variable; and Ninth processing for temporarily storing input data after the flag setting processing of the metastable state when not detected in the first variable, and flag setting of the metastable state when an active edge of the clock signal is not detected And an eleventh process for outputting the input data temporarily stored in the first variable when the input data is not detected after each of the tenth processes is performed.
[0024]
In addition, a value indicating the metastable state temporarily stored in the second variable can be set by a pseudo random number with a certain initial value.
[0025]
Furthermore, the value indicating the metastable state temporarily stored in the second variable can be set by an arbitrary fixed value designated by the user.
[0026]
Still further, a list processing of the active sequential circuit that extracts all the internal array elements of the sequential circuit that is activated by a clock signal specified by the user and lists the target internal array elements, and a list by the list processing. All event repetition processing that repeats the processing to move to the next one event time for all events after executing the first to eleventh processing for all the internal array elements that have been uploaded You can also.
[0027]
In addition, in the state where the asynchronous circuit is hierarchically structured in advance, in-layer extraction processing for extracting the internal array elements of all the sequential circuits included under the hierarchy specified by the user, and for the extracted internal array elements The list processing and the all event repetition processing may be executed to select the target sequential circuit by hierarchical name.
[0028]
Furthermore, the designation of the sequential circuit below the hierarchy may be performed on all sequential circuits included in the hierarchy.
[0029]
Furthermore, the designation of the sequential circuit below the hierarchy may target all sequential circuits except the hierarchy below.
[0030]
Alternatively, all the sequential circuits included in the hierarchization and all the sequential circuits excluding the lower hierarchy may be specified for the specific hierarchy only.
[0031]
In addition, a logic simulation considering timing is a phenomenon in which values held between sequential circuits differ due to a transmission delay time difference of input data signals generated between sequential circuits to which the same data signal is given in response to the same clock timing. You may reproduce and verify in a similar state.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
First, the outline of the present invention will be described. The asynchronous circuit verification method and the program according to the present invention provide the following processing as an operation in the functional simulation of the sequential circuit constituting the asynchronous circuit.
[0033]
That is, a process for temporarily storing an input data value generated at an event time within one cycle of the clock signal and a process for generating a metastable state are provided to generate the event at an event time within one cycle of the clock signal. Depending on the process of temporarily storing the input data value in the internal array element and the presence or absence of input data change when the clock signal is active, the input data at any one of the input data at the event time held in the internal array element is output. A process for defining a metastable state, and a process for outputting a metastable state value for a certain period of time.
[0034]
The internal array element here is an array element of D [m] possessed by each of FF1, FF2, and FF3 constituting the sequential circuit, and holds the value of the input data Din of each FF for m times. Is an array of Here, m indicates an arbitrary time from 0 to n. That is, there is one storage variable for each FF, and the value that goes into that variable is an arbitrary numerical value (including English characters, which may be 2, 4, 8,...).
[0035]
Further, the operations of FF1, FF2, and FF3 are all the same, and the processing flow of FIG. 1 is obtained, and the events of each process of S0-9 and B1 to B3 are independent.
[0036]
In the processing operation of the sequential circuit described above, the input data is temporarily held in the internal array elements preset in the flip-flops constituting the sequential circuit at every event time within one cycle of the clock signal, and the active edge of the clock signal is detected. Sometimes when the value of the input data changes with respect to the value one hour before, that is, as described above, the output signal is output when the setup time or hold time is not observed in the input signal of the latch or flip-flop. It is defined as a metastable state that becomes unstable, and a metastable state value is generated and output.
[0037]
Then, the input data at an arbitrary time is output among the input data previously held in the internal array element after the next one time.
[0038]
In addition to the conventional operation of forcing the sequential circuit to generate a metastable state for one time each time an active edge of the clock signal is detected by the above-described processing, a value to be acquired as input data is set to one cycle of the clock signal. The operation of setting an arbitrary value at one time is performed.
[0039]
Therefore, the asynchronous circuit is verified by the functional simulation using the operation of the sequential circuit described above, so that the malfunction of the sequential circuit generated in the asynchronous circuit can be changed without changing the cycle and phase conditions of each clock signal. Reproduce in the same way as the simulation considering the timing.
[0040]
In addition, timing problems caused by differences in the transmission delay time of input data signals that occur between sequential circuits that receive the same data signal triggered by the same clock signal, that is, a phenomenon in which the values held between these sequential circuits differ This can be verified by reproducing the simulation in the same manner as the simulation.
[0041]
As a result, it is possible to obtain the effects of simplifying the test bench description and verification work necessary for the simulation and shortening the verification TAT.
[0042]
Hereinafter, the first embodiment of the present invention will be described with reference to FIG. 1 showing an operation flowchart of the sequential circuit of the present invention and FIG. 2 showing a main configuration diagram of a general functional simulator for carrying out the present invention. This will be described in more detail with reference to FIG. 3 showing an example of a sequential circuit to which the sequential circuit verification method of the present invention is applied.
[0043]
The flowchart shown in FIG. 1 is obtained by further adding the operation of the present invention to the processing operation of the conventional sequential circuit shown in FIG. 9 described above, and is a processing operation in which processing S11 and processing S16 are newly added in FIG. is there.
[0044]
That is, in the sequential circuit verification method of the present invention, the input data holding process S11 for temporarily storing the input data n times before in one cycle of the clock signal, the active edge detection process S12 for the clock signal, and the active edge detection The input data change detection process S13 for detecting whether or not the input data has changed in the generated state, and the metastable state for detecting whether or not the metastable state has been detected in the state where the input data change has been detected. A detection process S14, a metastable state flag setting process S15 for setting a metastable state flag when a metastable state is detected, and an arbitrary time m (where m is an arbitrary time up to the n time) ) For temporarily storing the input data (holding the input data in the variable d) and the metastable state in the variable me When the metastable state is not detected in the generation process of the metastable state held in a, the output process S18 of the metastable state that moves the contents of the variable meta to the variable Qout, and the detection process S14 of the metastable state, A metastable state setting process S19 for changing the status flag to true, and a metastable state setting process S20 for changing the metastable state flag to false when no input data is detected in the input data change detection process S13. After the metastable state flag is changed to false in process S20, input data holding process S21 for holding input data in variable d, and held data output process S22 for outputting input data held in variable d to Qout And active edge detection If the active edge is not detected in S12, and a process of setting the metastable state S23 proceeding meta table status flag is changed to false processing S21.
[0045]
The configuration of a known functional simulator to which the above-described flowchart is applied includes a computer 10 and an inspection target device 20, and the computer 10 activates a ready signal when starting requested data or calculation from the inspection target device. After the data supply preparation is completed and the data is supplied to the verification system, the ready signal is deactivated and execution of predetermined verification is controlled.
[0046]
Next, the operation of the first embodiment will be described.
[0047]
Referring to FIGS. 1 and 3, for explaining the operation of the sequential circuit in FIG. 1, a circuit diagram of an asynchronous circuit is shown in FIG. This circuit diagram includes FF1, FF2, FF3 and an adder ALU1 as a sequential circuit.
[0048]
As the input data D1 of FF1, a value obtained by adding +1 to the output data Q1 of FF1 by the adder ALU1 is input, and the output data Q1 of FF1 is input to the input data D2 of FF2 and the input data D3 of FF3. The clock signal CLK1 is supplied to FF1, and the clock signal CLK2 is supplied to FF2 and FF3.
[0049]
The input / output signals of the sequential circuit FF1 are the clock signal CLK1, the input data D1, and the output data Q1, and the input / output signals of the sequential circuits FF2 and FF3 are the input data D2 and output data to the clock signals CLK2 and FF2. Input data D3 and output data Q3 to Q2 and FF3.
[0050]
Further, the metastable state flag MF1 of FF1, the metastable state flag MF2 of FF2, and the metastable state flag MF3 of FF3 are used.
[0051]
In the verification operation in the first embodiment, first, the input data value Din at the current time is held in the internal array element D [0] in the input data holding process S11. The internal array element D [n] has n (n is an integer) array elements, and n is a value smaller than the number of events in one clock cycle used in the function simulation.
[0052]
When the internal array element holds the input data values to FF1, FF2, and FF3, the value of D [0] changes to D [1] and the value of D [1] changes to D [2] as time passes. , D [n−1] holds values for n times to D [n].
[0053]
Next, in the active edge detection process S12 of the clock signal, the edge of the clock signal input to the sequential circuit is detected. If an edge is detected (Yes), the process proceeds to the next input data change detection process S13. If not (No), after performing the metastable state flag setting process S23, the retained data output process S22 is performed.
[0054]
In the input data change detection process S13, a change in the input data signal to the sequential circuit is detected. If the change is detected (Yes), the process proceeds to the metastable state detection process S14 in the next stage, and the change is not detected (No). Changes the metastable state flag to false in the metastable state flag setting process S20. Subsequently, the input data value D [0] is moved to the variable d in the input data holding process S21, and the value of the input data held in the variable d is output in the next held data output process S22.
[0055]
Next, in the metastable state detection process S14, the value of the metastable state flag held in the sequential circuit is checked. If the metastable state is true (true), the metastable state flag is processed in the next step S15. Is set to false.
[0056]
Next, after setting the metastable state flag to false in process S15, in process S16, the value of the arbitrary element m of the internal array element D [m] held in S11 described above is held in the variable d as input data. In step S17, a random value is used to generate a metastable state value and hold it in the variable meta.
[0057]
Finally, in step S18, the value of the metastable state of the variable meta is output to the output Qout of the sequential circuit. If the value of the metastable state flag is not the metastable state (false), after setting the metastable state flag to true in step S19, the same processes S16, S17, and S18 as described above are sequentially performed.
[0058]
The process S20 and the process S23 set the value of the metastable state flag to the case where the metastable state is not in the false state (false) as in the above-described process S15. The process of the process S21 is similar to the process S16 described above. The value of the input data Din to the sequential circuit is held in the variable d. In the processing in step S22, the value held in the variable d is output to the output Qout of the sequential circuit.
[0059]
As a result, after the metastable state detection process of process S14, in process S16, different input data is transferred between sequential circuits having the same data signal triggered by the same clock signal as input data, which is a feature of the present invention. Realize holding action. In the series of processing of processing S17 and processing S18, the value of the metastable state is output when the value of the input data is changed with respect to the value of one hour before the clock signal, which is a feature of the conventional example, is active. Perform the action.
[0060]
Further, when the clock signal is active by the series of processing S20, processing S21, and processing S22 after the input data change detection processing of processing S13, the value of the input data is not changed from the value one time before. After the clock signal is inactive by performing a series of processes S23 and S22 after the clock signal active edge detection process of process S12, the metastable state value is output, The output operation of the input data held from the internal array element is performed one hour later.
[0061]
Next, the operation when the sequential circuit verification method of FIG. 1 is applied to the circuit diagram of the asynchronous circuit of FIG. 3 will be described with reference to the timing chart of FIG.
[0062]
As shown in FIG. 4, it is assumed that the clock signal CLK1 to the FF1 of the sequential circuit changes every three times and the clock signal CLK2 to the sequential circuit FF2 changes every four times.
[0063]
In other words, the simulation does not work unless the width of the time to be held is one cycle of each CLK (6 times for CLK1 and 8 times for CLK2) -1 or less. If one period is exceeded, the value one clock before is also taken in, and the normal operation simulation is lost.
[0064]
Actually, the held width simulates a delay due to a wiring load in a simulation considering the delay, and the width of the metastable state (one time in FIG. 4) is the FF SETUP / HOLD. The model of the model is simulated.
[0065]
In the following description, for ease of explanation, it is assumed that the process of FIG. 1 is completed and the metastable flags MF1, MF2, and MF3 are active.
[0066]
In this case, the FF1 of the sequential circuit inputs, as input data D1, a value obtained by adding +1 by the adder ALU1 to the output Q1 of the Qout of the FF1, and the value between the three times, that is, the value of time 0 (= 1), time 1 Value (= 1) and time 2 value (= 1) are held in the internal array element (process S11), and when the rising edge of CLK1 at time 3 is detected (rising timing) (process S12), the internal array of FF1 After selecting the value (= 1) of the arbitrary time (= time 2) in the element as a normal value, it is output as the value of the output Q1 (= 1) from Qout at time 4, which is the next one time, as will be described later. (Process S22).
[0067]
At this time, the value of the metastable state flag MF1 of FF1 is the state in which the rising edge of CLK1 is active, that is, the active edge (processing S12), and the value of the input data D1 is the value one time before, that is, Although there is a change (= 1) with respect to the initial state value (= 0) of FF1 (processing S13), since the value of MF1 is false in the initial state, the metastable state detection is “No” in processing S14. false (detected false), and true (= 1) in process S19, and the metastable state value (= 6) is output from the output terminal Qout of FF1 to the output Q1 (process S18).
[0068]
Since it is in an inactive state that is not the rising edge of CLK1 at time 4 (process S12), the metastable state flag MF1 is changed to false (= 0) (process S23), and the internal array is used as the output Q1 as described above. The value (= 1) of the arbitrary time (= time 2) selected by the element is output (processing S22).
[0069]
Similarly, at time 9, 10, and time 15, 16, and time 21, 22, the value of the metastable state flag MF1 becomes true (= 1) during one clock cycle (processing S19), and the output terminal Qout of FF1 After outputting a metastable state value, for example, “6” in the output Q1, an arbitrary one time value among the three times held in the internal array element is output as a normal value (processing S22).
[0070]
Although not shown in the example of the timing chart, when all of the processes S12, S13, and S14 select Yes, the value of the metastable state flag MF1 is false (= 0) in process S15.
[0071]
Next, in the internal array element FF2 of the sequential circuit, similarly to FF1, the value of the input data D2 that is the same value as the output Q1 of FF1 for three times, that is, the value of time 1 (= 0), the value of time 2 (= 0), the value of time 3 (= 6) is held in the internal array element (process S11), and when the rising edge of CLK2 at time 4 is detected (process S12), the arbitrary value in the internal array element of FF2 After selecting the value (= 0) of the time (= time 1) as a normal value, the value is output as the value (= 0) of the output Q2 from the output terminal Qout of the FF2 at time 5, which is the next time (processing S22). ).
[0072]
At this time, similarly to the above-described FF1, the value of the metastable state flag MF2 of FF2 at time 4 is a value in which the rising edge of CLK2 is active (processing S12), and the value of the input data D2 is the value one time before, That is, since there is a change (= 6) with respect to the value of the initial state (= 0) of FF2 (process S13), it becomes true (= 1) (process S14 and process S19), and passes through processes S16 and S17. The metastable state value (= 3) is output from the output terminal Qout of the FF2 to the output Q2 (processing S18).
[0073]
At time 5, since it becomes an inactive state that is not the rising edge of CLK2 (process S12), the metastable state flag MF2 is changed to false (= 0) as Q2 (process S23), and is selected by the internal array element The value (= 0) of the arbitrary time (= time 1) is output (process S22).
[0074]
At times 12 and 13, and at times 20 and 21, since the value of D2 does not change during the active state in which CLK2 rises (processing S13), the value of the metastable state flag MF2 is false (= 0) (process S20), and at the output Q2 of Qout, the last stored time (= 11) among the three times (time 9, 10, 11) held in the internal array element (process S21) Is output as a normal value (step S22).
[0075]
Finally, the sequential circuit FF3 also performs the same operation as the above-described FF1 and FF2, and holds the value for three times of the input data D3 that is the same value as the output Q1 of the FF1 in the internal array element (processing S11). When the rising edge of CLK2 at time 4 is detected (processing S12), an arbitrary time (= time 3) value (= 6) in the internal array element of FF3 is selected as a normal value at the rising timing, and at the next one time At a certain time 5, it is output from Qout as the value of output Q3 (= 6) (process S22).
[0076]
Similarly to the above-described FF2, the value of the metastable state flag MF3 of the FF3 at the time 4 is a state in which the rising edge of the CLK2 is active (processing S12), and the value of the D3 is a value one time before, that is, the FF3. Since there is a change (= 6) with respect to the value of the initial state (process S13), it becomes true (= 1) (process S19), and the value of the metastable state (from Qout to Q3 through process S16 and process S17) ( = 7) is output (process S18).
[0077]
At time 5, CLK2 is in an inactive state that is not a rising edge (process S12). As Q3, the metastable state flag MF2 is changed to false (= 0) (process S23). The value (= 6) of the arbitrary time (= time 3) selected by the internal array element is output instead of the value of (= 1) (process S22)
That is, the sequential circuits FF2 and FF3 at time 4 take in the value of the output Q1 of the FF1, which is the same data signal, as input data D2 and D3 at the rising edge of CLK2, but each is an internal array held as a value for three times. Since the value selected at an arbitrary time from the elements is a different value such as the value of time 1 (= 0) in FF2 and the value of time 3 (= 6) in FF3, it is between the sequential circuits of FF2 and FF3. This means that the value held in is different.
[0078]
This simulates the time difference between the signal propagation delay of the input data D2 to the FF2 and the signal propagation delay of the input data D3 to the FF3 at the timing of time 4, and the same data signal triggered by the same clock signal is input. This shows that a malfunction occurs due to a timing problem between sequential circuits.
[0079]
Further, since the value of D3 (= 6) selected by FF3 as the normal value is the value of the metastable state generated in the sequential circuit FF1, the original expected input data, that is, the output Q1 at time 4 is stored in FF3. Unlike the value of = 1 (= 1), this asynchronous circuit caused a malfunction from time 5 to time 12, and the change in CLK1 at time 3 and the change in CLK2 at time 4 caused malfunction in this asynchronous circuit. The timing of the occurrence is shown, and the operation of the verification method of the prior art is also realized without any problem.
[0080]
The value in the metastable state described above is an arbitrary fixed value, and may be a fixed value “X” as in a third embodiment (FIG. 6) described later.
[0081]
Actually, the value is an arbitrary value within the range that the data Din can take, but is not limited thereto, and the effect of the present invention does not change.
[0082]
For example, if the FF is a 1-bit sequential circuit, the possible values are 0 and 1. In many cases, a value of 2 or more cannot be defined as a limitation of a simulator that is actually mounted. However, when one sequential circuit processes a 4-bit data length, it takes a value of 0 to 15.
[0083]
As described above, the operation of the sequential circuit is triggered by the same clock signal by holding the input data signal for one cycle of the clock signal and selecting and outputting a value at any one time within one cycle. The operation is performed in consideration of the timing problem due to the difference in the transmission delay time of the input data signal between the sequential circuits.
[0084]
Also, as the operation of the conventional example, when the value of input data changes with respect to the value one hour before when active edge is detected, it is defined as a metastable state, and a metastable state value is generated and output. Then, after the next one time, the input data is output by the above-described operation and the sequential circuit is forced to generate a metastable state for one time every active edge of the clock signal.
[0085]
Therefore, a circuit configuration including a timing problem due to a difference in transmission delay time of an input data signal generated between sequential circuits triggered by the same clock signal by performing verification of an asynchronous circuit using the operation of the sequential circuit by a functional simulation. However, the failure of the sequential circuit that occurs in the asynchronous circuit is not verified by checking the operation by changing the cycle and phase conditions of each clock signal in various ways. It can be verified by reproducing the operation.
[0086]
As a result, it is possible to obtain the effects of simplifying the test bench description and verification work necessary for the simulation and shortening the verification TAT.
[0087]
In the above-described embodiment, the rising change is used as the active edge of the clock signal, but the same applies to the falling change.
[0088]
Further, even if the active edge of the clock signal has a rising change and a falling change sequential circuit as a configuration of the asynchronous circuit, the same asynchronous circuit verification effect as that of the above-described embodiment can be obtained.
[0089]
Next, a second embodiment of the present invention will be described.
[0090]
The basic configuration of the second embodiment is the same as that of the first embodiment. That is, the generation of the metastable state in the metastable state generation process S17 in the sequential circuit verification flowchart of the present invention shown in FIG. 1 is further devised.
[0091]
Referring to FIG. 5 showing the configuration, the metastable state generation process S17 is a function in which the value of the metastable state is set as a pseudo-random number with a constant initial value and added to the variable meta. .
[0092]
A pseudo-random number with a constant initial value generally has a periodic pattern, and when used in the sequential circuit of the present invention, the value of the metastable state is an asynchronous circuit operation to be verified, that is, applied. Then, the value is the same as long as the number of sequential circuits in the circuit and the order of operation are not changed.
[0093]
When the verification of the asynchronous circuit according to the second embodiment is performed, if the target asynchronous circuit and the simulation pattern for the operation are the same, the function simulation result is the same no matter how many times it is executed. Effective in verification work that requires reproducibility.
[0094]
Therefore, the asynchronous circuit is verified by the functional simulation using the operation of the sequential circuit described above, so that the malfunction of the sequential circuit generated in the asynchronous circuit can be changed without changing the cycle and phase conditions of each clock signal. Reproduce in the same way as the simulation considering timing.
[0095]
In addition, the timing problem due to the transmission delay time difference between the input data signals generated between the sequential circuits to which the same data signal is input with the same clock signal as a trigger, that is, the phenomenon in which the value held between the sequential circuits is different is also determined. It can be verified by reproducing it in the same way as the simulation considered.
[0096]
As a result, it is possible to obtain the effects of simplifying the test bench description and verification work necessary for the simulation and shortening the verification TAT.
[0097]
Next, a third embodiment of the present invention will be described.
[0098]
In the second embodiment described above, by setting the metastable state value as a random number value, an effect of improving the comprehensiveness of the malfunction verification of the operation of the asynchronous circuit due to the propagation of the metastable state value is obtained. However, by setting this value as an arbitrary fixed value by the user, it is possible to mark the malfunction of the asynchronous circuit in the function simulation result.
[0099]
Referring to FIG. 5 showing the configuration of the third embodiment for that purpose, the metastable state generation process S17 sets the value of the metastable state with a pseudo-random number with an arbitrary fixed value specified by the user, A function to be held in the variable meta is added.
[0100]
That is, an arbitrary fixed value specified by the user is set as the occurrence of the metastable state. This makes it possible to identify the time at which the metastable state occurs and the sequential circuit that has occurred for the sequential circuit in the target asynchronous circuit, and can easily analyze the creation of malfunctions in the asynchronous circuit. .
[0101]
Also in this embodiment, the asynchronous circuit is verified by functional simulation using the operation of the sequential circuit described above, so that the malfunction of the sequential circuit generated in the asynchronous circuit can be changed in various cycle and phase conditions. It is reproduced in the same way as the simulation considering the timing without changing to.
[0102]
In addition, a phenomenon in which values held between sequential circuits that are input with the same data signal using the same clock signal as a trigger can be verified by reproducing the phenomenon in the same manner as a simulation considering timing.
[0103]
As a result, it is possible to obtain the effects of simplifying the test bench description and verification work necessary for the simulation and shortening the verification TAT.
[0104]
Next, a fourth embodiment of the present invention will be described.
[0105]
In the fourth embodiment, processing for selecting a target sequential circuit in a circuit is added to an asynchronous circuit to which the sequential circuit verification method of the present invention is applied. That is, as a feature of the present invention, it has a function of holding the input data value generated at the event time within one cycle of the clock signal in the internal array element, but this increases the scale of the asynchronous circuit to be verified. Therefore, it is expected that the state values held in the function simulator will be enormous, and therefore, there is a risk that the function simulation speed will be significantly lowered and the risk of being unable to execute due to a shortage of resources for simulator operation.
[0106]
Referring to FIG. 7 showing the flowchart of the fourth embodiment, all the sequential circuits that are newly added at the beginning of the process and are activated by the clock signal specified by the user are extracted, and the target order is extracted. A sequential circuit extraction process S41 for listing circuits, a process S42 for clearing FF [i] to i = 0, a process S43 for performing the verification flow of FIG. 1 on FF [i], and FF [i ] Is incremented one by one at i = i + 1, the verification flow is sequentially performed on the next FF [i], and repeated until i = k, i = k, and all events are completed. Step S46 is repeated from Step S42.
[0107]
That is, the processing of this embodiment performs the operation flow of FIG. 1 for all the listed sequential circuits in the loop processing of processing S43 to processing S45 for each event time of the function simulator, and all the sequential circuits are processed. When the above process is completed, the process proceeds to the next one event time.
[0108]
As a result, the application of the sequential circuit of the present invention can be limited to that of a clock signal line designated by the user, so that the effect of reducing the state value held in the function simulator generated in the present invention can be obtained.
[0109]
Further, since the asynchronous circuit portion to be verified can be easily specified by the user in units of clock signal lines, the description of the test bench and the simplification of the verification work inherent in the present invention are not impaired.
[0110]
Also in this embodiment, the asynchronous circuit is verified by functional simulation using the operation of the sequential circuit described above, so that the malfunction of the sequential circuit generated in the asynchronous circuit can be changed in various cycle and phase conditions. It is reproduced in the same way as the simulation considering the timing without changing to.
[0111]
In addition, a phenomenon in which values held between sequential circuits that are input with the same data signal using the same clock signal as a trigger can be verified by reproducing the phenomenon in the same manner as a simulation considering timing.
[0112]
As a result, it is possible to obtain the effects of simplifying the test bench description and verification work necessary for the simulation and shortening the verification TAT.
[0113]
Next, a fifth embodiment of the present invention will be described.
[0114]
Referring to FIG. 8 showing a configuration example of the fifth embodiment of the present invention. The present embodiment is a verification flowchart in which a process S51 based on a hierarchical name is added as a process of selecting a sequential circuit as a target in a circuit in addition to the above-described fourth embodiment.
[0115]
In the process S51, all the sequential circuits under the hierarchy designated by the user are extracted, the target sequential circuits are listed, and the processes S41 to S46 of FIG. 7 described in the fourth embodiment are then performed. Do.
[0116]
This sequential circuit designation method is applied by performing a method that targets all sequential circuits included under the hierarchy and a method that targets all sequential circuits except the hierarchical level. Even when the hierarchical structure of the asynchronous circuit is complicated, only a specific hierarchy can be specified.
[0117]
As a result, even if the target sequential circuit is specified by the clock signal, if the number of target sequential circuits is still large, the design of the asynchronous circuit to be applied is hierarchically structured to narrow down the verification range in units of hierarchy. Therefore, there is an effect that the verification operation is facilitated by further reducing the state value held inside the function simulator and narrowing down the verification range.
[0118]
Also in this embodiment, the asynchronous circuit is verified by functional simulation using the operation of the sequential circuit described above, so that the malfunction of the sequential circuit generated in the asynchronous circuit can be changed in various cycle and phase conditions. It is reproduced in the same way as the simulation considering the timing without changing to.
[0119]
In addition, a phenomenon in which values held between sequential circuits that are input with the same data signal using the same clock signal as a trigger can be verified by reproducing the phenomenon in the same manner as a simulation considering timing.
[0120]
As a result, it is possible to obtain the effects of simplifying the test bench description and verification work necessary for the simulation and shortening the verification TAT.
[0121]
【The invention's effect】
As described above, by applying the verification method of the present invention, the malfunction of the sequential circuit occurring in the asynchronous circuit can be adjusted during functional simulation without changing the cycle and phase conditions of each clock signal in various ways. Reproduce in the same way as the simulation considered.
[0122]
In addition, a phenomenon in which values held between sequential circuits that are input with the same data signal using the same clock signal as a trigger can be verified by reproducing the phenomenon in the same manner as a simulation considering timing.
[0123]
Therefore, it is possible to obtain the effects of simplifying the test bench description and verification work necessary for the simulation and shortening the verification TAT.
[Brief description of the drawings]
FIG. 1 is an operation flowchart of a sequential circuit according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a general functional simulator to which the present embodiment is applied.
FIG. 3 is a circuit diagram of an asynchronous circuit for explaining the operation of the present invention.
FIG. 4 is a timing chart for explaining the operation of the present invention.
FIG. 5 is a flowchart of occurrence of a metastable state in the second embodiment of the present invention.
FIG. 6 is a flowchart of metastable state generation according to the third embodiment of the present invention.
FIG. 7 is an operation flowchart according to the fourth embodiment of the present invention.
FIG. 8 is an operation flowchart according to the fifth embodiment of the present invention.
FIG. 9 is an operation flowchart of an example of a conventional sequential circuit.
[Explanation of symbols]
ALU1 adder
FF1, FF2, FF3 internal array elements
CLK1, CLK2 clock signal
D1, D2, D3 input data

Claims (18)

In an asynchronous circuit verification method performed using a language-level function simulation device for an asynchronous circuit configured by a sequential circuit to be verified, the function corresponds to the sequential circuit in order to hold input data values for a plurality of times. Input data is temporarily stored for each event occurrence time within one clock period for an internal array element provided in advance in the storage means of the simulation apparatus, and when the active edge of the clock signal is detected, the input data is one time of the active edge detection. If it is changed with respect to the previous value, it is defined as a metastable state, the value of the metastable state is generated and output, and after the next one time, the input data temporarily stored at each event occurrence time A method for verifying an asynchronous circuit, wherein input data at an arbitrary time is output.   2. The asynchronous circuit according to claim 1, wherein when the active edge of the clock signal is detected, the value of the metastable state is output for a certain period, and the value taken in as the input data is a value at any one time within one cycle of the clock signal. Verification method. In an asynchronous circuit verification method performed using a language-level function simulation device for an asynchronous circuit configured by a sequential circuit to be verified, the function corresponds to the sequential circuit in order to hold input data values for a plurality of times. A process of holding an input data value generated at an event time within one cycle of the clock signal for an internal array element provided in advance in the storage means of the simulation apparatus, and a value of the input data when the active edge of the clock signal is detected A process for defining a metastable state when the output data is different from the value held in the internal array element one time before, a process for generating the metastable state, and the input when the clock signal is an active edge Depending on the presence or absence of data change, the stored input data at any one time of the internal array element Verification method of asynchronous circuit and outputting, characterized in that it comprises a timing verification process step in which a processing for outputting a value of a certain period the metastable state.   4. The timing verification processing step is applied to the sequential circuit having a configuration in which the same data signal is commonly supplied from at least one of the internal array elements to the plurality of other internal array elements in synchronization with the same clock timing. A method for verifying the described asynchronous circuit.   A state in which the output data is given to each of the other internal array elements that commonly input the output data of the internal array elements with an arbitrary transmission delay time, and the values temporarily stored between the internal array elements are forcibly different. 3. A method for verifying an asynchronous circuit according to claim 1 or 2, wherein the internal array elements triggered at the same clock timing are made to malfunction in a pseudo manner, and a pre-verification of a defective portion based on the timing is performed.   6. The asynchronous circuit verification method according to claim 5, wherein verification of the asynchronous circuit is performed by functional simulation using the verification operation of the sequential circuit. In an asynchronous circuit verification method performed using a language-level function simulation device for an asynchronous circuit configured with a sequential circuit to be verified, n (n <(number of events in clock cycle)) time within one cycle of the clock signal A first process of temporarily storing the input data for a plurality of times in a plurality of internal array elements provided in advance in the storage means of the functional simulation device corresponding to the sequential circuit, and an active edge of the clock signal A second process for detecting the input data, a third process for detecting a change in the input data when the active edge is detected, and a value temporarily stored in the internal array element one time before the value of the input data A fourth process for detecting a metastable state which is an output data state at a different time, and a fifth process for setting a flag of the metastable state And a sixth process for temporarily storing the input data at an arbitrary time m (m is an arbitrary one time up to the n time) in the first variable, and a value indicating the metastable state in the second variable A seventh process for generating a metastable state to be temporarily stored; an eighth process for outputting a value indicating the metastable state stored in the second variable; and the process when the input data is not detected. A ninth process for temporarily storing input data to be executed after the metastable state flag setting process in the first variable, and a tenth process for setting the metastable state flag when an active edge of the clock signal is not detected. And an eleventh process for outputting the input data temporarily stored in the first variable when the input data is not detected after each process is executed. Verification method of the asynchronous circuit characterized by and.   The asynchronous circuit verification method according to claim 7, wherein a value indicating the metastable state temporarily stored in the second variable is set by a pseudo random number with a constant initial value.   8. The asynchronous circuit verification method according to claim 7, wherein a value indicating the metastable state temporarily stored in the second variable is set by an arbitrary fixed value designated by a user.   All the internal array elements of the sequential circuit activated by the clock signal specified by the user are extracted, and the active sequential circuit that lists the internal array elements to be listed is listed in the list processing. 8. An all-event repeating process in which a process of moving to the next one event time is repeated for all events after executing the first to eleventh processes for all the internal array elements. Asynchronous circuit verification method.   In a state in which asynchronous circuits are hierarchically structured in advance, in-layer extraction processing for extracting the internal array elements of all the sequential circuits included under the hierarchy specified by the user, and the list for the extracted internal array elements The asynchronous circuit verification method according to claim 10, wherein the sequential circuit as a target is selected by a hierarchical name by executing an up process and the all event repetition process.   The asynchronous circuit verification method according to claim 11, wherein the designation of the sequential circuit under the hierarchy targets all the sequential circuits included in the hierarchy.   The asynchronous circuit verification method according to claim 11, wherein the designation of the sequential circuit below the hierarchy is for all sequential circuits except the hierarchy below.   The asynchronous circuit verification method according to claim 11, wherein all sequential circuits included in the hierarchization and all sequential circuits excluding the lower hierarchy are specified as targets, and only a specific hierarchy is specified.   A state in which the value held between the sequential circuits varies according to the transmission delay time difference of the input data signal generated between the sequential circuits to which the same data signal is given in response to the same clock timing, according to the logic simulation considering the timing. The method for verifying an asynchronous circuit according to claim 1, wherein the verification is performed by reproducing. In an asynchronous circuit verification method performed using a language-level function simulation device for an asynchronous circuit configured with a sequential circuit to be verified, n (n <(number of events in clock cycle)) time within one cycle of the clock signal In order to hold the input data for a plurality of times, a first process for temporarily storing in an internal array element provided in advance in the storage means of the functional simulation device corresponding to the sequential circuit, and detecting an active edge of the clock signal A second process to detect, a third process to detect a change in the input data when the active edge is detected, and a value of the input data different from a value temporarily stored in the internal array element one time ago A fourth process for detecting a metastable state, which is an output data state, and a fifth process for setting a flag for the metastable state Any (m is any one time up to n times) of the time point m and a sixth process of temporarily storing the input data in the first variable provided in the storage means, said stored value indicating the metastable state A seventh process for generating a metastable state temporarily stored in a second variable provided in the means; an eighth process for outputting a value indicating the metastable state stored in the second variable; Ninth processing for temporarily storing input data to be executed in the first variable after flag setting processing of the metastable state when the input data is not detected, and the metastable when the active edge of the clock signal is not detected After each execution of the tenth process for setting the state flag, the input data temporarily stored in the first variable when the input data is not detected And processing of the 11 that outputs a program for causing a computer to execute. All the internal array elements of the sequential circuit activated by the clock signal specified by the user are extracted, and the active sequential circuit that lists the internal array elements to be listed is listed in the list processing. After executing the first to eleventh processes for all the internal array elements, the computer is caused to execute an all event repetition process that repeats the process of moving to the next one event time for all events. The program according to claim 16 . In a state in which asynchronous circuits are hierarchically structured in advance, in-layer extraction processing for extracting the internal array elements of all the sequential circuits included under the hierarchy specified by the user, and the list for the extracted internal array elements 18. The program according to claim 17, which causes a computer to execute an up process and an execution process of the all event repetition process.

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