JP3753049B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit capable of reducing the number of external terminals.
[0002]
[Prior art]
FIG. 3 is a circuit configuration diagram of a conventional semiconductor integrated circuit. 1 is a clock terminal, 2 is a pull-up resistor, 3 is a data terminal, 4 is a pull-up resistor, 6 is a parallel / serial control selection terminal, 7-1 is a plurality of parallel control terminals, and 7-2 is a first signal detection. Indicator terminal, 7-3 a second signal detection indicator terminal, 10 an audio multiplexed signal input terminal, 11 a first signal detection circuit, 12 a second signal detection circuit, 13 a parallel / serial conversion circuit, 14 Is an OR circuit, 17 is an output transistor, 19 and 20 are output transistors, 21 and 22 are pull-up resistors, and 23 is a control signal decoder.
[0003]
The circuit operation of the conventional semiconductor integrated circuit configured as described above will be described below with reference to FIG. FIG. 2 is a timing chart showing operation waveforms of respective parts of the conventional example of FIG. 3, where the horizontal axis represents time and the vertical axis represents DC voltage. However, for VIN only, the vertical axis represents the frequency of the input signal.
[0004]
In FIG. 3, when a signal VIN having a frequency fH (= 15.734 kHz) is input from the audio multiplex signal input terminal 10, the output VD1 of the first signal detection circuit 11 becomes high level, and the second signal detection circuit 12 The output VD2 is low level. When a signal VIN having a frequency of 5 fH is input, the output VD1 of the first signal detection circuit 11 is at a low level and the output VD2 of the second signal detection circuit 12 is at a high level.
[0005]
First, the operation when the semiconductor integrated circuit is serially controlled will be described. A clock signal from a bidirectional serial control microcomputer (not shown) is input to the clock terminal 1, and serial data is also input to the data terminal 3. The serial data input by the controller is decoded by the control signal decoder 23, and output mode switching and fH signal confirmation and 5fH signal confirmation are performed bidirectionally.
[0006]
<When controlling devices in parallel>
Using the parallel control microcomputer, the parallel data input from the parallel control terminal 7-1 is decoded by the control signal decoder 23, the output mode is switched, and the fH signal is confirmed at the first signal detection indicator terminal 7-2. The 5fH signal is confirmed at the second signal detection indicator terminal 7-3.
[0007]
As described above, the signal detection indicator terminal of the conventional semiconductor integrated circuit requires a signal detection indicator terminal for parallel control separately from the bidirectional serial control terminal in order to support both serial control and parallel control. .
[0008]
[Problems to be solved by the invention]
Signal detection in a conventional semiconductor integrated circuit requires two terminals (data and clock) in the case of bidirectional serial control and as many indicator terminals as the number of signals to be detected in parallel control. Therefore, in order to support both parallel control and serial control, an indicator terminal for parallel control is necessary. For this reason, the number of terminals of the semiconductor integrated circuit is increased.
[0009]
SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a semiconductor integrated circuit that reduces the number of terminals by sharing terminals used during bidirectional serial control and terminals used during parallel control. .
[0010]
[Means for Solving the Problems]
In order to achieve this object, the semiconductor integrated circuit according to the present invention includes a clock / ID1 terminal 1 connected to the first pull-up resistor 2, a data / ID2 terminal 3 connected to the second pull-up resistor 4, The serial decoder 5 to which the clock / ID1 terminal 1 and the data / ID2 terminal 3 are connected, the parallel / serial control selection terminal 6, the parallel control terminal 7-1, the parallel control terminal 7-1 and the serial decoder 5 A selector 8 connected to the parallel / serial control selection terminal 6, an audio output mode switching circuit 9 connected to the selector 8, an audio multiplexed signal input terminal 10, and a first connected to the audio multiplexed signal input terminal 10. A signal detection circuit 11; a second signal detection circuit 12 connected to the audio multiplexed signal input terminal 10; the serial decoder 5; and the first signal detection circuit 1 The parallel / serial conversion circuit 13 connected to the output and the second signal detection circuit 12, the OR circuit 14 connected to the parallel / serial conversion circuit 13 and the serial decoder 5, the OR circuit 14 and the parallel / serial A data / ID2 switching SW 15 connected to the control selection terminal 6 and the second signal detection circuit 12, and a grounded emitter having the data / ID2 switching SW 15 connected to the base and the data / ID2 terminal 3 connected to the collector. One output transistor 17, a clock / ID1 switching SW 16 connected to the parallel / serial control selection terminal 6 and the first signal detection circuit 11, and the clock / ID1 switching SW 16 is connected to the base and the clock / ID1 terminal 1 has a second emitter-grounded output transistor 18 connected to the collector.
[0011]
With this configuration, the data and clock terminals can be used as signal detection indicator terminals during parallel control, so the number of terminals can be reduced.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0013]
FIG. 1 shows a circuit configuration according to an embodiment of the present invention. In FIG. 1, 1 is a clock / ID1 terminal, 2 is a first pull-up resistor, 3 is a data / ID2 terminal, 4 is a second pull-up resistor, 5 is a serial decoder, 6 is a parallel / serial control selection terminal, 7-1, a parallel control terminal, 8 a selector, 9 an audio output mode switching circuit, 10 an audio multiplexed signal input terminal, 11 a first signal detection circuit, 12 a second signal detection circuit, and 13 a parallel / A serial conversion circuit, 14 is an OR circuit, 15 is a data / ID2 switching SW, 16 is a clock / ID1 switching SW, 17 is a first output transistor, and 18 is a second output transistor. The operation of the semiconductor integrated circuit of the present embodiment configured as described above will be described below.
[0014]
First, when a sine wave signal having a frequency fH (= 15.734 kHz) is input from the audio multiplexed signal input terminal 10 of FIG. 1, the output VD1 of the first signal detection circuit 11 becomes a DC voltage of Hi, and the second signal. The output of the detection circuit 12 is a DC voltage of Lo. Conversely, when a sine wave signal having a frequency of 5 fH is input, the output VD1 of the first signal detection circuit 11 becomes a DC voltage of Lo, and the output of the second signal detection circuit 12 becomes a DC voltage of Hi. That is, when the VIN signal in FIG. 2 is input, the first signal detection circuit output and the second signal detection circuit output are output as VD1 and VD2, respectively. In FIG. 2, the horizontal axis represents time, and the vertical axis represents DC voltage (for VIN only, the vertical axis represents the input signal frequency).
[0015]
<When serially controlling a device>
Using a bidirectional serial control microcomputer, serial data input from the clock / ID1 terminal 1 and data / ID2 terminal 3 is decoded by the serial decoder 5, and output mode switching and fH signal confirmation and 5fH signal confirmation are performed bidirectionally.
[0016]
When serial control is selected at the parallel / serial control selection terminal 6, the selector 8 selects the output of the serial decoder 5 and transmits it to the audio output mode switching circuit 9. The clock and data shown in FIG. 1 are an example when the detection results VD1 and VD2 are transmitted to the serial control microcomputer. The device address is specified by the 1st to 7th bit data at the rising edge of the clock, and the transmission / reception direction is specified by the 8th bit data. The data shown in FIG. 1 is an example of the transmission mode from the device to the serial control microcomputer because the data at the 8th bit of the clock rise is Hi. The data at the 9th bit of the clock rise is a BIT for confirming that the device has recognized the address, and transmits a recognition signal from the device to the serial control microcomputer. Specifically, during the period from the 8th bit fall of the clock to the 9th bit fall, the grounded emitter output Tr1 whose collector is connected to the data terminal is turned on and the data terminal is lowered to Lo, and the serial control microcomputer Is recognized at the 9th bit of the clock rise. The 10th bit data at the rising edge of the clock is the fH signal detection recognition BIT, and the 11th bit data is the 5fH signal detection recognition BIT. When a clock and data as shown in FIG. 1 are input, the serial decoder outputs VCK and VR signals, and the parallel / serial conversion circuit 13 converts the parallel signals of the detection circuit outputs VD1 and VD2 into a serial signal VD12. VS is an OR signal of VAK and VD12. Here, since serial control is selected at the parallel / serial control selection terminal 6, the data / ID2 switching SW15 operates to select the a side and the clock / ID1 switching SW16 is turned OFF. Therefore, the serial signal VS is input to the base of the output Tr1, and the detection result is transmitted to the data / ID2 terminal 3.
[0017]
<When controlling devices in parallel>
Using the parallel control microcomputer, the output mode is switched by the parallel data input from the parallel control terminal 7-1, the fH signal is confirmed at the clock / ID1 terminal 1, and the 5fH signal is confirmed at the data / ID2 terminal 3.
[0018]
When parallel control is selected at the parallel / serial control selection terminal 6, the selector 8 selects the signal at the parallel control terminal 7-1 and transmits it to the audio output mode switching circuit 9. The data / ID2 switch SW15 selects the b side, and the clock / ID1 switch SW16 operates to turn ON. Accordingly, the detection circuit outputs VD1 and VD2 are respectively input to the bases of the output Tr1 and Tr2 whose emitters are grounded, and the detection results are output to the clock / ID1 terminal 1 and the data / ID2 terminal 3.
[0019]
As described above, according to the present embodiment, since the clock / ID1 terminal 1 and the data / ID2 terminal 3 are provided and the bidirectional serial control terminal and the indicator terminal for parallel control are shared, serial control and parallel control are performed. The number of terminals can be reduced at the same time as both.
[0020]
The above is one embodiment of the present invention, and the number of terminals can be similarly reduced even if the detection signal is an arbitrary signal other than fH or 5fH, and an arbitrary number of signal detection confirmation BITs.
[0021]
【The invention's effect】
The present invention realizes a semiconductor integrated circuit with a reduced number of terminals by sharing a bidirectional serial control terminal as an indicator terminal for parallel control.
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is an operation timing chart of the semiconductor integrated circuit of the present invention. FIG. 3 is a block diagram of a conventional semiconductor integrated circuit.
1 Clock / ID1 terminal 2 First pull-up resistor 3 Data / ID2 terminal 4 Second pull-up resistor 5 Serial decoder 6 Parallel / serial control selection terminal 7-1 Parallel control terminal 7-2 First parallel indicator terminal 7 -3 Second parallel indicator terminal 8 Selector 9 Audio output mode switching circuit 10 Audio multiplexed signal input terminal 11 First signal detection circuit 12 Second signal detection circuit 13 Parallel / serial conversion circuit 14 OR circuit 15 Data / ID2 switching SW
16 Clock / ID1 switch
17 First output transistor 18 Second output transistor 19 Third output transistor 20 Fourth output transistor 21 Third pull-up resistor 22 Fourth pull-up resistor 235 Signal decoder

Claims (1)

Clock / ID1 terminal connected to the first pull-up resistor, data / ID2 terminal connected to the second pull-up resistor, the clock / ID1 terminal, the data / ID2 terminal, the parallel control terminal, and the parallel / serial control A control signal decoder connected to the selection terminal, an audio multiplex signal input terminal, a first signal detection circuit and a second signal detection circuit commonly connected to the audio multiplex signal input terminal, and an output of the first signal detection circuit And a parallel / serial conversion circuit to which the second signal detection circuit output and the first output of the control signal decoder are connected, and an OR to which the parallel / serial conversion circuit output and the second output of the control signal decoder are connected. Circuit, the OR circuit output, the second signal detection circuit output, the data / ID2 switching SW connected to the parallel / serial control selection terminal, and the second signal detection circuit. A clock / ID1 switching SW connected to an output and the parallel / serial control selection terminal; a first emitter-grounded output transistor having the data / ID2 switching SW connected to a base and the data / ID2 terminal connected to a collector; A semiconductor integrated circuit comprising a second emitter-grounded output transistor having the clock / ID1 switching switch connected to a base and the clock / ID1 terminal connected to a collector.

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