JP3752938B2 - comparator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a differential type comparator, and more particularly to a low voltage operation comparator.
[0002]
[Prior art]
FIG. 4 is a principal circuit diagram of a conventional differential comparator. In the following description, each MOSFET is represented by a number M.
This comparator includes a constant current circuit 51, an input stage circuit 52, and an output stage circuit 53. The constant current circuit 51 includes M20 and a current source circuit 57. The input stage circuit 52 has a circuit configuration in which a bias unit 54, a gate signal input unit 55, and an output signal transmission unit 56 are connected in series, and this circuit is VDD (here, VDD is a high potential side of a power source or a power source voltage). And a ground GND. The bias unit 54 is configured by M21, the gate signal input unit 55 is configured by M22 and M23, and the output signal transmission unit 56 is configured by M24 and M25 serving as active loads. The output stage circuit 53 includes M26, M27 and M28, M29. M20 and M21 and M26 and M27 form a current mirror circuit.
[0003]
The operation of this circuit will be described. A bias current I21 having the same magnitude as the bias current I20 flowing through M20 of the constant current circuit 57 flows through M21. M21 that constitutes the bias section 54 of the input stage circuit 52, M22 and M23 that constitute the gate signal input section 55 of the input stage circuit 52, and M24 that is an active load that constitutes the output signal transmission section 56 of the input stage circuit 52. , M25 are operated in the saturation region, and the bias currents I22, I23 flowing in M22, M23 constituting the gate signal input unit 55 are suppressed by M24, M25 used as active loads.
[0004]
The drain voltages of M24 and M25 are input to the gates of M29 and M28 constituting the output stage circuit 53. M26 and M27 constituting the output stage circuit 53 constitute a current mirror circuit, and the bias current I25 flowing through M27 does not flow more than the bias current I24 flowing through M26. In addition, the magnitudes (energization capability) of the currents I24 ′ and I25 ′ that M28 and M29 can flow are proportional to the drain voltages of M24 and M25.
The magnitudes of the bias currents I25 and I24 are determined.
[0005]
However, when I24 ′ <I25 ′, since M26 and M27 constitute a current mirror circuit, the size of I25 is suppressed to the size of I24. In this case, M29 operates in the non-saturated region, and M27 operates in the saturated region. Accordingly, the impedance of M29 becomes extremely small, because the impedance of M27 is increased, becomes zero drain-source voltage VDS of the M29, M2 7 drain-source voltage VDS of the VDD. Therefore, the output voltage is 0V.
[0006]
On the other hand, when I24 '>I25', M29 operates in the saturation region and M27 operates in the non-saturation region, so that VDD is applied to M29 and the output voltage becomes VDD.
The output characteristics of the MOSFET used here are shown in FIG. When the MOSFET is operated in the saturation region, since the change in the drain current IDS is small with respect to the change in the drain-source voltage VDS, the constant current characteristic of the MOSFET can be maintained and the operation is stabilized.
[0007]
Therefore, M21, M22, M23, M24, and M25 of the input stage circuit 52 of FIG. 4 are operated in the saturation region. Since the gate threshold voltage Vth of each MOSFET is 0.6V in normal manufacturing, it is assumed here that Vth = 0.6V.
The minimum voltage at which the input stage circuit 52 operates will be described. The gate threshold value of each MOSFET is 0.6V, the gate input voltage VINP2 of M22, the gate input voltage VINM2 of M23, and VINM2 = 1V.
[0008]
The drain-source voltage of M21, M24, and M25 is VDS = 0.6V, and the drain-source voltage of M23 is VDS = VINM2-Vth = 1V-0.6V = 0.4V. Therefore, the minimum power supply voltage that can be operated is VDD = (VDS of M21) + (VDS of M23) + (VDS of M24) = 0.6V + 0.4V + 0.6V = 1.6V. However, in order to make the circuit operate stably, this value is usually increased by about 0.2V. Therefore, the practical minimum power supply voltage of the conventional comparator is VDD = 1.8V.
[0009]
FIG. 6 is a diagram illustrating DC characteristics (output characteristics) of a conventional comparator. A case where VDD = 2V, a case where VDD = 1.5V and VIPM2 = 1V are shown.
When VDD = 2V and VINP2> VINM2, as described above, I25 becomes smaller than I24, V27 of M27 becomes 0V, and VDD is applied to M29. Therefore, the output voltage is 2V.
[0010]
On the other hand, when VDD = 2V and VINP2 <VINM2, as described above, I25 is suppressed to the magnitude of I24, VDD is applied to M27, and VDS of M29 becomes 0V. Therefore, the output voltage is 0V.
When VDD = 1.5V, the voltage between the drain and source of M21, M24, and M25 becomes lower than Vth, and no current flows through these MOSFETs. For this reason, the input stage circuit 52 does not operate, and regardless of the magnitude of VINP2, VDD is applied to M27, and VDS of M29 becomes 0V. Therefore, the output voltage becomes 0 V regardless of the magnitude of VINP2, and does not function as a comparator.
Thus, in order to stably operate the conventional comparator, 1.8 V is necessary as the minimum voltage of the high potential side voltage VDD of the power source.
[0011]
[Problems to be solved by the invention]
In recent years, there has been a strong demand for lowering the voltage of power supplies used in portable devices and the like, and the main factor preventing this lowering is the high operating voltage of the comparator.
An object of the present invention is to solve the above-described problems and provide a comparator that operates at a low voltage.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, in the differential comparator that compares the input signal voltage with the reference voltage and selects and outputs either the ground voltage or the power supply voltage, the input signal voltage and the reference voltage are selected. An input stage circuit that inputs a voltage, compares the magnitudes thereof, and outputs an output signal to the output stage circuit is connected between the high potential side and the low potential side of the power supply. And the signal input unit, the signal input unit is composed of two rows of gate signal input units, and an output signal transmission unit is connected in parallel to the gate signal input unit. The input unit is individually connected to each of the two rows of input signal bias units constituting the bias unit, and the input signal bias unit and the gate signal input unit include a single-stage transistor, The output signal transmission part Switch and, possess the active load of the switch connected in series, the output stage circuit of the first and second output stage connected to the pair of transistors and said pair of transistors constituting the current mirror circuit in series A circuit input transistor is provided, and a signal from an output signal transmission unit connected in parallel to the two rows of gate signal input units is connected to the gates of the first and second output stage circuit input transistors .
[0013]
Said active load and said switch, formed by transistors, may transistors constituting the active load that make up each said first and second output stage circuit input transistor and the current mirror circuit.
Thus, by configuring the input stage circuit in two stages of the bias part and the gate signal input part, the operating voltage of the comparator can be lowered to about the threshold voltage of one MOSFET.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a circuit diagram of a principal part of a comparator according to a first embodiment of the present invention. In the following description, each MOSFET is represented by a number M.
The comparator includes a constant current circuit 1, an input stage circuit 2, and an output stage circuit 3. The constant current circuit 1 includes M0 and a current source circuit 7. The input stage circuit 2 has a circuit configuration in which a bias unit 4, a circuit unit in which a gate signal input unit 5 and an output signal transmission unit 6 are connected in parallel, and a circuit unit connected in series. The input stage circuit 2 is connected between VDD (here, VDD indicates the high potential side of the power supply or the power supply voltage) and the ground GND. The bias unit 4 is composed of M1 and M3 (which corresponds to the two columns of input signal bias units described in claim 1), the gate signal input unit 5 is composed of M2 and M4, and the output signal transmission unit 6 Consists of M5 and M6, which are active loads, and switches SW1 and SW2. The output stage circuit 3 includes M7, M8, M9, and Ma. The M0, M1 and M3, and M7 and M8 constitute a current mirror circuit. Here, a circuit related to the gate input signal of the input stage circuit 2 is divided into two systems, which are A part and B part, A part is M1 and M2, and B part is M3 and M4. Further, a circuit related to transmission of an output signal of the input stage circuit 2 is divided into two systems, which are a C part and a D part, the C part is M1, SW1, and M5, and the D part is M3, SW2, and M6. The MOSFETs constituting the A part and the B part, the C part and the D part, and the E part and the F part are symmetrical, and the sizes of these MOSFETs are the same. Here, M0, M1, M3, M7, and M8 are p-channel MOSFETs, and M2, M4, M5, M6, M9, and Ma are n-channel MOSFETs.
[0015]
The difference between the circuit of FIG. 1 and the circuit of FIG. 4 is that the output signal transmission unit 6 of the input stage circuit 2 is juxtaposed with the gate signal input unit 5, and the output signal transmission unit 6 is the switches SW1 and SW2 and the active load. This is a point constituted by M5 and M6.
Next, the operation of this comparator will be described. A bias current I0 is supplied, and equal bias currents I1 and I2 are supplied to M1 and M3. For example, when the gate input voltage VINM of M4 is made constant, the bias current I2 is distributed to I6 and I5, and a constant current flows. Next, when the gate input voltage VINP of M2 is changed from 0V which is the ground voltage to VDD which is the power supply voltage, the bias current I1 is distributed to I3 and I4 by the gate input voltage VINP of M2.
[0016]
If VINP <VINM, then I4 <I6 and thus I3> I5. When VINP> VINM, I4> I6, and therefore I3 <I5. Here, the magnitudes of the currents I7 and I8 flowing through the output stage circuit are proportional to I5 and I3, respectively. However, I8 is restricted by I7.
When VINP <VINM, I8 tends to be larger than I7, but is limited by I7, so that M8 operates in the saturation region and Ma operates in the non-saturation region. Therefore, the impedance of M8 becomes large, while the impedance of Ma becomes very small. Therefore, VDD is applied to M8, and the drain / source voltage VDS of Ma becomes 0V. Therefore, the output voltage output from the output terminal 8 is 0 V (ground voltage).
[0017]
When VINP> VINM, since I8 is smaller than I7, M8 operates in the non-saturated region, and Ma operates in the saturated region. Therefore, the drain-source voltage VDS of M8 becomes zero and VDD becomes Ma. To be applied. Therefore, the output voltage output from the output terminal 8 is VDD. In this way, the comparator operation is performed.
Next, the power supply voltage VDD required for the comparator will be described. The MOSFETs M1, M2, M3, M4, M5, and M6 are operated in the saturation region. When considering the minimum VDD for the operation of this comparator, it is an essential requirement to operate the B part and the D part stably.
[0018]
First, VDD in which the B section operates stably will be described. Since the MOSFET operates in the saturation region, the drain-source voltage VDS of M3 needs to be equal to or higher than the gate threshold voltage Vth, and the drain-source voltage VDS of M4 is (gate input voltage VINM−gate threshold voltage). Vth) or more is required. When Vth = 0.6V and VINM = 1V, the minimum power supply voltage VDD at which the part B operates is the sum of Vth of M3 and VDS (saturation region) of M4. That is, VDD = Vth + VDS = 0.6V + 0.4V.
[0019]
On the other hand, as described above, the drain-source voltage VDS of M3 in the D section is required to be equal to or higher than the gate threshold voltage Vth, and the drain-source voltage VDS of M6 is also required to be higher than the gate threshold voltage Vth. The minimum power supply voltage VDD at which the D section operates is the sum of the Vth of M3, the voltage drop of SW2, and the Vth of M6. If the voltage drop of SW2 is 0.1V, VDD = 2 * Vth + SW2 voltage drop = 2 * 0.6V + 0.1V = 1.3V. As described above, when the 0.2V power supply voltage is increased for stable operation, the practical minimum power supply voltage VDD is 1.5V.
[0020]
In this way, by setting the gate input signal unit 5 and the output signal transmission unit 6 in parallel, the practical minimum power supply voltage can be reduced from the conventional 1.8V to 1.5V.
FIG. 2 is a circuit diagram showing the principal part of the comparator according to the second embodiment of the present invention. 2 is a circuit in which a bias voltage VDC1 is applied to these gates using p-channel MOSFETs M15 and M17 instead of the switches SW1 and SW2 of the output signal transmission unit 6 of FIG. is there. VDC1 is sufficiently high so that the drain-source voltage VDS of M15 and M17 is 0.1 V or less. I10, I11, I12, I13, I14, I15, I16, I17, and I18 are bias currents and correspond to the bias currents in FIG.
[0021]
FIG. 3 is a DC characteristic diagram of the comparator of the present invention. This is a DC characteristic of the comparator when VDD1 = 2V and 1.5V and VINM = 1V. The comparator operates stably with either power supply voltage. Thus, by operating the switch in the non-saturation region instead of the MOSFET, the power supply voltage VDD1 of the comparator operating stably can be lowered by 0.3 V with respect to the conventional power supply voltage.
[0022]
【The invention's effect】
According to the present invention, the power supply voltage for operating the comparator can be lowered by paralleling the gate signal input unit and the output signal transmission unit constituting the input stage circuit.
[Brief description of the drawings]
FIG. 1 is a main part circuit diagram of a comparator according to a first embodiment of the present invention. FIG. 2 is a main part circuit diagram of a comparator according to a second embodiment of the present invention. 4 is a circuit diagram of a conventional differential comparator. FIG. 5 is an output characteristic diagram of a MOSFET. FIG. 6 is a DC characteristic diagram of a conventional differential comparator.
DESCRIPTION OF SYMBOLS 1 Constant current circuit 2 Input stage circuit 3 Output stage circuit 4 Bias part 5 Gate input signal part 6 Output signal transmission part 7 Current source circuit 8 Output terminal M0, M1, M3, M7, M8 p channel MOSFET
M2, M4, M5, M6, M9, Man channel MOSFET
M15, M17 n-channel MOSFET
SW1, SW2 Switches I0, I1, 12, I3, I4 Bias currents I5, I6, 17, I8 Bias current VDD Power supply high potential side / Power supply voltage VDC1 Bias voltage GND Ground

Claims (2)

In the differential comparator that compares the input signal voltage with the reference voltage and selects and outputs either the ground voltage or the power supply voltage, the input signal voltage and the reference voltage are input, and the magnitude is calculated. In comparison, an input stage circuit that outputs an output signal to the output stage circuit is connected between the high potential side and the low potential side of the power supply, and the input stage circuit is configured by two stages of a bias unit and a signal input unit The signal input unit includes two rows of gate signal input units, and the gate signal input unit includes an output signal transmission unit connected in parallel, and each of the gate signal input units configures the bias unit. Two input signal bias units connected to each other, the input signal bias unit and the gate signal input unit each include a single-stage transistor, and the output signal transmission unit includes a switch, In series with the switch Possess the active load to continue, the output stage circuit comprises a first and second output stage circuit input transistors connected respectively in series to the pair of transistors and said pair of transistors constituting a current mirror circuit, wherein A comparator characterized in that a signal from an output signal transmission unit connected in parallel to two rows of gate signal input units is connected to the gates of the first and second output stage circuit input transistors . It said active load and said switch, formed by transistors, claim 1, characterized in Rukoto transistors constituting the active load to configure each of the first and second output stage circuit input transistor and the current mirror circuit Comparator described in 1.

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