JP3741314B2 - High-speed signal transmission system - Google Patents

Description

【００６０】
から、ｄ＝３９μｍが求まる。ここでは分岐パッドが存在するが、バス構造は終端まで同じであり、特性インピーダンスの不整合を心配する必要は無い。平行等長配線を前提にすると、パッドピッチはｗ／２＝１００μｍとなり、現状技術で設計可能である。ｈ２の厚みをプリント配線板プリプレーグの標準である６０μｍにすれば理想的な層構造となる。
【００６１】
一方、パッケージ配線はチップパッドピッチにしたがって設計する必要がある。ここでチップパッドピッチを５０μｍとすると、パッケージ上スタックトペア配線のｗは１００μｍとなる。上式よりｄ＝１９．５μｍとなる。これでチップパッドから終端抵抗まで２８Ω伝送線路設計となるが、ファンアウト部の配線長さが異なるため、図１８のような工夫をする。
【００６２】
ファンアウト配線に対する等長配線の公知例としてジグザグ蛇行構造のミアンダー配線が良く採用されているが、隣接効果で電磁界的に複雑な伝送特性になるため、図１８のように円弧が等長であるようにレイアウトする。ミアンダーのような折れ曲り反射が無いため、スムーズな伝送が期待されるだけでなく、隣接配線間距離も比較的広く取れるためクロストークに対しても有利な配置となる。
【００６３】
幾何学的な円弧で設計する計算式を構築すると、図１９にしたがい、次のようになる。ここで、Ａ，Ｂをパッドとする。弦ＡＢ＝１₁ は最外端パッド間の直線距離とする。これを変数とし隣接パッド間において円弧ＡＢを一定とする半径ＯＰ＝ｒ₁ を見出す関係式を導く。∠ＡＣＯは直角、∠ＡＯＢ＝θ₁ とする。いま、線分ＰＣ＝ｒ₁ −ｈ₁ 、ＣＯ＝ｈ₁ とすると、（１₁ ／２）² ＝ｒ₁ ² −ｈ₁ ² が得られ、θ₁ ／２＝ｔａｎ^-1（１₁ ／２ｈ₁ ）、円弧ＡＢ＝ｒ₁ θ₁ ［ラジアン］である。これらの式からｈ₁ を適当に決めるとｒ₁ が求まる。円弧ＡＢ＝ｒ₁ θ₁ は一定として次以降のパッド間距離１_x に対して次々とｈ_x とｒ_x を求めることができる。ｌ_x と各パッド間の半径ｒ_x は、
【００６４】
【数２】

【００６５】
もちろん、円弧ＡＢは楕円や任意の高次曲線でもよく、急激な曲がりのないことが本発明の特徴となる。
さて、パッケージを使用した構造案を提示したが、最近パッケージを省略してプリント配線板上にチップを直接接続し、ファンアウト配線を経た後並行バス配線とする設計手法がよく用いられているが、線幅ｗに応じてペア線間距離ｄを変更することは同一基板上で作りにくい。たとえ作ったとしてもコスト高になり、その段差部分の接続信頼度が低下する。次なる提案はペア線路間ｄを一定にしてｗを変える構造に関するものである。図２０にこれを示す。ファンアウト構造の部分はマイクロストリップ線路かストリップ線路とし、並行バス線路はスタックトペア線路として使い分けることを提案する。
【００６６】
マイクロストリップ線路やストリップ線路はグランド面に対して電界が広がるため、単位長さ当たりのキャパシタンスC₀が増大する。その結果
【００６７】
【数３】

【００６８】
は同一線幅ｗであれば小さくなる。逆にＺ₀ を一定とすればｗを小さくできることになる。マイクロストリップ線路の近似式（Harold A. Wheeler ）（図１５の記号参照)は、
【００６９】
【数４】

【００７０】
となる。Ｚ₀ ＝２８Ωとすると、ｄ＝３９μｍでｗ＝１７０μｍが算出される。導体厚み（ｔ＝２５μｍ）の影響を補正するには、経験的に導体厚みｔ（２５μｍ）をマイナスすればよく、補正された線幅ｗ＝１４５μｍが得られる。スタックトペア線路ｗ＝２００μｍに対して同じペア線間スペースｄ＝３９μｍで、マイクロストリップ線路にすると線幅ｗ＝１４５μｍまで微細化が可能となる。
【００７１】
チップパッドの間隔が５０μｍピッチ、ファンアウト配線の線幅がｗ＝１００μｍの設計に対して線幅ｗ＝１４５μｍは不足であるが、パッドの極近傍で絞り込むことで対応が可能となる。絞り込 む配線長は分岐配線長と同じ考えでよく、コラム、ビアホール等のインピーダンス不整合の長さに対する対応と同様に（６×絞込み長さの総合遅れ時間）＜（立ち上がり時間）とすればよい。
【００７２】
メモリチップが信号を発信するときは図２１に示す方法をとる。メモリのドライバより発信した信号はバス線路の両サイド（７２，７３）に信号が流れる。同じ特性インピーダンスであるため、エネルギ保存の法則から、信号電圧は１／２となる。右方向へ流れる信号は無駄信号であり、終端に配置したレシーバが感応しないようにしなければならない。さらに、ここで全反射して左のコントローラチップに戻ると、不要信号であるにもかかわらず感応する。これも防止しなければならない。メモリがストローブされて信号が発信するとき、右端のレシーバはその信号を受けてノンアクティブになると共に、終端抵抗（７０）がアクティブになって無駄信号はここで消滅する。
【００７３】
一方、コントローラチップ（７４）に到達した、１／２正規信号はコントローラのレシーバ回路（遺伝的アルゴリズム回路を含む）を駆動し、そこに付属している終端抵抗（７５）で吸収され消滅する。しかし、すでに記憶した全反射信号変形から、１／２だけ修正した波形でセンスアンプに取り込まれるため、正しい波形で、正しいタイミングで認識する。
【００７４】
ドライバ、レシーバともに外側から見たとき常にハイインピーダンスであることから、１ビットのバスで送受信回路を併設することは何ら問題のないことになる。
・遺伝的アルゴリズム回路
遺伝的アルゴリズム回路により調整される回路の１実施例を示す。
【００７５】
以上に示す回路は伝送路の特性を規定するＬ₀ ，Ｃ₀ 以外の独立したＬとＣを存在させることを極力排除し、周波数特性を無くしたものである。すなわち、式で表すと特性インピーダンスＺ０は、
【００７６】
【数５】

【００７７】
となり、イマジナリパート（虚数部分）と各周波数を消去した形、言い換えればインピーダンスが純抵抗成分である伝送線路を構成したことにある。
しかし、いくら完全に設計しても製造条件のばらつきなどで寄生する独立した微小な相互インダクタンス（Ｍ）と容量（Ｃ）が存在することになる。これを表現すると図２５のようになる。図１０に見られる伝送線路は電磁界がほぼ閉じた伝送線路であり、上記の式にしたがい、同軸ケーブルに近い特性をもっている。そこで図２４では伝送線路的表現を取っている。この伝送線路間に弱いＭＣ結合が存在するという概念となる。線路間以外にも筐体やビアホール、コネクタなどでのＭＣ結合が考えられ、これらの弱いＭＣ結合による問題は低周波では無視できるものである。しかし、１０ＧＨｚ以上のパルスは回路全体のわずかな寄生的ＭとＣが大きく影響する。それをアドミッタンスＹで表すと、
Ｙ＝ｊ（ωＣ−１／ωＭ）
となり、ωの増大で大きく変化するだけでなく、ωＣ−１／ωＭ＝０の条件で共振する。このように避けられない実用的問題を排除する回路の挿入が不可欠になる。本発明は、遺伝的アルゴリズムでこの寄生ＭとＣを相殺するＬＣネットを自動的に作り、ドライバ信号に重畳させることを提案する。その構成は、
（１）高速信号を確保するため、波形整形は純粋のＬＣＲネットとし、そのどの部分を動作させるかは、電荷ポンプアップ、ポンプダウン型トランジスタで行う構成とする。
【００７８】
（２）テスト信号を発信して、全反射信号を終端抵抗で取り込むが、その電圧を感知し、波形解析を行う。その解析ステップは波形整形の相補的逆変換であるＬＣＲネットとする 。
【００７９】
（３）テスト信号補正を行った遺伝的アルゴリズム回路はシステム変化が起こるまで、記憶しているものとする。
このアルゴリズムを図示すると図２２のようになる。
【００８０】
ＬＣＲネットワーク内の回路接続を制御トランジスタで自由に変更可能な構成として、受信端で本来のディジタル信号波形が受信できるように受信波形を検出してそれと相補的になる波形に送信波形を調整する。この調整は、遺伝的アルゴリズムにより実行される。その波形の一例を図２３に示す。遺伝的アルゴリズムは、確率的探索手法の一つであり、(1) 広域探索において有効に作用し、(2) 評価関数値以外には微分値等の派生的な情報が必要でなく、(3) しかも容易な実装性を持つ、アルゴリズムである。従って、本発明においては、調整パラメータの探索に遺伝的アルゴリズムを用いると好適である。この調整方法は他の確率的探索方法でもよく、遺伝的アルゴリズムに限らず、山登り法、焼き鈍し法、枚挙法、進化政略、タブーサーチ法のいずれか、あるいはこれらの組み合わせでもよい。
【００８１】
なお、遺伝的アルゴリズムの基本回路および調整方法は、特願平１１−２４００３４号「電子回路およびその調整方法」（特開２０００−１５６６２７）を準用する。回路が固定的である限り、修正は１度限りであり、システム出荷段階で遺伝的アルゴリズムを実行するコンピュータは外付けでよく、システムに包含させる必要はない。
【００８２】
遺伝的アルゴリズムのＬＣ回路を一例で示すと図２６のようになる。図２６の遺伝的アルゴリズム出力ＬＣネット８１は模式的に表現しているが、その具体的回路を図３４〜図３８に示す。
【００８３】
図３３を用いて遺伝的アルゴリズムによる波形の調整方法を述べると、以下のとおりである。
・共通概念
受信側できれいな波形になるように送信側の波形を調整（波形整形）して、信号伝送の品質を上げる。いわゆる等化の一種である。
【００８４】
波形評価回路９１は波形の善し悪しを評価して電圧を出力する回路である。この結果の値を遺伝的アルゴリズムの評価関数値として用いて、遺伝的アルゴリズム（ＧＡ）により波形整形の状態を最適に制御する。具体的には、図３３において、ドライバは、送信データを差動対の伝送線路に出力するもので、波形調整機能を有する。レシーバは伝送線路からの信号入力から受信データを得るものである。波形評価回路９１は、レシーバーで受信する信号波形の歪みの程度を定量的に評価する機能を有する回路であり、受信波形の評価結果に対応する電圧値を出力する。外部装置９２は、確率的探索手法である遺伝的アルゴリズムを実行して、波形の調整値をドライバに出力する。ドライバー出力の送信波形は外部装置９２からの制御信号により調整される。ここで、波形評価回路９１の出力する電圧値は、遺伝的アルゴリズムにおける評価関数値であり、この電圧値が外部装置９２に入力され、受信信号波形の評価値が最良となるように遺伝的アルゴリズムにより波形の調整値が探索される。その結果、波形の最適化が行われる。
【００８５】
波形整形の方法として、次の、周波数軸による調整と時間軸による調整の２つがある。
・周波数軸による調整（図３４）
周波数軸による調整の一例として、図３４に示す等化フィルタを用いる構成について説明する。図３４の等化フィルタの回路は、図３３のドライバに実装される。該等化フィルタ回路は、伝送線路で発生する信号波形の歪みに対して、周波数軸上での振幅の補償と、周波数軸上での位相の補償を行い受信波形の歪みを最小化する。振幅の調整を主に行う回路図３４（ａ）と位相の調整を主に行う回路図３４（ｂ）の少なくとも２種類の回路を縦続接続した等化フィルタ回路で波形整形を行う。
【００８６】
この回路において、図中の抵抗Ｒの抵抗値とコンデンサＣの容量値を、遺伝的アルゴリズムによって受信波形の歪みが最小となるように調整する。抵抗ＲとコンデンサーＣのみの調整では、等化フィルタの定抵抗条件（反射信号がない最適条件）を満たすことが困難であり、一般にこの条件では特性の解析がきわめて困難な場合であるが、受信波形が最良（最小歪み）となる送信波形をＧＡが検索してくれる。
（以下本文中において、「￣」（オーバーライン）を付す場合、表記の制限の都合上、「 」（アンダーライン）に置き換えて表記する。）
・時間軸による調整（図３５〜図３７）
時間軸による調整の一例を、図３５〜図３７を用いて説明する。ここで説明する回路は図３３のドライバに実装される。まず、図３５は送信波形を時間軸上で調整する回路の動作原理を示す。この回路は、切替回路９３（スイッチアレイがＳ１〜Ｓｎ、それに応じた出力信号がＰ１〜ＰｎおよびＰ１〜Ｐｎ、ここでＰｎとＰｎは相補信号）、差動入力データを所定のタイミングだけ遅延させる遅延回路９４、アナログの直流可変定電流源９５（各電流値をＣ１〜Ｃｎとする）、高速スイッチ９６（切替回路９３からのデータ出力信号Ｐ１〜Ｐｎ，Ｐ１〜Ｐｎを受けて相補的にスイッチがＯＮ，ＯＦＦする）から構成されている。
【００８７】
送信データである一組のデータ入力（この相補信号はデータ入力）のデジタル信号を受け、最初に切替回路９３のスイッチＳ１を経由してＰ１，Ｐ１の信号が変化し、Ｐ１，Ｐ１に対応する高速スイッチ９６を動作させる。これによりＣ１に対応する可変定電流源９５の出力電流（電流の設定値がＣ１）を切り替えて、出力電流Ｉｏｕｔ，Ｉｏｕｔの一要素を得る。
【００８８】
同様に一組のデータ入力のデジタル信号は、各遅延回路９４を経由して所定の複数の遅延のタイミングが設定され、一連の信号Ｐ２〜Ｐｎ、Ｐ２〜Ｐｎが生成される。これらは次々と高速スイッチ９６を動作させる相補信号Ｐ２〜Ｐｎ、Ｐ２〜Ｐｎであり、各可変定電流源９５の各電流Ｃ２〜Ｃｎを通電する。
【００８９】
各高速スイッチは出力側が非反転信号、反転信号のそれぞれについてすべて並列に接続されているので、合成された相補電流Ｉｏｕｔ，Ｉｏｕｔを得る。高速スイッチ９６の各部においては、入力データから所定の複数のタイミングを持つ電流波形が重畳され、波形整形が行われる。
【００９０】
上記で合成された電流Ｉｏｕｔ，Ｉｏｕｔは、図中、データ出力およびデータ出力として出力される。この出力信号が図３３におけるドライバの出力信号である。伝送線路での波形歪みを補償する波形が出力されるとレシーバでの入力波形は歪みが最小となる。
【００９１】
図３３における波形評価回路９１の出力電圧値をもちいて外部装置９２で実行する遺伝的アルゴリズムにより、可変定電流源９５の電流値Ｃ１〜Ｃｎおよび切替回路９３のスイッチＳ１〜Ｓｎの設定が最適化される。その結果、レシーバでの受信信号の歪みが最小となる送信波形に自動調整される。
【００９２】
高速スイッチ９６を５組（Ｐ１，Ｐ１，Ｐ２，Ｐ２，Ｐ３，Ｐ３，Ｐ４，Ｐ４，Ｐ５，Ｐ５）で構成した時の、各スイッチを流れる電流の波形（波高値はＣ１〜Ｃ５に相当）を図３６に示す。各々の高速スイッチ９６（Ｐ１，Ｐ１〜Ｐ５，Ｐ５に対応）を流れる電流の合成されたものがＩｏｕｔおよびＩｏｕｔである。各高速スイッチ９６を流れる電流は差動になっているから、その合成であるＩｏｕｔ，Ｉｏｕｔも差動電流となる。図３５に示した原理構成を実装例として示したものが図３７である。各動作要素ブロックは同一番号９３，９４，９５，９６として示した。ここでスイッチ要素になるトランシスタはＦＥＴで表現したが、バイポーラトランシスタでも可能であ る。
【００９３】
このような波形整形を行わない場合と上記のように時間軸上で波形整形を行った場合の比較例を図４２，図４３に示す。波形整形を行わない図４２の場合、図４２（ａ）の理想的な矩形波１１０を送信波形（ドライバの出力電圧）として送信した場合の伝送線路を通過した後の受信波形を計算機上でシミュレーションすると、図４２（ｂ）の１１１のような受信波形が得られる。これは高い周波数成分が伝送線路で減衰したためで、デジタル信号の「１」と「０」が曖昧になっている。
【００９４】
一方、遺伝的アルゴリズムによって時間軸上で波形整形を行った場合の送信波形１１２、受信波形１１３は図４３（ａ），（ｂ）に示される。この場合、伝送線路を通過した受信波形１１３のデジタル信号の「１」と「０」を理想に近い波形にするべく送信波形１１２が調整されるので、受信波形１１３がデジタル信号の「１」と「０」に対応する電圧地となり、電圧のずれの少ない、理想状態に近い波形が得られている。
【００９５】
なお、他の実施例としては、線路の構成の新しい構成方法としてスタックドペア線路（図１０）で上下の線路幅を変えることで線路の位置ずれに対する線路の特性インピーダンスの変化を小さくできる。また、このとき、ペア線路の上下の絶縁層の厚さを変えることでコモンモードインピーダンスを同じにできるので、このような工夫をこの発明に追加してもよい。
【００９６】
【発明の効果】
以上述べたように、種々の工夫に基づいた本発明の高速信号伝送システムによれば、２ＧＨｚ以上の高速クロック周波数のＬＳＩチップに対応し、チップクロックと同じ伝送クロックのＩ／Ｏバスが実現できる。
【００９７】
これは、従来５３３ＭＨｚしか実現できなかったＩ／Ｏバスを飛躍的に高速にすることができるという顕著な効果を奏する。
その基本は、２０ＧＨｚに達する高速パルスの伝送帯域に巧妙に整合あせる工夫にあり、また浮遊容量や寄生インダクタンスを巧妙に吸収させ、あるいはキャンセルさせる工夫にある。
【００９８】
これら工夫は「新規性」があり、また、遺伝的アルゴリズムの活用も見逃せない効果を奏する。
かくして、ＬＳＩクロックと整合したＩ／Ｏバンド幅が確保でき、ＬＳＩチップの高速化に対応し、メモリとのデータ転送を含めたデータ処理システム全体の高速化が実現できることになる。
【図面の簡単な説明】
【図１】ＬＳＩ設計の一般的な配線長の分布を示す図である。
【図２】本発明のドライバとレシーバを接続する構造の一例を示す図である。
【図３】本発明の３５ＧＨｚのパルス実効周波数相当のシミュレーションモデル回路を示す図である。
【図４】図３のシミュレーション結果を示す図である。
【図５】本発明の図２におけるｎＭＯＳ構造のドライバの断面構造の一例を示す図である。
【図６】本発明のバイポーラトランジスタのキャリア再利用回路を示す図である。
【図７】本発明のレシーバ端の回路の一例を示す図である。
【図８】ドライバの平面構造の一例を示す図である。
【図９】ドライバトランジスタ部の断面構造の一例を示す図である。
【図１０】本発明の伝送システムに好適な伝送線路を示す図である。
【図１１】不均質絶縁層における導体周辺の絶縁層の実効比誘電率整合の一例を示す図である。
【図１２】コラム、ビアホールなどインピーダンス不整合の長さのモデルを示す図である。
【図１３】５０Ωを基準にしたミスマッチインピーダンスと多次反射エネルギの通過率を示す図である。
【図１４】バススイッチタイプドライバの一例を示す図である。
【図１５】チップ間伝送線路接続構造を示す図である。
【図１６】チップパッド配列の制約を示す図である。
【図１７】パッケージを用いたときのファンアウト配線構造を示す図である。
【図１８】等長ファンアウト配線の一例を示す図である。
【図１９】円弧ＡＢを一定にして弦ＡＢを変数にするためのモデル図である。
【図２０】ペア線路間の距離を一定にして線幅を変える線路構造の一例を示す図である。
【図２１】メモリ側からの送信回路を示す図である。
【図２２】信号修正回路アルゴリズムを示す図である。
【図２３】アルゴリズムを説明する波形の処理ステップの一例を示す図である。
【図２４】本発明のドライバとレシーバを接続する構造(遺伝的アルゴリズム回路含まず)の他の一例を示す図である。
【図２５】線路間の寄生結合素子を示す概念図である。
【図２６】遺伝的アルゴリズムの回路モデルの一例を示す図である。
【図２７】ｐＭＯＳトランジスタの構造と容量成分の説明図である。
【図２８】ゲート電圧とｐＭＯＳバラクタ容量の関係を示す図である。
【図２９】ｎＭＯＳトランジスタとバラクタを持つ基本回路の一例を示す図である。
【図３０】ＣＭＯＳバラクタの構造を示す図である。
【図３１】ｐＭＯＳとゲート電圧の関係を示す図である。
【図３２】ｎＭＯＳとゲート電圧の関係を示す図である。
【図３３】等化による高速データ伝送の調整方法の説明図である。
【図３４】図３３において、波形を周波数軸上で調整する回路を示す図である。
【図３５】図３３において、波形を時間軸上で調整する回路の原理説明図である。
【図３６】図３３において、波形を時間軸上で調整する場合の各スイッチの電流波形と出力電流波形を示す図である。
【図３７】図３５において、波形を時間軸上で調整する回路の実装例を示す図である。
【図３８】送端終端のみグランドに落としたＦＥＴ１個の基本スイッチ回路の例を示す図である。
【図３９】図３８の回路の波形図である。
【図４０】実測基板のトランジェント解析回路の例を示す図である。
【図４１】図４０の回路の波形図である。
【図４２】波形整形を行わない場合の送信波形と受信波形を示す図である。
【図４３】図３３の波形整形を行った場合の送信波形と受信波形を示す図である。
【符号の説明】
１ ドライバ
２ レシーバ
３ 送信端
４ レシーバ端
５，６ 受端整合抵抗
７，８，９ トランジスタ・オン抵抗
１０ 伝送線路
２１、２２ トランジスタ
５１ 終端抵抗
５２ 遺伝的アルゴリズム回路
５３ ドライバ
５５ レシーバチップ
９１ 波形評価回路
９２ 外部装置
９３ 切替回路
９４ 遅延回路
９５ 可変定電流源
９６ 高速スイッチ[0001]
BACKGROUND OF THE INVENTION
The present invention responds to a demand for smoothing the signal processing of an LSI of a high-speed LSI chip whose digital signal clock frequency is 2 GHz or more, and is a chip that is connected to the high-speed LSI chip and exchanges signals with the LSI chip. In the external line, the bandwidth of the input / output circuit (hereinafter referred to as I / O) matched with the LSI clock is ensured, that is, the bandwidth is matched to make the chip clock and the I / O bus transmission clock the same. Related to technology.
[0002]
[Prior art]
In recent years, the clock frequency for operating an LSI chip has reached 2 GHz, but the frequency of the external line for exchanging this signal is only 533 MHz (Rambus protocol), and the bandwidth required to load the signal into the LSI is required by the LSI. It is in a state that is lacking against. In order to make LSI signal processing smooth, cache memory is embedded in both logic chips and memory chips to cope with insufficient bandwidth, but not only requires a large cache memory area but also requires extra address calculation and complicated architecture. become. If an I / O bandwidth consistent with the LSI clock can be secured, a cache memory is unnecessary and the system is simple in architecture. It is fundamental to digital systems that chip I / O is essentially the same as the number of processing bits in the chip, and in order to match the bandwidth, the chip clock and the I / O bus transmission clock must be the same. Don't be. In the era of entering the GHz band in the future, improvement of the bus clock is urgent. Even if the transmission line which is the basic configuration of the bus has the characteristics, the GHz band clock does not pass. In other words, GHz transmission is possible only when the driver / receiver and the package structure that wraps the driver / receiver are all ready to pass high-speed signals.
[0003]
On the other hand, predicting the future in the chip, Intel announced a MOS structure with a gate length of 20 nm at 2001 Symposium on VLSI Technology (2001.6 Kyoto), and said that it can process 20 GHz digital signals (predicted to be realized in 2007). However, in order to pass a digital signal of 20 to 50 GHz with a 10 mm square in-chip wiring, a configuration based on a new idea that is a departure from the concept of the RC charge / discharge circuit is required. In other words, to create a unified environment across the entire system, it is necessary to construct a system that is fundamentally renewed.
[0004]
[Problems to be solved by the invention]
An object of the present invention is to connect a high-speed LSI chip with a clock frequency of 2 GHz or more while affirming the conventional system configuration and component configuration as much as possible, and several tens of GHz to an external line of the chip that exchanges signals with the LSI chip. It is to realize a transmission system that transmits (transmits) a band digital high-speed signal.
[0005]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is based on a device structure that automatically pumps up and down a transistor carrier, a stochastic search method such as a genetic algorithm that feeds back received information and adjusts the waveform on the transmitting side. We propose to insert a circuit to be adjusted (hereinafter referred to as a genetic algorithm circuit, etc.), create a transmission line for the wiring that goes out of the transistor, and create a configuration that eliminates the common power supply of the circuit. That is, in the pulse signal transmission in the GHz band, it is required to limit the process of moving the pulse energy in the circuit or the line (process of changing the charge Q) as much as possible and to eliminate the discontinuity that causes the reflection. It is done.
[0006]
That is, the high-speed signal transmission system of the present invention is connected to a high-speed LSI chip with a clock frequency of GHz band, and the logic of the transistor, the memory circuit, etc. over the entire electronic circuit such as the transmitting end and the terminating end are input differentially and differentially. In a high-speed signal transmission system having an output line and an off-chip line for exchanging signals with the LSI chip, which has no branch wiring, for confirming a reference potential on one of the transmission end side and the termination side of the external line on the chip It has a connection to the power source or the ground, but it does not have a connection to the power source or the ground at the terminal end or transmitting end opposite to the transmitting end or the terminal end side where the reference potential is confirmed. Furthermore, the power supply line of the system is a power supply / ground pair line structure, and each element circuit of each minimum logic element and memory element circuit is connected by one dedicated pair line. .
[0007]
In addition, the high-speed signal transmission system of the present invention is connected to a high-speed LSI chip with a clock frequency of GHz band. In a high-speed signal transmission system having an output and an off-chip line for exchanging signals with the LSI chip, which has no branch wiring, a MOS differential sense amplifier is connected to the terminal, and signal transmission on the path An adjustment circuit is added to the output circuit so that the received waveform is correctly transmitted to the sense amplifier by analyzing and detecting the defect by the waveform analysis circuit and shaping the transmission waveform, and the adjustment circuit is adjusted by the stochastic search method. It is characterized by that. Further, the sense amplifier is composed of a MOS FET having a gate capacitance of 10 fF or less, and the probabilistic search method includes genetic algorithm, hill climbing method, annealing method, enumeration method, evolutionary strategy, taboo One of the search methods or a combination thereof is characterized.
[0008]
Further, the transmission line differentially output via the circuit adjusted by the stochastic search method is matched with the characteristic impedance from all transmission ends to the termination, and the sense amplifier combines the transmission waveform and the total reflection waveform. A terminating resistor is inserted on the transmission end side so that the total reflection waveform is received and re-reflected from the transmission end again.
[0009]
Further, the connection line (signal transmission line, power supply / ground pair line) is characterized in that the TEM mode is maintained, and the line has a structure in which electromagnetic waves are leaked into the air. A high dielectric constant material is coated so that the effective dielectric constant of the portion matches the internal dielectric constant. Furthermore, the transmission line is any one of a pair coplanar, a stacked pair, a guard stacked pair, and a guard coplanar structure.
[0010]
In addition, when the circuit is composed of a plurality of bits, the physical structure is relatively the same over the entire line, and the length is the same length, and the parallel length is basically used. An arc-shaped wiring is used for equal length.
[0011]
Furthermore, the active elements of the driver circuit and the receiver circuit are Si or SiGe MOS-FET (field effect transistor) or GaAs n-channel MES-FET, differential output without ground connection and differential input circuit, Shotot high speed It is characterized in that it is composed of a bipolar differential circuit or a bus switch circuit, and is characterized in that the same MOS / FET, MES / FET, and bipolar transistor structure varactor are arranged for all transistors in a complementary manner. . Furthermore, the above-described case is characterized in that the common well is electrically floated.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
In order to describe the present invention in more detail, it will be described with reference to the accompanying drawings.
LSI chip I / O driver / receiver circuit configuration
First, a circuit for exchanging signals according to the present invention is shown in FIG. Here, the configuration of the driver 1 and the receiver 2 enabling differential output is described. There is a ground connection 3 on the transmitting end side, but the receiver end 4 has no ground connection. In FIG. 2, the signal transmission line is shown as a coaxial line for the sake of simplicity, but is actually a pair line (parallel two lines) as shown in FIG. The same applies to FIGS. 5, 6, 14, 21, 21, 24, 25, and 26.
[0013]
First, an electromagnetic concept will be described as background knowledge of a phenomenon when operating at high speed.
In general, a pulse as a signal is a composite wave including many harmonics of a sine wave. If the clock frequency of the pulse is the fundamental wave (energy rate about 82%), the third harmonic with about 9% energy, the fifth harmonic with about 3% energy, and the seventh harmonic with 2% energy It is a synthesis of a 9th harmonic with 1% energy and a harmonic with small energy at odd multiples. Looking at the energetically problematic harmonics on the safe side, problems up to an order of magnitude higher than the pulse clock frequency should be discussed. That is, for example, if there is no 20 GHz transmission band for a 2 GHz pulse, waveform distortion occurs in the pulse. Further, even when the rise time tr (fall time tf) is steep even at the same pulse frequency, the energy of the higher-order high frequency is higher, and assuming the frequency f of the band necessary for transmission from the rise time, f = 0.35 / tr. Or f = 0.35 / tf. This is termed the pulse effective frequency. As a matter of course, this transmission band includes a pulse effective frequency.
[0014]
It is well known that sinusoidal energy transmitted at an electromagnetic wave velocity causes resonance with respect to a transmission distance that becomes a wave node. The minimum node is a quarter wavelength (λ / 4). When the resonance of the high-order harmonic described above occurs, the transmission conductance of the sine wave becomes ∞ (infinite), that is, the resistance becomes 0, and the transmission is greatly different from the finite conductance of other sine waves. That is, it is amplified. In extreme cases, harmonics with energy of several percent are transmitted with the same energy as the fundamental wave, and the pulse waveform is greatly disturbed and at the same time causes electromagnetic radiation.
[0015]
In the case of the aforementioned Intel CPU, the problem is up to the ninth harmonic of the clock frequency of 20 GHz. This is a sine wave of 180 GHz. The electromagnetic wave velocity of the line transmitting the field having the relative dielectric constant εr = 4 is 1.5 × 10⁸ Since m / s, 1/4 wavelength of 180 GHz λ / 4 = 210 μm. Therefore, in order to avoid the resonance, the wiring length in the LSI chip cannot be over 210 μm. If necessary, a repeater circuit must be inserted. Practically, the wiring length that is a problem due to delay due to RC charging / discharging is less than this, and all the global wiring in the LSI chip must be a transmission line that can withstand high frequencies in order to pass the harmonic components. become.
[0016]
As a general theory of LSI design, the distribution of wiring length is as shown in FIG. A long wiring is a so-called global wiring between LSI functional blocks. As shown in FIG. 1, Kazuya Masashi of Tokyo Institute of Technology proposes to separate a part that does not need to be a transmission line (lumped constant circuit part) and a part that must be a transmission line (distributed constant circuit). It is realistic that the present invention also exists within the scope of this proposal. Assuming that the circuit configuration that requires long wiring is 10% of the LSI, the countermeasures for the occurrence of problems at high frequencies according to the present invention will be described.
[0017]
A switch and a power source are required to obtain the driver's pulse output signal. However, when a large amount of current flows instantaneously from a state where no current flows, the current transition gradient di / dt becomes steep and a voltage (Ls: parasitic inductance) of v = Ls (di / dt) is generated. Then, the power supply Vdd instantaneously drops by this voltage v (Vdd−v). An increase in clock frequency by one digit corresponds to an increase of v by one digit in the same wiring structure. When the parasitic inductance Ls in the circuit is roughly estimated, it becomes 10 pH when the wiring length is 10 μm. Conventionally, if the circuit is based on 10 pH, in order to improve the frequency by one digit, 1 pH, that is, the wiring length must be 1 μm. Alternatively, in order to maintain the 10 μm wiring, it is necessary to set Ls = 0.1 pH or make the current constant. However, these are impossible in a lumped constant circuit design. However, this is possible with a distributed constant circuit. Now consider a concrete circuit.
[0018]
When the signal rise tr in the GHz band is set to tr = 10 ps or less, the pulse effective frequency is 35 GHz or more, so that the conventional circuit does not operate at all. A current switch type driver using an ECL circuit having a long history is intended to eliminate this problem. But this also doesn't work at all. The circuit shown in FIG. 2 for realizing this is a differential circuit made of one stage of n-MOS instead of ECL. FIG. 24 shows another embodiment similar to that of a CMOS. Also in FIG. 24, the bypass capacitor at the receiver end is separated from the gate of the receiver and thus does not fall to the ground.
[0019]
Usually, a latch exists in front of the driver and is a flip-flop circuit. Since this circuit inevitably has a differential output terminal, a differential switch can be relatively easily made up of n-MOSs arranged complementary to the input signal to the driver. In a circuit in which a large number of transistors are arranged, the pn junction capacitance is increased by the number of transistors, and not only a large amount of superimposed instantaneous current flows, but also it is necessary to discharge this when switching signals, thereby inducing a delay in switching operation. . The driver circuit for preventing this must be configured with the minimum number of transistors as shown in FIG. Resistor R connected in series with this transistor_E In (3), a diffusion resistance that causes pn junction capacitance is not used, and a metal film resistance made of tungsten, molybdenum, silicide thereof, or the like is desirable.
[0020]
Although the receiver of FIG. 2 is expressed as a logic circuit diagram, it may be the same circuit as the driver circuit, and the reception differential signal is received by the gate of the differential receiver and is not connected to the ground at this portion. Details thereof will be described later.
[0021]
Let's confirm the usefulness of this circuit by simulation. FIG. 3 shows a driver circuit of the present invention at tr = tf = 10 ps (35 GHz pulse effective frequency)._dd= 2V, transmission line voltage 0.05V (reception end is 0.1V due to total reflection). The simulation result is shown in FIG. R8, R9 (5, 6) have a receiving end matching resistance of 55Ω, and R1, R2, R3 (7, 8, 9) have a transistor on-resistance of 500Ω. U1, U3 and U2, U4 represent the switching operation of the differential transistor. The on-resistance of the simulation circuit is 0.001Ω and the off-resistance is 1 MΩ. In order to set the transistor parasitic capacitance, 10 fF of C4, C5, C6, and C7 was added. The transmission line 10 has a characteristic impedance of 50Ω that seems to be controllable within the LSI, and is a line surrounded by an insulator having a relative dielectric constant εr = 4, and a delay of 20 ps corresponding to a 3 mm line length is set. A gate capacitance of 5 fF was added for each input to the differential gate. Assuming that the characteristic impedance of the power / ground pair line is thicker than the signal line size, the impedance is set to 15Ω, and the power is supplied from a distance of 7.5 mm. The bypass capacitor scattered in the chip was set to 20 pF. Here, L1 is the parasitic inductance of the bypass capacitor, and since the capacitance is small, the counter current path is short and 1 pH. The differential signal is handled in a single-ended manner as shown in FIG. 2, but since there is no such tool in the simulation, it is expressed as a transmission line with two pairs of power supply and ground.
[0022]
The signal voltage amplitude at the receiving end is very low at 0.1 V (11), but the potential difference is sufficiently detectable by differential input / output. A constant current is passed during charging and discharging of the transmission line, but the current is reduced and the setting is conscious of low power. In this setting, 200 μA (13) is obtained, and 2 V × 200 μA = 400 μW is consumed per driver per transition. As a guideline, it is necessary to use a global wiring with a relatively large power consumption and designed to be limited to about 10% per LSI.
[0023]
Even at such a high frequency, almost constant current is maintained in the simulation, and there is almost no problem. A current indentation (spike-like change) should appear at the gate capacitance of the transistor 10 fF. The reason why they are not visible at all is that they exist in a complementary manner. This is the description of FIG. 4 described later. The change in the switching time constant τ due to the voltage dependence of the drains and sources of the two series nMOSs can be ignored because there is almost no voltage difference.
[0024]
If the transition of the next output signal occurs during the charge / discharge period (2 tpd) in the transmission line, the waveform will be disturbed. Therefore, if the wiring length is 3 mm, 2 tpd = 40 ps, and a frequency with a period less than this will be a problem. . That is, 40 ps is 25 GHz in terms of frequency, so that a circuit that can operate at a pulse frequency of 25 GHz has been proposed. Incidentally, if the wiring is suppressed to 1.5 mm, it becomes 50 GHz.
[0025]
Proposal of the present invention around the driver is as follows: (1) The differential driver is composed of one stage transistor or a parallel circuit of one stage transistor. (2) The parallel circuit of the differential driver or the adjustment circuit connected to the differential driver is configured to be optimized by a genetic algorithm (described later). (3) The power supply / ground must be a pair transmission line. (4) A bypass capacitor must be provided at the driver end in order to pass a complementary current of the ground to the power supply (generally called a return current, but it is called a complementary current for misleading terms). (5) A differential signal is handled by a single-ended transmission line structure (Fig. 2), and is not differential based on a general ground. (6) A configuration in which the matching termination is set to the same value as the characteristic impedance of the single-ended transmission line, and the midpoint is a reference ground to form a current path. (7) A structure in which the waveform analysis circuit is placed on the receiving side, and the waveform adjustment circuit is installed between the terminating resistor and the driver. (8) The differential driver is provided in the same well structure, and each channel (in the case of MOS • FET) and base (in the case of bipolar transistor: in this case, a common collector structure) is used. Configuration that considers complementary use. It is characterized by.
[0026]
(8) means that the accumulated charges of C4, C5, C6, and C7 in FIG. 3 are reused at the time of inversion, and the indent peak of the simulation result in FIG. 4 can be controlled. Within the same well structure, the characteristics of transistors of the same size are unlikely to be unbalanced, and exactly the same amount of charge can be pumped up and down.
[0027]
FIG. 5 shows an example of a transistor cross-sectional structure that realizes the function (8).
The differential driver transistor is in the same well structure. Channel charges attracted to each gate potential (in nMOS, electrons are a small number of induced conduction carriers, but holes are majority carriers in the well and cannot be said to be a channel, but a high hole density is temporarily called a channel) are complementary. When it is released by the input signal, it is a time when the adjacent transistor is attracted, and high-speed carrier exchange can be performed. In addition, it greatly contributes to power saving by reusing the electric charge.
[0028]
A bipolar transistor may have a cross-sectional structure as shown in FIG. The extraction of the base accumulated minority carriers to the collector side is emphasized by the common collector electrode, and the common collector compensates for the complementary increase and decrease of the depletion layer charge. Since the extraction of the emitter is not different from the conventional one, it is a structure that enables a large high-speed operation although it is less than the effect in the MOS, and the electric power can be reduced by reusing the charge.
[0029]
Here, the high-speed operation by the carrier pump up and pump down and the detailed structure principle of the transistor will be described.
The biggest reason why the transistor does not operate at high speed is that it takes time to supply the charge to release the accumulated charge that exists just before the transistor transition and put it in the accumulated charge distribution according to the new state. is there. Even if a bypass capacitor is supported in the chip, the power ground is passive in nature, and does not actively assist the charge supply and discharge of the transistor that undergoes active changes. An increase in the instantaneous current due to the capacitance component) causes a drop in the power supply voltage and an increase in the ground level, thereby limiting the instantaneous current. In general, since the bypass capacitor is not adjacent to the transistor, it is difficult to provide an emergency charge supply measure. This problem will be described with the pMOS transistor structure of FIG.
[0030]
When the voltage of the electrode of the pMOS transistor is a base potential when base B = drain D = source S and a negative potential is applied to the gate G with respect to the reference source potential, the n-channel (channel layer region) immediately below the gate insulator is The holes are inverted to induce a configuration as shown in FIG. The charge is opposite between the gate potential and the inversion layer potential and C_ox(In this case, the charge of the inversion layer is a hole). Since a depletion layer is generated under the inversion layer and the charge is confronted here, C_i Exists. The potential distribution of the well structure by the inversion layer causes C under the depletion layer._b Also occurs. The total capacity of these is C_mos I will call it. As the voltage rises, this state is weakened and the charges become increasingly discrete. In this situation, the horizontal axis represents the gate voltage, and the vertical axis represents C._mos Then, the relationship as shown in FIG. 28 can be drawn. When the inversion layer is eliminated and only the depletion layer is present, the amount of charge is minimized. That is, the transistor in this case can be regarded as a two-terminal variable capacitor depending on the voltage.
[0031]
When the gate potential is further increased to the plus side, accumulated charges (in this case, electrons in the layer immediately below the gate) are accumulated in the channel layer region. Naturally, the accumulated charge amount is the same as when holes were stored, the capacity increased, and C_oxReturn to. This C_oxThe value of
C_ox= Ε_oxS / t_ox
It becomes. Where ε_oxIs the dielectric constant of the gate insulator, S is the area of the channel surface, t_oxIs the insulator thickness. C in FIG._mos The lowest value of C_min Then, inversion of the gate voltage (V_swing ) Q_tran= 2V_swing (C_ox-C_min ) Charge amount must be injected from the power source. In order to invert the charge, a factor of 2 is attached. This is energy for operating the transistor itself, which is not related to the transistor output charge.
[0032]
Now, signal voltage 0.5V, C_mos = 5 fF, C_min = 2.5 fF and the transition time (rise or fall time) of the signal input to the gate is 25 ps, the charge amount Q accompanying the transition_tran= 1.25 fC and transition current i_tran= 50 μA flows for 25 ps, which is extra for driving the transistor. This energy must be absorbed and released instantaneously at each signal transition, and in a circuit in which many transistors are gathered, the transistor capability cannot be exhibited if the power supply ground state is slightly bad.
[0033]
As described above, the voltage of the power supply ground is static, and if a current of 50 μA is applied instantaneously, the power supply voltage drops or the ground level rises due to the parasitic inductance of the line. A circuit for forcibly pumping up and down the charge necessary for the operation of the transistor is necessary to support the high-speed switch of the transistor. Many CMOS logic circuits and memory circuits have differential output terminals. Here, it is assumed that all input signals are differentially received. The basic circuit will be described with the configuration of an nMOS transistor and a varactor as shown in FIG. The two nMOS transistors and the varactor have exactly the same size structure and are driven complementarily.
[0034]
When a varactor having the same dimensions as a CMOS transistor (a two-terminal circuit element in which the source electrode and drain electrode of FET are connected) is designed based on the PMOS transistor of FIG. 27, it is complementary with a structure similar to that of the CMOS transistor as shown in FIG. A varactor with characteristics is obtained. As will be understood from this, when the MOS transistor requires a charge with a complementary differential signal, the varactor capacity decreases as shown in FIGS. 31 and 32 due to the change in voltage applied to the gate, and the charge corresponding to the capacity decrease. That is, electrons or holes required by the MOS transistor are emitted. This flows from the source or drain electrode, and instantaneously satisfies the accumulated charge necessary for the transition of the MOS transistor. When a MOS transistor has to discharge electric charge, it is a time when the same varactor needs electric charge, and it will absorb this positively. It ’s done.
[0035]
In a varactor, transistor, or CMOS / FET switch type driver, high-speed exchange of + and-charges is performed in a common well of complementary elements, so that the common well is electrically floated (not connected to GND or power supply). It is desirable. However, in some cases, there is a case where the common well is connected to the GND or the power source at the sacrifice of the operation speed in order to reduce noise.
[0036]
FIG. 7 shows an example of the receiver end circuit. Since n1 and n2 (21 and 22) of the differential receiver transistors are inverted signal inputs, high-speed operation is possible with a common well structure or a common collector structure (when bipolar is used), as in FIGS. It is. Since n3, n4, and p3 are static transistors, a conventional circuit is sufficient. The varactor may be set as shown in FIG. 6 using the inversion operation of n1 and n2, as in FIG. 5, and this enables high-speed operation and power saving operation. It is sufficient that p1 and the left varactor and p2 and the right varactor are in the same well structure.
[0037]
The wiring structure is shown in FIG. The important design point is that the input signal is a pair transmission line, the output line is a transmission line, and the power supply ground pair is also a transmission line (upper layer) (both are a pair coplanar line). Another important point is that they are in the same well structure.
[0038]
The power ground layer is formed as a pair coplanar line along each transistor array in the third layer as indicated by a two-dot chain line. FIG. 9 shows the cross-sectional structure for easy understanding.
[0039]
First, attention is paid to the cross section of the coplanar line (30) of the upper power supply ground. In order to strengthen the power supply / ground coupling, it is desirable that the aspect ratio t / w ≧ 1.5. This is because the coupling with the power supply ground is strengthened by increasing the opposing surface, and the leakage of the electromagnetic field to the outside is reduced. Next, in order to strengthen the coupling in the upper power supply ground pair layer, the fringe of the opposing electromagnetic field should not cross over the layers as much as possible, that is, in order to avoid crosstalk, the condition of d <h is satisfied. It is necessary to satisfy. Thirdly, s / d ≧ 1.5 is necessary to avoid the influence of fringe. The same thing should be realized with all pair coplanar lines (signal lines, clock lines). In addition to the driver and receiver structures, it is desirable to use this structure for all LSI logic and memory transistor connections operating at a clock frequency of several GHz or higher. Of course, it goes without saying that this wiring rule is preferably applied to all the global wirings of the chip.
[0040]
As shown in the example in Fig. 2, the output of the driver is in the process of passing through the main line bus to the transmission line, and the pair line is not connected to the common ground anywhere, and exists as an independent line through the resistor. To do. The effect of this is that the pair signal lines swing complementarily and the maximum amplitude effective for the differential amplifier receiver can be obtained. A further effect is that the disturbance of the electromagnetic field in the transmission line is minimized, the waveform is not disturbed, and the circuit is configured to minimize the parasitic inductance and the parasitic capacitance.
[0041]
The important point here is that the signal line ground is paired with the signal line and cannot be said to be a ground, so it is not connected to the common. In order to match the level with other signals (so that there is no bias difference), it is dropped to the ground in one place, but this is also unnecessary in a strict sense. The reason for limiting to one place is to prevent a complementary current existing in the ground from branching through another ground loop. If this is called loop current or eddy current, this current causes EMI generation, and the present invention is characterized by preventing this phenomenon.
[0042]
For example, in the case of a microstrip line, the microstrip line has a structure in which the strip line is wired via a dielectric with respect to the common ground, and the electromagnetic field distribution between the strip line and the common ground passes through the common ground. It also couples with the strip line and interferes with other strip lines. However, since the signal line ground of the present invention is a pair of signal lines and is separated from the common ground, it is basically impossible to interfere with other signal paths via the common ground as described above. Absent. This is the effect of providing a signal line ground separated from the common ground. In the present invention, the center of the spread of the electric field is the cross-sectional center of the pair transmission line (signal line and signal line ground line).
[0043]
FIG. 39 shows a simulation result using one FET basic switch circuit shown in FIG. 38 in which only the transmission terminal end is dropped to the ground. In FIG. 39, the waveform 103 at the transmitting end 101 in FIG. 38 is the receiving end 102 in FIG. 38, and the waveform 104 is divided by the terminal resistance and the FET on resistance, and the output amplitude is reduced. However, it can be seen that the 1 GHz pulse passes. However, what to do with the ground of the transmission line (T2) remains as an examination subject.
[0044]
Next, S-parameter measurement of 230 mm line length (line / space = 1/1, characteristic impedance about 50Ω) microstrip line MSL and stacked pair line SPL was performed, and both circuits were dropped to ground on the input side at 1 GHz. FIG. 40 and FIG. 41 show simulation analysis results when the output side is floated with a resistance of 10 MegΩ. In FIG. 40, the actually measured S parameter is input to the circuit component 105 of 2 Port, and the materials are FR-4, BT resin, and Teflon (registered trademark).
[0045]
41 shows that the transmission waveform 106 becomes reception waveforms 107, 108, and 109. FIG. From this, even if the transmission line T2 is floating, the simulation of the above line shows that the waveform of 1 GHz passes through both the microstrip line MSL and the stacked pair line SPL, and any one of the input and output points It turns out that you can drop the ground.
[0046]
The structure of the transmission line used in the circuit is shown in FIG. Although two pairs are described, it is a rule of the pair coplanar and the stacked pair that the distance from the adjacent pair line has a space (2S) more than twice the space of the pair line itself. For the guard coplanar line and the guard stacked pair line, the adjacent wiring space can be designed with a space (S) of 1 or more times based on the space of the pair line itself. The advantage of the guarded line is that the characteristic impedance of the transmission line can be lowered and the design range can be made appropriate.
[0047]
In order to observe the TEM wave transmission conditions, the transmission line must be surrounded by a homogeneous insulating material. In the pair coplanar and stacked pair, the range is 2s (Fig. 10), which is equivalent to the effective electromagnetic field from the outer periphery of the conductor. In the guard coplanar and guard stacked pair, the effective electromagnetic field stays in the guard. , S.
[0048]
FIG. 11 proposes a countermeasure when the spread of the insulating layer cannot be protected. An example of a stacked pair line is shown. This image is a printed wiring board, which is the uppermost solder resist part. Since the solder resist is thin, the electric lines of force extending upward reach the air layer (relative dielectric constant 1), so the effective relative dielectric constant of the solder resist is small. When the relative dielectric constant of the lower insulator is a (a> 1), a configuration using a solder resist having a large dielectric constant so that the effective relative dielectric constant of the solder resist is the same a is a feature of the present invention. . Thereby, the transmission line can substantially maintain the TEM wave mode. In the case of a pair coplanar or stacked pair line, when there are different types of insulating layers or air layers in the range of 2 s, the layer is adjusted so that the substantial relative permittivity becomes the same relative permittivity within the spread range. Structure is also a feature of the invention. The guard coplanar and guard stacked pair lines are also configured so that similar regulations are observed within the range of s. Specific dimensions are shown on the printed wiring board as a model for stacked pair lines. If the solder resist thickness of (1/2) s is defined since the effective electromagnetic field is closed at 2 s, (3/2) s (ie, 2S-1 / 2S) Become. Since the relative permittivity of air is 1, assuming that the relative permittivity of the solder resist is b, the simple calculation formula is 1 × (3/2) + b × (1/2) = a. It becomes weaker in proportion to the square of the distance from the center, and b = 2a is measured in actual measurement.
[0049]
Next, as shown in FIG. 12A, consideration is given to the length of impedance mismatching such as columns and via holes.
When the relative dielectric constant of the insulating layer in the chip is 3, the electromagnetic wave transmission speed is 1.73 × 10.⁸ [M / s], and the transmission delay of the 100 μm line length is 0.578 ps. Since this assumes that the main line pulse rise time is 10 ps, it can be interpreted that the following phenomenon occurs. Even if energy flows in the mismatched portion, the return is 0.578 × 2 = 1.156 ps, which is a time in which reciprocation is possible 8.5 times in 10 ps. By this reciprocal adjustment, the stable region is reached during the rise time (FIG. 12B). Therefore, although there is a disturbance in the waveform during the rise, after the rise, the stable waveform passes through the mismatched portion and then proceeds through the wiring. As shown in FIG. 13, in terms of energy, 90% of the energy that has passed the time required for three round trips passes through even a mismatch of 50Ω / 200Ω. In conclusion, this length is negligible. That is, if the delay time tpd of the mismatched portion is 7 tpd <tr, the influence of mismatch is negligible, so a configuration of tr> 7 tpd is proposed.
[0050]
Here, a varactor element insertion circuit is proposed as a configuration of the bus switch type driver. An example of this is shown in FIG. Here, the varactor has the same configuration as the MOS transistor, MES transistor, or bipolar transistor. This is because the same LSI fabrication process is used for simultaneous fabrication.
[0051]
It should be added that a differential output circuit (similar to FIG. 2) using a reference power supply may be used for the buffer in the front stage of the driver.
・ System structure
In the above, the device and circuit part of the driver receiver transmission system were demonstrated. The following describes the structural parts that make up the system for this purpose. First, an ideal form is shown, which is a structure in which isometric parallel wirings are connected at the pitch. This is shown in FIG. A terminal resistor (51) that absorbs the return signal of total reflection at the sending end, and a circuit that detects the return voltage waveform is attached. The waveform is analyzed and fed back to the genetic algorithm circuit (52) to correct the transmitted waveform. It becomes composition to do.
[0052]
A preferred transmission line structure in the chip is a coplanar line. However, since a vertically long cross-sectional structure having a large aspect ratio cannot be obtained by a package or a printed wiring board, a stacked pair line is preferable here. The plan view of FIG. 15A is a perspective view of the chip. The driver (53) leads to the chip pad (54) through the coplanar line, and is connected to the wiring board by flip chip connection. The signal line and the ground line that run below the pad layer are connected to each lower layer by flip-pad pad via holes and overlap with each other as short as possible to form a cross-sectional structure (FIG. 15B). The ground layer is desirably 1.2 to 1.5 times larger than the line width w in order to prevent the vertical displacement of the stack and leakage of the electromagnetic field to the lower layer. Other relations are shown: w ≦ s, (d + t) ≦ s / 2, d ≦ h₁ , D ≦ 2h₂ Must. A receiver pad (55) is provided at an equal position from the driver and is connected to the receiver. It is desirable that this short wiring is a stacked pair line if it is in a package, and a coplanar line if it is in a chip. In FIG. 15A, the second and third receivers are overlapped so that they are indicated by dotted lines. Of course, there are a number of branch pads and receivers omitted. A termination resistor (57) matching the line characteristic impedance is connected to the end of the line. As can be seen from the cross-sectional structure, an orthogonal line such as a power supply ground is set under the stacked pair line.
[0053]
As clearly shown in FIG. 15, the receiver chip (56) straddles the bus wiring at the branch portion. Thus, the transmission line length can be made as short as possible. With such a configuration, the following requirements as shown in FIG. 16 emerge from the pad arrangement of the driver chip and the receiver chip.
[0054]
(1) Stacked pair wiring is arranged at a pitch twice as large as the pad pitch, and the pads must be aligned in a straight line perpendicular to the bus line direction.
(2) The structure is such that the signal line is taken out from one row pad of the chip, and the constraint condition when coupled to another side becomes large.
[0055]
These two constraints pose significant problems for designers. When the chip area shrinks due to improvement, the pad pitch must also be shrunk. Similarly, when the wiring pitch is shrunk due to technical improvement of the printed wiring board, the chip pad pitch must be shrunk. The improvement timing of the driver chip and the memory chip is different, and it becomes difficult to find the matching condition. The shrinking pad pitch requires the improvement of the joining technique that most affects the reliability, and is difficult.
[0056]
For this reason, the use of an LSI package as an interposer can solve the problem temporarily, but an extension of the branch wiring length and a fan-out type wiring structure (60) as shown in FIG. 17 are required. Although the extension of the wiring can be devised to be within the restricted range, the fan-out structure breaks down the principle of equal-length wiring, causing problems with synchronous incoming calls. If the fanout wiring is designed to have a wider wiring width, there is a problem that the characteristic impedance changes. The present invention also proposes these problem-solving structures.
[0057]
In FIG. 17, it is not expressed as a stacked pair line for convenience, but it is assumed that the fan-out structure in the package and the wiring on the printed wiring board are also stacked pair lines. The line size of the printed wiring board can be made thicker than the fan-out line, and the size can be set freely by adjusting the fan-out spread angle. That is, since it can be designed independently of the chip pad pitch, the use of a package has become the mainstream of existing technology. In a high-speed signal system, it is required that the characteristic impedance is the same across all lines, and that the wirings are of equal length.
[0058]
Consider a characteristic impedance of 28Ω as a reference. Now, assuming that w = 200 μm and εr = 4.5, a characteristic impedance approximate expression of a stacked pair line (Harold A. Wheeler) (see symbol in FIG. 15)
[0059]
[Expression 1]

[0060]
From this, d = 39 μm is obtained. Although there are branch pads here, the bus structure is the same up to the termination, and there is no need to worry about mismatching in characteristic impedance. Assuming parallel isometric wiring, the pad pitch is w / 2 = 100 μm, which can be designed with current technology. If the thickness of h2 is 60 μm, which is the standard for printed wiring board prepreg, an ideal layer structure is obtained.
[0061]
On the other hand, the package wiring needs to be designed according to the chip pad pitch. Here, when the chip pad pitch is 50 μm, the w of the stacked pair wiring on the package is 100 μm. From the above formula, d = 19.5 μm. This makes the 28Ω transmission line design from the chip pad to the termination resistor. However, since the wiring length of the fan-out portion is different, the device is devised as shown in FIG.
[0062]
As a well-known example of equal-length wiring with respect to fan-out wiring, zigzag meandering meander wiring is often used. However, since the electromagnetic field is complicated due to the adjacent effect, the arc has an equal length as shown in FIG. Lay out as there is. Since there is no bent reflection like meander, not only smooth transmission is expected, but also the distance between adjacent wirings can be made relatively wide, which is advantageous for crosstalk.
[0063]
When a calculation formula for designing with a geometric arc is constructed, it is as follows according to FIG. Here, A and B are pads. String AB = 1₁ Is the linear distance between the outermost pads. Using this as a variable, radius OP = r that makes arc AB constant between adjacent pads₁ Deriving a relational expression to find ∠ACO is right angle, ∠AOB = θ₁ And Now, line segment PC = r₁ -H₁ , CO = h₁ Then, (1₁ / 2)² = R₁ ² -H₁ ² Is obtained, and θ₁ / 2 = tan^-1(1₁ / 2h₁ ), Arc AB = r₁ θ₁ [Radians]. From these equations, h₁ If we decide appropriately, r₁ Is obtained. Arc AB = r₁ θ₁ Is constant and the following pad distance is 1_x One after the other_x And r_x Can be requested. l_x And radius r between each pad_x Is
[0064]
[Expression 2]

[0065]
Of course, the arc AB may be an ellipse or an arbitrary high-order curve, and it is a feature of the present invention that there is no sharp bend.
Now, a structural proposal using a package has been presented. Recently, a design method in which a package is omitted, a chip is directly connected to a printed wiring board, a fan-out wiring, and a parallel bus wiring is often used. Changing the distance d between the pair lines according to the line width w is difficult to make on the same substrate. Even if it is made, the cost is high, and the connection reliability of the stepped portion is lowered. The next proposal relates to a structure in which w is changed while d between the pair lines is constant. This is shown in FIG. It is proposed that the fan-out structure is a microstrip line or a strip line, and the parallel bus line is properly used as a stacked pair line.
[0066]
Microstrip lines and strip lines have a capacitance C per unit length because the electric field spreads to the ground plane.₀Will increase. as a result
[0067]
[Equation 3]

[0068]
Becomes smaller if the line width is the same. Conversely, Z₀ If w is constant, w can be reduced. The approximate expression of the microstrip line (Harold A. Wheeler) (see symbol in Fig. 15) is
[0069]
[Expression 4]

[0070]
It becomes. Z₀ = 28Ω, d = 39 μm and w = 170 μm are calculated. In order to correct the influence of the conductor thickness (t = 25 μm), the conductor thickness t (25 μm) may be subtracted empirically, and the corrected line width w = 145 μm is obtained. When the stacked pair line w = 200 μm, the space between the pair lines is the same, d = 39 μm, and if the microstrip line is used, the line width w = 145 μm can be miniaturized.
[0071]
The line width w = 145 μm is insufficient for the design in which the spacing between the chip pads is 50 μm and the line width of the fan-out wiring is w = 100 μm, but it can be dealt with by narrowing down in the vicinity of the pads. The wiring length to narrow down may be the same idea as the branch wiring length, and (6 x total delay time of narrowing length) <(rise time), as with the correspondence to the impedance mismatch length of columns, via holes, etc. Good.
[0072]
When the memory chip transmits a signal, the method shown in FIG. 21 is used. A signal transmitted from the memory driver flows on both sides (72, 73) of the bus line. Since the characteristic impedance is the same, the signal voltage is ½ from the law of energy conservation. The signal flowing in the right direction is a waste signal, and the receiver arranged at the end must be made insensitive. Further, if the signal is totally reflected here and returns to the left controller chip, it will be sensitive to an unnecessary signal. This must also be prevented. When the memory is strobed and a signal is transmitted, the rightmost receiver receives the signal and becomes inactive, and the termination resistor (70) becomes active and the useless signal disappears here.
[0073]
On the other hand, the 1/2 regular signal that has reached the controller chip (74) drives the receiver circuit (including the genetic algorithm circuit) of the controller, and is absorbed by the terminating resistor (75) attached thereto and disappears. However, since the waveform is corrected by 1/2 from the already stored total reflection signal deformation, it is taken into the sense amplifier, so that the correct waveform is recognized at the correct timing.
[0074]
Since both the driver and the receiver are always high impedance when viewed from the outside, it is not problematic to provide a transmission / reception circuit with a 1-bit bus.
・ Genetic algorithm circuit
1 illustrates one embodiment of a circuit tuned by a genetic algorithm circuit.
[0075]
The circuit shown above defines L that defines the characteristics of the transmission line.₀ , C₀ The existence of independent L and C other than is eliminated as much as possible, and the frequency characteristics are eliminated. In other words, the characteristic impedance Z0 is
[0076]
[Equation 5]

[0077]
Thus, the imaginary part (imaginary part) and each frequency are eliminated, in other words, a transmission line having a pure resistance component in impedance is formed.
However, no matter how completely designed, there are independent minute mutual inductances (M) and capacitances (C) that are parasitic due to variations in manufacturing conditions. This is expressed as shown in FIG. The transmission line seen in FIG. 10 is a transmission line in which the electromagnetic field is almost closed, and has characteristics close to that of a coaxial cable according to the above equation. Therefore, in FIG. 24, a transmission line expression is taken. The concept is that weak MC coupling exists between the transmission lines. In addition to the line-to-line connection, MC coupling is also conceivable in the case, via holes, connectors, etc., and the problems caused by these weak MC couplings can be ignored at low frequencies. However, pulses of 10 GHz or more are greatly affected by slight parasitic M and C in the entire circuit. Expressing it with admittance Y,
Y = j (ωC-1 / ωM)
Thus, not only does it change greatly with an increase in ω, but also it resonates under the condition of ωC−1 / ωM = 0. It is essential to insert a circuit that eliminates such inevitable practical problems. The present invention proposes that an LC net that cancels the parasitics M and C is automatically created by a genetic algorithm and superimposed on the driver signal. Its configuration is
(1) In order to ensure a high-speed signal, the waveform shaping is a pure LCR net, and which part is operated by a charge pump-up / pump-down transistor.
[0078]
(2) A test signal is transmitted and a total reflection signal is captured by a terminating resistor. The voltage is detected and a waveform analysis is performed. The analysis step is an LCR net which is a complementary inverse transform of waveform shaping.
[0079]
(3) It is assumed that the genetic algorithm circuit subjected to the test signal correction is stored until a system change occurs.
This algorithm is illustrated in FIG.
[0080]
The circuit connection in the LCR network can be freely changed by the control transistor, and the reception waveform is detected so that the original digital signal waveform can be received at the reception end, and the transmission waveform is adjusted to a complementary waveform. This adjustment is performed by a genetic algorithm. An example of the waveform is shown in FIG. The genetic algorithm is one of the probabilistic search methods. (1) It works effectively in a wide area search. (2) Derivative information such as differential values is not required other than the evaluation function value. It is an algorithm with easy implementation. Therefore, in the present invention, it is preferable to use a genetic algorithm for searching for adjustment parameters. This adjustment method may be another stochastic search method, not limited to a genetic algorithm, and may be any of a hill-climbing method, an annealing method, an enumeration method, an evolutionary strategy, a tabu search method, or a combination thereof.
[0081]
Note that Japanese Patent Application No. 11-240034 “Electronic Circuit and Adjustment Method” (Japanese Patent Laid-Open No. 2000-156627) applies mutatis mutandis to the basic circuit and adjustment method of the genetic algorithm. As long as the circuit is fixed, the modification is limited to one time, and the computer that executes the genetic algorithm at the system shipping stage may be external and need not be included in the system.
[0082]
An example of the LC circuit of the genetic algorithm is shown in FIG. The genetic algorithm output LC net 81 in FIG. 26 is schematically represented, and specific circuits thereof are shown in FIGS.
[0083]
A waveform adjustment method using a genetic algorithm will be described with reference to FIG.
・ Common concept
Adjust the waveform on the transmitting side (waveform shaping) so that the receiving side has a clean waveform to improve the quality of signal transmission. It is a kind of so-called equalization.
[0084]
The waveform evaluation circuit 91 is a circuit that evaluates the quality of the waveform and outputs a voltage. The value of this result is used as the evaluation function value of the genetic algorithm, and the waveform shaping state is optimally controlled by the genetic algorithm (GA). Specifically, in FIG. 33, the driver outputs transmission data to a differential pair of transmission lines and has a waveform adjustment function. The receiver obtains received data from a signal input from the transmission line. The waveform evaluation circuit 91 is a circuit having a function of quantitatively evaluating the degree of distortion of the signal waveform received by the receiver, and outputs a voltage value corresponding to the evaluation result of the received waveform. The external device 92 executes a genetic algorithm, which is a probabilistic search method, and outputs a waveform adjustment value to the driver. The transmission waveform of the driver output is adjusted by a control signal from the external device 92. Here, the voltage value output from the waveform evaluation circuit 91 is an evaluation function value in the genetic algorithm, and this voltage value is input to the external device 92 so that the evaluation value of the received signal waveform is the best. Thus, the adjustment value of the waveform is searched. As a result, waveform optimization is performed.
[0085]
There are two waveform shaping methods: adjustment based on the frequency axis and adjustment based on the time axis.
・ Adjustment by frequency axis (Fig. 34)
As an example of adjustment using the frequency axis, a configuration using an equalization filter shown in FIG. 34 will be described. The equalization filter circuit of FIG. 34 is implemented in the driver of FIG. The equalization filter circuit minimizes the distortion of the received waveform by compensating the amplitude on the frequency axis and the phase on the frequency axis for the distortion of the signal waveform generated in the transmission line. Waveform shaping is performed by an equalization filter circuit in which at least two types of circuits, ie, a circuit diagram 34 (a) that mainly adjusts amplitude and a circuit diagram 34 (b) that mainly adjusts phase, are cascade-connected.
[0086]
In this circuit, the resistance value of the resistor R and the capacitance value of the capacitor C in the figure are adjusted by a genetic algorithm so that the distortion of the received waveform is minimized. Adjustment with only the resistor R and the capacitor C makes it difficult to satisfy the constant resistance condition of the equalization filter (optimum condition with no reflected signal). In general, it is very difficult to analyze characteristics under this condition. The GA searches for the transmission waveform with the best waveform (minimum distortion).
(In the text below, when “￣” (overline) is added, “ "(Underlined). )
・ Adjustment by time axis (Figs. 35-37)
An example of the adjustment based on the time axis will be described with reference to FIGS. The circuit described here is mounted on the driver shown in FIG. First, FIG. 35 shows an operation principle of a circuit for adjusting a transmission waveform on a time axis. This circuit includes a switching circuit 93 (switch array S1 to Sn, and corresponding output signals P1 to Pn andP1~PnWhere Pn andPnIs a complementary signal), a delay circuit 94 that delays differential input data by a predetermined timing, an analog DC variable constant current source 95 (each current value is C1 to Cn), and a high-speed switch 96 (data from the switching circuit 93). Output signals P1 to Pn,P1~PnIn response, the switch is complementarily turned ON and OFF).
[0087]
A set of data inputs that are transmitted data (this complementary signal isData entry), And first, through the switch S1 of the switching circuit 93, P1,P1Changes to P1,P1The high-speed switch 96 corresponding to is operated. As a result, the output current of the variable constant current source 95 corresponding to C1 (the current set value is C1) is switched, and the output current Iout,IoutGet one element.
[0088]
Similarly, a set of data input digital signals are set with a plurality of predetermined delay timings via the delay circuits 94, and a series of signals P2 to Pn,P2~PnIs generated. These are complementary signals P2 to Pn for operating the high speed switch 96 one after another,P2~PnEach current C2 to Cn of each variable constant current source 95 is energized.
[0089]
Since each high-speed switch is connected in parallel for the non-inverted signal and the inverted signal on the output side, the combined complementary currents Iout,IoutGet. In each part of the high-speed switch 96, a current waveform having a plurality of predetermined timings is superimposed from input data, and waveform shaping is performed.
[0090]
The current Iout synthesized above,IoutThe data output andData outputIs output as This output signal is the output signal of the driver in FIG. When a waveform that compensates for waveform distortion on the transmission line is output, the distortion of the input waveform at the receiver is minimized.
[0091]
The settings of the current values C1 to Cn of the variable constant current source 95 and the switches S1 to Sn of the switching circuit 93 are optimized by the genetic algorithm executed by the external device 92 using the output voltage value of the waveform evaluation circuit 91 in FIG. Is done. As a result, the transmission waveform is automatically adjusted to minimize the distortion of the reception signal at the receiver.
[0092]
Five sets of high-speed switches 96 (P1,P1, P2,P2, P3P3, P4P4, P5P5) Shows the waveform of the current flowing through each switch (the peak value is equivalent to C1 to C5). Each high speed switch 96 (P1,P1~ P5P5The combined current flowing through Iout andIoutIt is. Since the current flowing through each high speed switch 96 is differential, Iout,IoutIs also a differential current. FIG. 37 shows the principle configuration shown in FIG. 35 as an implementation example. Each operation element block is shown as the same number 93, 94, 95, 96. The transistor used as the switching element is represented by an FET, but it can also be a bipolar transistor.
[0093]
42 and 43 show a comparative example when such waveform shaping is not performed and when waveform shaping is performed on the time axis as described above. In the case of FIG. 42 in which waveform shaping is not performed, the reception waveform after passing through the transmission line when the ideal rectangular wave 110 in FIG. 42A is transmitted as the transmission waveform (driver output voltage) is simulated on the computer. Then, a received waveform such as 111 in FIG. 42B is obtained. This is because high frequency components are attenuated in the transmission line, so that “1” and “0” of the digital signal are ambiguous.
[0094]
On the other hand, a transmission waveform 112 and a reception waveform 113 when waveform shaping is performed on the time axis by a genetic algorithm are shown in FIGS. 43 (a) and 43 (b). In this case, since the transmission waveform 112 is adjusted so that “1” and “0” of the digital signal of the reception waveform 113 that has passed through the transmission line are close to ideal waveforms, the reception waveform 113 becomes “1” of the digital signal. A voltage ground corresponding to “0” is obtained, and a waveform close to the ideal state with little voltage deviation is obtained.
[0095]
As another embodiment, as a new configuration method of the configuration of the line, the change in the characteristic impedance of the line with respect to the positional deviation of the line can be reduced by changing the upper and lower line widths in the stacked pair line (FIG. 10). At this time, the common mode impedance can be made the same by changing the thicknesses of the upper and lower insulating layers of the pair line, so such a device may be added to the present invention.
[0096]
【The invention's effect】
As described above, according to the high-speed signal transmission system of the present invention based on various devices, an I / O bus having the same transmission clock as the chip clock can be realized corresponding to an LSI chip having a high-speed clock frequency of 2 GHz or more. .
[0097]
This has a remarkable effect that the I / O bus that can only be realized at 533 MHz can be remarkably increased in speed.
The basic idea is to make a clever match with the transmission band of a high-speed pulse reaching 20 GHz, and to make a stunning absorption or cancellation of stray capacitance and parasitic inductance.
[0098]
These ideas have “novelty” and also have the effect that the use of genetic algorithms cannot be overlooked.
In this way, an I / O bandwidth that is consistent with the LSI clock can be secured, the speed of the LSI chip can be increased, and the speed of the entire data processing system including data transfer with the memory can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a general wiring length distribution in LSI design.
FIG. 2 is a diagram showing an example of a structure for connecting a driver and a receiver of the present invention.
FIG. 3 is a diagram showing a simulation model circuit corresponding to a pulse effective frequency of 35 GHz according to the present invention.
4 is a diagram showing the simulation result of FIG. 3. FIG.
5 is a diagram showing an example of a cross-sectional structure of an nMOS driver in FIG. 2 of the present invention.
FIG. 6 is a diagram showing a bipolar transistor carrier reuse circuit of the present invention.
FIG. 7 is a diagram illustrating an example of a receiver-end circuit according to the present invention.
FIG. 8 is a diagram illustrating an example of a planar structure of a driver.
FIG. 9 is a diagram illustrating an example of a cross-sectional structure of a driver transistor portion.
FIG. 10 is a diagram showing a transmission line suitable for the transmission system of the present invention.
FIG. 11 is a diagram showing an example of effective relative permittivity matching of an insulating layer around a conductor in a heterogeneous insulating layer.
FIG. 12 is a diagram showing a model of impedance mismatch length such as columns and via holes.
FIG. 13 is a diagram showing a mismatch impedance based on 50Ω and a pass rate of multi-order reflected energy.
FIG. 14 is a diagram illustrating an example of a bus switch type driver.
FIG. 15 is a diagram showing an inter-chip transmission line connection structure.
FIG. 16 is a diagram showing restrictions on chip pad arrangement;
FIG. 17 is a diagram showing a fan-out wiring structure when a package is used.
FIG. 18 is a diagram illustrating an example of an equal-length fan-out wiring.
FIG. 19 is a model diagram for making the arc AB constant and making the chord AB a variable.
FIG. 20 is a diagram illustrating an example of a line structure in which the line width is changed while the distance between the pair lines is constant.
FIG. 21 is a diagram illustrating a transmission circuit from the memory side;
FIG. 22 is a diagram illustrating a signal correction circuit algorithm.
FIG. 23 is a diagram illustrating an example of a waveform processing step for explaining an algorithm;
FIG. 24 is a diagram showing another example of a structure (not including a genetic algorithm circuit) for connecting a driver and a receiver of the present invention.
FIG. 25 is a conceptual diagram showing a parasitic coupling element between lines.
FIG. 26 is a diagram illustrating an example of a circuit model of a genetic algorithm.
FIG. 27 is an explanatory diagram of the structure and capacitance component of a pMOS transistor.
FIG. 28 is a diagram showing a relationship between a gate voltage and a pMOS varactor capacitance.
FIG. 29 is a diagram showing an example of a basic circuit having an nMOS transistor and a varactor.
FIG. 30 is a diagram showing a structure of a CMOS varactor.
FIG. 31 is a diagram showing a relationship between a pMOS and a gate voltage.
FIG. 32 is a diagram illustrating a relationship between an nMOS and a gate voltage.
FIG. 33 is an explanatory diagram of a method for adjusting high-speed data transmission by equalization.
FIG. 34 is a diagram showing a circuit for adjusting the waveform on the frequency axis in FIG. 33;
FIG. 35 is a diagram illustrating the principle of a circuit for adjusting a waveform on the time axis in FIG. 33;
FIG. 36 is a diagram illustrating a current waveform and an output current waveform of each switch when the waveform is adjusted on the time axis in FIG.
FIG. 37 is a diagram showing a mounting example of a circuit for adjusting the waveform on the time axis in FIG.
FIG. 38 is a diagram showing an example of a basic switch circuit of one FET in which only the transmission end is dropped to the ground.
39 is a waveform diagram of the circuit of FIG. 38. FIG.
FIG. 40 is a diagram illustrating an example of a transient analysis circuit of an actual measurement board.
41 is a waveform diagram of the circuit of FIG. 40. FIG.
FIG. 42 is a diagram showing a transmission waveform and a reception waveform when waveform shaping is not performed.
43 is a diagram showing a transmission waveform and a reception waveform when the waveform shaping of FIG. 33 is performed.
[Explanation of symbols]
1 Driver
2 receivers
3 Sending end
4 Receiver end
5,6 Receiving end matching resistance
7, 8, 9 Transistor on resistance
10 Transmission line
21, 22 transistor
51 Terminating resistor
52 Genetic Algorithm Circuit
53 drivers
55 Receiver chip
91 Waveform evaluation circuit
92 External device
93 switching circuit
94 Delay circuit
95 Variable constant current source
96 High speed switch

Claims (9)

It is connected to a high-speed LSI chip with a clock frequency of GHz band, and the logic of the transistor throughout the electronic circuit such as the transmission end and termination, the memory circuit, etc. are configured with differential input and differential output, and there is no branch wiring. It has an off-chip line for exchanging signals with the LSI chip, and has a connection to a power source or a ground for confirming a reference potential on one of the transmission end side or the termination side of the off-chip line. In a high-speed signal transmission system that does not have a connection to the power supply or ground at the termination or transmission end opposite the confirmed transmission end or termination side ,
The transmission line differentially output via the circuit adjusted by the probabilistic search method is matched with the characteristic impedance from all transmitting ends to the terminating end, and the sense amplifier that captures the signal receives the combined transmission waveform and total reflection waveform A high-speed signal transmission system is characterized in that a terminating resistor is inserted on the transmitting end side so that the total reflection waveform is not reflected again from the transmitting end and transmitted.   The power supply line of the system has a structure of a power / ground pair line, and is connected by one dedicated pair line per one element circuit of each minimum logic element and memory element circuit. Item 4. The high-speed signal transmission system according to Item 1. The high-speed signal transmission system according to claim 1 or 2, wherein the connection line (signal transmission line, power supply / ground pair line) is configured to maintain a TEM mode. In the structure in which the electromagnetic wave leaks into the air, the line is a structure coated with a high dielectric constant material so that the effective dielectric constant of the portion matches the internal dielectric constant. The high-speed signal transmission system according to any one of claims 1 to 3 . The high-speed signal transmission system according to any one of claims 1 to 4, wherein the transmission line is any one of a pair coplanar, a stacked pair, a guard stacked pair, and a guard coplanar structure. When the circuit is composed of a plurality of bits, the physical structure is relatively the same over all lines, and the length of the wiring is the same length. The high-speed signal transmission system according to any one of claims 1 to 5, wherein an arc-shaped wiring is used. The driver circuit and receiver circuit consisted of Si or SiGe MOS / FET, or GaAs n-channel MES / FET without differential ground connection and differential input circuit, Schottky high-speed bipolar differential circuit or bus switch circuit. 7. The high-speed signal transmission system according to claim 1, wherein the high-speed signal transmission system is any one of the above. The high-speed signal transmission according to any one of claims 1 to 7, wherein all transistors are complementarily arranged with varactors having the same MOS-FET, MES-FET, and bipolar transistor structure. system. 9. The high-speed signal transmission system according to claim 8, wherein the common well of the complementary operating elements is electrically floated.

Images