JP3738334B2 - Electronic equipment with power generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic device with a power generator such as an electronic wristwatch with a solar cell.
[0002]
[Prior art]
For example, an electronic wristwatch with a solar battery stores a voltage generated by the solar battery in a secondary battery for charging, and operates using the charged secondary battery as a power source.
In such an electronic wristwatch that uses a power generation voltage of a solar battery to charge the secondary battery as an operating power source, the secondary battery is not charged due to no light entering the solar battery for a long time, and the power supply voltage is lowered. As a result, the clock voltage stops below the operating voltage of the clock circuit composed of an LSI or the like.
[0003]
[Problems to be solved by the invention]
Then, after the operation of the timepiece circuit is temporarily stopped due to the decrease in the charging voltage due to the power generation stop, the light enters the solar cell again to charge the secondary battery, and when the power supply voltage rises, Although the circuit operation is resumed when the operating voltage is exceeded, there is a problem in that the timepiece circuit is not initialized and does not operate normally.
[0004]
The present invention has been made in view of the above-described problems. For example, when the charging voltage is reduced due to power generation and the circuit operation is temporarily stopped, when the charging voltage is restored, normal circuit operation can be obtained. It is an object of the present invention to provide an electronic device with a power generator that can be used.
[0005]
[Means for Solving the Problems]
That is, in the electronic device with a power generation device according to claim 1 of the present invention, a power supply circuit having a power generation means and a storage means charged with an output voltage of the power generation means, and an oscillation circuit driven with the output voltage of the power supply circuit A timepiece LSI driven by the output voltage of the power supply circuit and operated by a signal output from the oscillation circuit, and a predetermined voltage level at which the output voltage of the power supply circuit is slightly higher than the operation lower limit voltage of the timepiece LSI Until the output of the all-clear signal to the timepiece LSI, until the output voltage reaches the operation lower limit voltage and the oscillation operation start voltage of the oscillation circuit higher than the predetermined voltage, And an all-clear circuit unit that continues to output the all-clear signal .
Therefore, when the power supply voltage is recovered by the charging recovery of the power supply circuit, Ru can return the operation of the electronic circuit automatically normal operation.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of an electronic wristwatch with a solar cell according to an embodiment of the present invention.
[0009]
This electronic wristwatch includes a clock LSI 10.
The timepiece LSI 10 includes a CPU, a ROM, and a RAM therein, and controls the operation of each unit in accordance with a system program stored in advance in the ROM, for example. A secondary battery power supply (VBAT) 12 charged by the power generation operation by is connected.
[0010]
An overcharge prevention circuit 13 and a backflow prevention diode 14 for the secondary battery power supply 12 are connected between the solar power generation device 11 and the secondary battery power supply 12. On the other hand, the electronic wristwatch performs operations such as an oscillation circuit 14 that outputs an oscillation signal of, for example, 32 kHz, which becomes a basic clock signal CLK for operating the clock LSI 10, time setting, alarm setting, timer setting, mode switching, and the like. Switch 15, a display device 16 composed of a liquid crystal screen for displaying in accordance with each operation mode, and a sounding device 17 for generating a buzzer sound such as a time signal sound and an alarm sound, all of which are connected to the clock LSI 10. Is done.
[0011]
Further, the electronic wristwatch includes a power supply voltage Vbat supplied from the secondary battery power supply (VBAT) 12 to the timepiece LSI 10, a basic clock signal CLK output from the oscillation circuit 14, and a timepiece based on the basic clock signal CLK. An AC circuit unit 18 is provided that outputs an all clear (initial setting) signal AC for the timepiece LSI 10 according to the divided pulse signal BU and the operation clock signal CK output from the LSI 10.
[0012]
The AC circuit unit 18 is configured such that when the power supply voltage of the secondary battery power supply 12 is lowered to a predetermined voltage level slightly higher than the operation lower limit voltage of the timepiece LSI 10 due to insufficient charging from the solar power generation device 11, for example. The output of the all clear (initial setting) signal AC to the timepiece LSI 10 is started, and the power source voltage of the secondary battery power source 12 starts the oscillation operation by the oscillation circuit 14 by the charge recovery from the solar power generator 11, for example. The output of the all clear (initial setting) signal AC to the clock LSI 10 is continued until a certain time has elapsed after reaching the voltage.
[0013]
The oscillation start voltage of the oscillation circuit 14 is higher than a predetermined voltage level detected by the AC circuit unit 18, and the oscillation stop voltage is lower than the operation lower limit voltage of the timepiece LSI 10 and from the operation voltage of the CMOS-IC. It is set with high hysteresis characteristics.
[0014]
FIG. 2 is a block diagram showing the configuration of the AC circuit unit 18 in the solar cell equipped electronic wristwatch.
The AC circuit unit 18 is configured by combining a latch circuit FF, a voltage drop AC circuit 20, an oscillation stop detection circuit 21, a delay counter 22, two NAND gates NAND-A and NAND-B, and an inverter INV.
[0015]
The output signal of the NAND gate NAND-A is supplied to the set terminal S of the latch circuit FF, the divided pulse signal BU output from the timepiece LSI 10 is supplied to the input terminal I, and the timepiece LSI 10 is supplied to the clock terminal CK. Is supplied with an operation clock signal CK.
[0016]
An enable signal EN for the voltage drop AC circuit 20 is output from the output terminal X of the latch circuit FF.
The output signal OUT of the voltage drop AC circuit 20 is supplied to the first terminal of the NAND gate NAND-A and also to the first terminal of the NAND gate NAND-B.
[0017]
On the other hand, the basic clock signal CLK output from the oscillation circuit 14 is supplied to the input terminal IN of the oscillation stop detection circuit 21, and the output signal OUT is supplied to the second terminals of the NAND gates NAND-A and NAND-B. Supplied together.
[0018]
The output signal of the NAND gate NAND-B is supplied to the reset terminal R of the delay counter 22, and the basic clock signal CLK output from the oscillation circuit 14 is supplied to the counter clock terminal CK of the delay counter 22. The counter output signal OUT is output to the timepiece LSI 10 as the all clear (initial setting) signal AC through the inverter INV.
[0019]
The delay counter 22 keeps the basic clock signal CLK supplied to the clock terminal CK constant from the time when the output signal of the NAND gate NAND-B changes from “H” to “L” and the supply of the reset signal R stops. Counting time, the counter output signal OUT is changed from “L” to “H”, and the all clear (initial setting) signal AC is changed from “H” to “L”.
[0020]
FIG. 3 is a circuit diagram showing a configuration of the voltage drop AC circuit 20 in the AC circuit unit 18 of the solar cell equipped electronic wrist watch.
The voltage drop AC circuit 20 is configured by combining a comparator 20a and reference voltage setting units 20b and 20c, and the enable signal EN supplied from the output terminal X of the latch circuit FF is “L” and the comparator circuit is OFF. The output signal OUT is “H”, and when the enable EN is “H” and the comparator circuit is ON, the output signal OUT is such that the power supply voltage Vbat of the secondary battery power supply 12 is lower than a predetermined voltage level. When it is high, it becomes “H”, and when it is low, it becomes “L”.
[0021]
FIG. 4 is a circuit diagram showing a configuration of the oscillation stop detection circuit 21 in the AC circuit unit 18 of the solar cell equipped electronic wristwatch.
The oscillation stop detection circuit 21 is provided between the input terminal IN and the node 1 of the NOR gate NOR at the output end, and corresponds to the signal period of the 32 kHz basic clock signal CLK supplied from the oscillation circuit 14 to the input terminal IN. A pair of switch elements SW1a and SW2a that are alternately turned ON, and another pair of switch elements SW1b and SW2b that are provided between the switch elements SW1a and SW2a and the node 2 of the NOR gate NOR so as to perform an inversion operation. In each of the first switch elements SW1a and SW1b, a high resistance R is connected in series with VDD in each of the first switch elements SW1a and SW1b. Also, in each of the second switch elements SW2a and SW2b, Capacitors Ca and Cb are connected in parallel.
[0022]
That is, in the oscillation stop detection circuit 21, in a state of oscillation in which the basic clock signal CLK from the oscillation circuit 14 is supplied to the input terminal IN, the pair of switch elements SW1a, SW2a, SW1b, SW2b are alternately arranged. However, since the high resistance R is connected in series to each of the switching elements SW1a and SW1b on the VDD side, both the node 1 and the node 2 are substantially at the VCH level “L” and pass through the NOR gate NOR. The output signal OUT becomes “H”.
[0023]
In the oscillation stop detection circuit 21, in the oscillation stop state where the basic clock signal CLK from the oscillation circuit 14 is not supplied to the input terminal IN, the input terminal IN is fixed to “H” and fixed to “L”. There are two cases of the case, but when “H” is fixed, the switch elements SW1a and SW1b are turned on and off, and the switch elements SW2a and SW2b are turned off and on, respectively. While being charged to the VDD level “H”, the node 2 becomes the VCH level “L”, and the output signal OUT via the NOR gate NOR becomes “L”.
[0024]
When the input terminal IN is fixed to “L”, the node 1 is set to the VCH level “L” and the node 2 is set to the VDD level “H” by an operation opposite to the case where the input terminal IN is fixed, and the output is made via the NOR gate NOR. Similarly, the signal OUT becomes “L”.
[0025]
Next, the output operation of the all clear (initial setting) signal AC accompanying the fluctuation of the power supply voltage of the electronic wristwatch with the solar cell having the above configuration will be described.
FIG. 5 is a timing chart showing the output operation of the all clear (initial setting) signal AC accompanying the fluctuation of the power supply voltage of the solar cell equipped electronic wristwatch.
[0026]
FIG. 6 is a timing chart showing the output operation of the all clear (initial setting) signal AC when the power supply voltage of the electronic wristwatch with solar cell is lowered.
FIG. 7 is a timing chart showing an output operation of the all clear (initial setting) signal AC when the power supply voltage of the electronic wristwatch with solar cells is increased.
[0027]
First, when the power supply voltage Vbat by the secondary battery power supply 12 is higher than a predetermined voltage detection level in the voltage drop AC circuit 20, the divided pulse signal BU output from the timepiece LSI 10 is output from the timepiece LSI 10. The latch circuit FF of the AC circuit unit 18 is latched according to the operation clock signal CK, and the enable signal EN synchronized with the divided pulse signal BU is supplied to the voltage drop AC circuit 20 from the output terminal X of the latch circuit FF.
[0028]
At this time, as shown in FIG. 3, the output signal OUT of the voltage drop AC circuit 20 is that the enable signal EN is “L” while the comparator circuit is OFF, and the enable signal EN is “H”. Regardless of the ON state, it remains “H” (timing a).
[0029]
At this time, since the output signal OUT of the oscillation stop detection circuit 21 is held at “H” during oscillation, the output signals of the NAND gates NAND-A and NAND-B are both “L”.
[0030]
For example, when there is no light incident on the solar power generation device 11 and the secondary battery power supply 12 is insufficiently charged, and the power supply voltage Vbat is gradually lowered and falls below a predetermined voltage detection level in the voltage drop AC circuit 20, In response to the enable signal EN output from the latch circuit FF, the output signal of the voltage drop AC circuit 20 changes from “H” to “L”, and the outputs of the NAND gates NAND-A and NAND-B both change from “L” to “H”. (Timing b).
[0031]
Then, the reset signal R “H” from the NAND gate NAND-B is supplied to the delay counter 22, and the counter output signal OUT of the delay counter 22 is changed from “H” to “L” and all cleared (initially). Setting) signal AC changes from “L” to “H”.
[0032]
At this time, since the output of the NAND gate NAND-A remains changed to “H” and the latch circuit FF remains set, the enable signal EN in the voltage drop AC circuit 20 is continuously held at “H”. (Timing c).
[0033]
When the power supply voltage Vbat by the secondary battery power supply 12 decreases and falls below the oscillation stop voltage in the oscillation circuit 14, the output signal OUT from the oscillation stop detection circuit 21 changes to "L" during oscillation stop ( Timing d).
[0034]
Thereafter, when the power supply voltage Vbat by the secondary battery power supply 12 further decreases and falls below the operating voltage of the CMOS-IC, the enable signal EN and its output signal OUT in the voltage drop AC circuit 20, the oscillation stop detection circuit 21. Output signal OUT also becomes indefinite. For example, when charging of the secondary battery power supply 12 by the solar power generation device 11 is resumed and the power supply voltage Vbat returns to the operating voltage of the CMOS-IC or higher, the NAND gate NAND-A The output signal OUT of the voltage drop AC circuit 20 is “L”, and the output signal of the NAND gate NAND-B is “H”. All clear (initial setting) signal output from the delay counter 22 via the inverter INV. C is maintained at "H" (timing e).
[0035]
When the power supply voltage Vbat by the secondary battery power supply 12 further rises and returns to a predetermined voltage detection level in the voltage drop AC circuit 20, the output signal OUT of the voltage drop AC circuit 20 changes from “L” to “H”. "(Timing f).
[0036]
Thereafter, when the power supply voltage Vbat by the secondary battery power supply 12 further increases and returns to the oscillation start voltage in the oscillation circuit 14, the output signal OUT of the oscillation stop detection circuit 21 changes from “L” to “H”. The output signals of the NAND gates NAND-A and NAND-B change from “H” to “L”, and the generation timing of the enable signal EN supplied from the latch circuit FF to the voltage drop AC circuit 20 is output from the clock LSI 10. The timing changes in accordance with the divided pulse signal BU and the operation clock signal CK, and the reset signal R of the delay counter 22 changes from “H” to “L”. A counting operation for a predetermined time (T) is started (timing g).
[0037]
When the count operation for a predetermined time T by the delay counter 22 is completed from the time point when the oscillation operation of the oscillation circuit 14 starts and the normal operation of the timepiece LSI 10 is restored, the counter output signal OUT changes from “L” to “H”. The all clear (initial setting) signal AC changes from “H” to “L” (timing h).
[0038]
As a result, the all clear (initial setting) signal AC for the timepiece LSI 10 is generated for a certain time after the power supply voltage Vbat by the secondary battery power supply 12 is restored to the oscillation operation voltage of the oscillation circuit 14 after the operation voltage of the timepiece LSI 10 is restored. It is released after being maintained until T elapses, and it is possible to reliably return to normal circuit operation.
[0040]
Further, according to the electronic wristwatch with a solar cell having the above-described configuration, the all clear (initial setting) signal AC supplied to the timepiece LSI 10 when the power supply voltage Vbat is restored is generated after the oscillation operation by the oscillation circuit 14 is started. Since the configuration is such that the basic clock signal CLK is counted after being released by a predetermined number (fixed time: T), the all-clear process for the clock LSI 10 can be surely performed and the normal clock operation can be restored.
[0041]
In the embodiment, the case where the solar power generation device 11 is used as the power generation means for charging the secondary battery power source 12 in the electronic wristwatch is described. It consists of a rotating spindle and a motor having a rotor and a coil, and uses a method in which the rotation of the rotating spindle is accelerated and transmitted to the rotor of the motor to rotate the rotor and charged by an induced current generated in the coil. May be.
[0042]
【The invention's effect】
As described above, according to the power generation device with the electronic apparatus according to claim 1 of the present invention, when the power supply voltage is recovered by the charging recovery of the power supply circuit, so that it is possible to return the operation of the electronic circuit automatically normal operation Become.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an electronic wristwatch with a solar cell according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of an AC circuit section in the electronic wristwatch with a solar cell.
FIG. 3 is a circuit diagram showing a configuration of a voltage drop AC circuit in an AC circuit part of the solar cell equipped electronic wrist watch.
FIG. 4 is a circuit diagram showing a configuration of an oscillation stop detection circuit in an AC circuit section of the solar cell equipped electronic wrist watch.
FIG. 5 is a timing chart showing an output operation of an all clear (initial setting) signal AC according to fluctuations in power supply voltage of the electronic wristwatch with solar cells.
FIG. 6 is a timing chart showing an output operation of an all clear (initial setting) signal AC when the power supply voltage of the electronic wristwatch with solar cells is lowered.
FIG. 7 is a timing chart showing an output operation of an all clear (initial setting) signal AC when the power supply voltage of the electronic wristwatch with solar cells is increased.
[Explanation of symbols]
10: Clock LSI,
11 ... solar power generator,
12 ... secondary battery power supply,
13: Overcharge prevention circuit,
14 ... backflow prevention diode,
15 ... switch,
16 ... display device,
17… reporting device,
18: AC circuit section,
20 ... Voltage drop AC circuit,
21: Oscillation stop detection circuit,
22 ... delay counter,
FF ... latch circuit,
AC: All clear (initial setting) signal.

Claims (1)

A power supply circuit having a power generation means and a power storage means charged with an output voltage of the power generation means;
An oscillation circuit driven by the output voltage of the power supply circuit;
A clock LSI that is driven by an output voltage of the power supply circuit and is operated by a signal output from the oscillation circuit;
When the output voltage of the power supply circuit drops to a predetermined voltage level slightly higher than the operation lower limit voltage of the timepiece LSI, the output of the all clear signal to the timepiece LSI is started, and the output voltage is set to the operation lower limit voltage. And an all-clear circuit unit that continues to output the all-clear signal until reaching a start voltage of the oscillation operation of the oscillation circuit that is higher than the predetermined voltage .

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