JP3737660B2 - Digital signal processing circuit and communication apparatus provided with the circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital signal processing circuit that performs encoding and decoding processing of, for example, a video signal and an audio signal, and a communication apparatus such as a portable information terminal, a cellular phone, and an in-vehicle information communication terminal including the circuit.
[0002]
[Prior art]
With the spread of digital contents such as MPEG (Moving Picture Coding Experts Group), the importance of digital signal processing technology is increasing. When such digital signal processing is realized in a communication apparatus such as a portable information terminal or a mobile phone, it is common to use a processor such as a DSP (Digital Signal Processor) or a RISC (Reduced Instruction Set Computer). .
[0003]
By the way, when digital signal processing is performed using these processors, the word length of the digital signal is directly related to the calculation accuracy. If the word length is short, the hardware resources such as the bit width of the arithmetic unit and the memory capacity can be reduced. However, depending on the contents of the signal processing, the influence on the quality becomes large. Especially when performing multimedia signal processing that handles video signals and audio signals, sufficient quality cannot be obtained if the word length is insufficient. Therefore, in order to ensure quality, a method to match the word length of the digital signal to the shortest word length that satisfies the required quality and a method to compensate for the shortage of word length by software processing to ensure calculation accuracy are studied. Has been.
[0004]
[Problems to be solved by the invention]
However, in digital signal processing, what greatly affects quality is the case where errors are accumulated by performing further computations on the computation results. Such computation processing is a small part of the overall processing. Often. For this reason, giving the maximum word length for all the arithmetic processes in accordance with some arithmetic processes increases the circuit scale and increases the cost in terms of hardware resources such as the bit width and memory capacity of the arithmetic unit. Is undesirable.
[0005]
On the other hand, the method of compensating for the shortage of word length by software processing is effective in terms of hardware resources, but is not suitable for signal processing that requires real-time characteristics because it tends to cause processing delay. In addition, since an increase in processing amount causes an increase in power consumption, it is very undesirable particularly in battery-driven communication devices such as portable information terminals and cellular phones.
[0006]
For example, in multimedia signal processing that requires real-time performance, it is necessary to perform routine arithmetic processing such as filter calculation and correlation calculation at high speed. In addition, since this type of arithmetic processing tends to accumulate arithmetic errors due to a finite word length, high-precision arithmetic processing is required. However, when performing this type of arithmetic processing, RISC has a large overhead such as addressing and it is difficult to perform efficient arithmetic.
[0007]
On the other hand, DSP can perform high-speed routine operations such as filter operations. However, since the types of operations are limited, it is not good at performing irregular operations at high speed. However, it is difficult to describe logic in a high-level language, and there is a problem in development efficiency.
[0008]
The present invention has been made paying attention to the above circumstances, and its purpose is to reduce the memory capacity, to make the hardware resources small and inexpensive, and to provide high accuracy for multiple types of digital signals having different word lengths. It is an object of the present invention to provide a digital signal processing circuit capable of performing the above arithmetic processing and a communication device including this circuit.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention performs arithmetic processing on a first digital signal having a first word length and a second digital signal having a second word length longer than the first word length, respectively. In the digital signal processing circuit, a main arithmetic processing circuit and a dedicated arithmetic processing circuit connected to the main arithmetic processing circuit are provided,
The main arithmetic processing circuit includes a main arithmetic unit having an arithmetic processing function corresponding to the first word length, and a first memory having a storage capacity of a unit storage area corresponding to the first word length And when storing the first digital signal in the first memory, the one word length is stored in the unit storage area of the first memory, When storing the second digital signal, the word length is divided and stored in a plurality of unit storage areas of the first memory. Then, the first digital signal is supplied to the main arithmetic unit to perform arithmetic processing, and the second digital signal is transferred to the dedicated arithmetic processing circuit.
[0010]
On the other hand, the dedicated arithmetic processing circuit includes a dedicated arithmetic unit having an arithmetic processing function corresponding to the second word length, and a second storage unit having a storage capacity corresponding to the second word length. And a dedicated arithmetic control means. Then, the dedicated arithmetic control means uses the dedicated arithmetic unit and the second memory to supply the second digital signal transferred from the main arithmetic processing circuit to the dedicated arithmetic unit to perform arithmetic processing. The result of the arithmetic processing is returned to the main arithmetic processing circuit.
[0011]
Therefore, according to the present invention, for example, the first digital signal having a normal word length is processed by the main arithmetic processing circuit, while the second digital signal having a long word length is transferred to the dedicated arithmetic processing circuit. Arithmetic processing is performed. For this reason, the main arithmetic processing circuit only needs to perform the digital signal processing of the normal word length, so that it is not necessary to prepare the arithmetic unit and the memory corresponding to the word length of the second digital signal. Accordingly, the hardware resources of the main arithmetic processing circuit can be made small and inexpensive. In terms of software, it is not necessary to compensate for the shortage of word length with software, so high-quality processing can be performed in real time.
[0012]
In addition, the memory required for the dedicated arithmetic processing circuit only needs to be capable of temporarily storing a small number of words of digital signals transferred from the main arithmetic processing circuit, so that a relatively small capacity is required, and the arithmetic unit supports standard arithmetic processing. Because it is sufficient, it can be relatively small. For this reason, the configuration of the dedicated arithmetic processing circuit can also be suppressed to a relatively small scale.
[0013]
Further, according to the present invention, when the second digital signal is stored in the memory of the main arithmetic processing circuit, the word length is divided and stored in a plurality of unit storage areas, so that the memory is wasted. There is an advantage that it can be used efficiently without generating a surplus storage area.
[0014]
According to the present invention, word length conversion means is provided in at least one of the main arithmetic processing circuit and the dedicated arithmetic processing circuit, and when the second digital signal is transferred by the word length conversion means, the word length is changed to the first length. It is also characterized by conversion between the word length and the second word length.
[0015]
With this configuration, even if the second digital signal is stored in a plurality of unit storage areas by dividing the word length in the first memory of the main arithmetic processing circuit, the second digital signal is stored. Since the word length is converted at the time of signal transfer, the main arithmetic processing circuit does not need to replace the data order of the second digital signal, which eliminates the need for a large number of memory accesses and shift arithmetic processing. Generation can be reduced.
[0016]
Further, according to the present invention, data order conversion means is provided in at least one of the main arithmetic processing circuit and the dedicated arithmetic processing circuit, and when the second digital signal is transferred by the data order conversion means, the processing contents in the dedicated arithmetic processing section are provided. It is also characterized in that the data order is converted accordingly.
With this configuration, it is possible to increase the efficiency of the arithmetic processing by reducing the number of arithmetic processing steps in the arithmetic unit of the dedicated arithmetic processing circuit.
[0017]
Furthermore, the present invention is characterized in that another process is executed in the main arithmetic processing circuit during a period from when the second digital signal is transferred to the dedicated arithmetic processing circuit until the arithmetic processing result is returned.
By configuring in this way, the main arithmetic processing circuit and the dedicated arithmetic processing circuit can be operated in parallel, thereby improving the signal processing efficiency of the entire circuit.
[0018]
Furthermore, according to the present invention, the main arithmetic processing circuit may set its operation state to a resting state during a period from when the second digital signal is transferred to the dedicated arithmetic processing circuit until the arithmetic processing result is returned. It is a feature.
With this configuration, it is possible to reduce the power consumption of the main arithmetic processing circuit and save the power of the entire circuit as compared with the case where the main arithmetic processing circuit is always operated.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of a communication apparatus according to the present invention, and is a circuit block diagram of a multimedia mobile communication terminal apparatus.
[0020]
First, the receiving system is configured as follows. That is, a radio frequency signal arriving from a base station or a relay station (not shown) is received by the antenna 1 and then input to the radio unit 2, where frequency conversion and digital demodulation processing are performed. In the baseband processing unit 3, reception baseband processing such as error correction decoding processing and de-interleaving processing is performed on the demodulated digital signal output from the radio unit 2, and the received digital signal after this processing is demultiplexed 4 is input. The demultiplexer 4 separates audio data, video data, and computer data from the received digital signal according to the contents of the header information. The audio signal processor 5, video signal processor 6, and data processor 7 are respectively separated. Is input.
[0021]
The audio signal processing unit 5 includes a digital signal processing circuit constituting an audio codec, and performs audio decoding processing on the received audio data. Then, the decoded audio signal is loudly output from the speaker 51.
[0022]
The video signal processing unit 6 performs a video decoding process defined in, for example, MPEG4 on the received video data, and supplies the video signal reproduced thereby to the display control unit 8.
[0023]
The data processing unit 7 converts the received computer data into a displayable form and inputs it to the display control unit 8. The display control unit 8 selectively displays the video signal and the computer data on a liquid crystal display unit (LCD) 9.
[0024]
On the other hand, the transmission system is configured as follows. That is, the audio signal input from the microphone 52 is input to the audio signal processing unit 5 where it is encoded by the audio codec. A video signal obtained by imaging by the camera 61 is encoded by the video signal processing unit 6 according to an encoding method defined in MPEG4. Further, computer data such as a document file input from the input unit 14 or read from the storage unit 13 is input from the main control unit 10 to the data processing unit 7 and is transmitted here as necessary. Is input to the demultiplexing unit 4.
[0025]
The demultiplexing unit 4 receives the transmission audio data output from the audio signal processing unit 5, the transmission video data output from the video signal processing unit 6, and the computer data output from the data processing unit 7 in a predetermined manner. For example, a transmission packet is generated by multiplexing according to the format.
[0026]
The baseband processing unit 3 performs transmission baseband signal processing such as error correction coding and interleaving on the transmission packet, and inputs the processed transmission packet to the radio unit 2. The radio unit 2 performs digital modulation processing, frequency conversion to a radio transmission frequency, and control of a transmission power level on the transmission packet, and a radio frequency signal generated thereby is transmitted from the antenna 1 to the base station or relay station. Sent to.
[0027]
In the figure, reference numeral 12 denotes a power supply circuit unit which generates a predetermined operating voltage Vcc based on the output voltage of the battery 11 and supplies it to each circuit module in the apparatus.
[0028]
Incidentally, the audio signal processing unit 5 and the video signal processing unit 6 are provided with a digital signal processing circuit according to the present invention. Here, a digital signal processing circuit provided in the audio signal processing unit 5 will be described as an example.
[0029]
FIG. 2 is a block diagram showing a schematic configuration of a digital signal processing circuit for audio signal processing. The digital signal processing circuit includes a main processor 20, a dedicated engine 30 connected to the main processor 20 via a control signal line 60, a direct memory access (DMA) controller 40, and an external interface (I / F). Circuit 50.
[0030]
The main processor 20 includes an arithmetic core 21, an instruction memory (IMEM) 22 that stores an instruction (program) for causing the arithmetic core 21 to perform signal processing, and a data memory (DMEM) that stores a digital signal to be processed. 23. The arithmetic core 21 is configured so that the arithmetic width and the like correspond to a digital signal with normal accuracy, for example, audio data in which 16 bits are one word. In the data memory 23, a storage area that can be specified by one address is set to 16 bits corresponding to the digital signal with the normal accuracy.
[0031]
In contrast, the dedicated engine 30 includes a high-precision arithmetic core 31 and a data memory (DMEM) 32. The high-precision arithmetic core 31 is configured to correspond to a high-precision digital signal having a word width longer than that of the normal-precision digital signal, for example, 24-bit audio data. The data memory 32 stores the high-precision digital signal transferred from the main processor 20 and the data to be returned to the main processor 20 after completion of the operation, and corresponds to the high-precision digital signal. The storage area that can be specified by one address is set to 24 bits.
[0032]
Incidentally, the arithmetic core 21 of the main processor 20 is configured as follows. FIG. 3 is a circuit block diagram showing the configuration.
That is, the decode circuit 214 reads the instruction stored in the storage area of the address indicated by the program counter (PC) 212 from the instruction memory 22 via the instruction memory interface (IMEM IF) 213, and decodes this instruction. This is given to the control circuit 211. Note that the value of the program counter 212 indicates an address to be sequentially read out unless it is updated by the control circuit 211.
[0033]
Based on the decoding result of the above instruction, the control circuit 211 loads data from the data memory 23 to the 16-bit word register file 215 via the data memory interface (DMEM IF) 217, or conversely from the register file 215 to the data memory. Each module is controlled such that data is stored in the register 23, data in the register file 215 is passed to the arithmetic unit 216 to be operated, and the value of the program counter 212 is controlled. The arithmetic unit 216 includes an adder / subtracter and a multiplier.
[0034]
The control circuit 211 also has an interface function with the DMA controller 40, and designates an address and a size when data is DMA-transferred to the external interface 50 or the dedicated engine 30. The control circuit 211 further has an interface function with the dedicated engine 30, specifies calculation contents (CALC MODE) to the dedicated engine 30 via the control signal line 60, and the data memory 23 to the data memory of the dedicated engine 30. The data exchange order (DMA MODE) at the time of data transfer is designated, and the operation start instruction is given.
[0035]
The control circuit 211 also has a function of receiving a busy signal indicating a calculation state from the dedicated engine 30, and determines the calculation state of the dedicated engine 30 based on the busy signal. Based on the determination result, the operation of the main processor 20 itself is controlled while the dedicated engine 30 is in a busy state, that is, during a calculation operation.
[0036]
For example, if a process independent of the calculation result of the dedicated engine 30 can be executed, the instruction is executed. That is, a parallel operation with the dedicated engine 30 is performed. If the processing cannot be continued depending on the calculation result of the dedicated engine 30, the clock control circuit (CLK control circuit) 218 is instructed to stop the supply of the clock to each module. The main processor 20 is set in the sleep state until the process ends.
[0037]
On the other hand, the high-precision arithmetic core 31 of the dedicated engine 30 is configured as follows. FIG. 4 is a circuit block diagram showing the configuration.
[0038]
That is, the DMA MODE register 316 stores a mode indicating the rearrangement order of data transferred by the DMA via the DMA controller 40, and this mode is set by the main processor 20. The address conversion circuit 315 performs processing for changing the order of high-precision digital signals according to the mode stored in the DMA MODE register 316. Then, control is performed so that the data after the replacement process is stored in a predetermined address area of the data memory 32 via the data memory interface (data memory I / F) 314.
[0039]
The data memory 32 includes a table area 321 for storing coefficients for calculation and a data area 322 of 2read2write type. In this data area 322, for example, one address area is composed of 24 bits, and a 24-bit 1-word high-precision digital signal and data of the calculation result can be stored in the one address area as they are.
[0040]
The CALC MODE register 313 stores a mode indicating the calculation contents of the high-precision calculator 311 designated by the main processor 20. Upon receiving a calculation start signal from the main processor 20, the arithmetic control circuit 312 controls the high-precision arithmetic unit 311 and the data memory 32 according to the mode stored in the CALC MODE register 313.
[0041]
The high-precision calculator 311 includes two multipliers and two adders / subtractors, and performs, for example, a 4-point complex fast Fourier transform (FFT) calculation using these calculators. FIG. 5 shows an example of the configuration.
[0042]
Next, the operation of the digital signal processing circuit configured as described above will be described.
For example, when the audio data output from the demultiplexing unit 4 is input to the audio signal processing unit 5, it is taken into the main processor 20 from the external interface circuit 50 via the DMA controller 40 and stored in the data memory 23. The When decoding processing is performed on stored audio data, the intermediate data in the decoding process is processed with normal accuracy (16 bits) if the calculation accuracy is not sensitive to the reproduction quality. That is, the words are stored in the address areas of the data memory 23 as they are.
[0043]
On the other hand, a calculation whose calculation accuracy is sensitive to reproduction quality requires high-precision (24-bit) calculation and data retention as intermediate data. In this case, the high-precision digital signal cannot be stored as it is because the size of one word is larger than the size (16 bits) of one address area of the data memory 23. Therefore, a high-precision digital signal consisting of 24 bits and one word is divided into 16 bits on the MSB side and 8 bits on the LSB side, the 16 bits on the MSB side are stored in one address area of the data memory 23, and the 8 bits on the LSB side are stored in the next address. Store in the area or the previous address area.
[0044]
That is, 8 bits on the LSB side of each high-precision digital signal are stored in the empty area of the data memory 23. FIG. 6 shows an example of the storage state. By doing so, high-precision digital data can be efficiently stored without causing a wasteful empty area in the data memory 23.
[0045]
When the main processor 20 starts arithmetic processing in accordance with the instruction stored in the instruction memory 22 in this state, it is necessary to access the normal precision digital signal and the high precision digital signal stored in the data memory 23. In this case, if the data is normal precision, the control circuit 211 supplies the calculation unit 216 with the calculation.
[0046]
On the other hand, in the case of a high-precision digital signal, it is transferred from the main processor 20 to the dedicated engine 30 via the DMA controller 40 and is calculated in the dedicated engine 30.
[0047]
That is, the control circuit 211 of the main processor 20 first sends the mode information for designating the address and size of the transfer data and the data replacement order to the dedicated engine 30 and the mode information for designating the operation contents via the control signal line 60. Notify through. The dedicated engine 30 stores these pieces of information in the DMA MODE register 316 and the CALC MODE register 313, respectively. Subsequently, the main processor 20 sequentially transfers the high-precision digital signals stored in the data memory 23 to the dedicated engine 30 by the DMA controller 40.
[0048]
When the high-precision digital signal is transferred from the main processor 20 by the DMA controller 40, the dedicated engine 30 uses the address conversion circuit 315 in accordance with the mode information for designating the address, size, and replacement order of the transfer data previously notified. Perform data replacement processing.
[0049]
For example, since the high-precision digital signal is now stored in the data memory 23 in a state where one word is divided and packed in a free area as shown in FIG. 6, the addresses 1, 4, 7,. The two LSB side 8-bit data respectively stored in... Are divided, and the divided two LSB side 8 bit data respectively correspond to the MSB side 16-bit data before 1 byte and the MSB side 16-bit data after 1 byte. Thus, a 24-bit 1-word high-precision digital signal is constructed.
[0050]
At the same time, the address conversion circuit 315 also performs a data replacement process for efficiently performing the high-precision calculation according to the designated content of the high-precision calculation that has been previously notified. For example, if the processing content of the high-precision calculation is Fast Fourier Transform (FFT) described later, the order of data [5], data [13],... Is shown in FIG. Swap so that it is positioned next to.
[0051]
The high-precision digital signals whose data order has been changed are sequentially stored in the data area 322 in the data memory 32 via the data memory interface 314.
[0052]
Next, the dedicated engine 30 causes the high-precision arithmetic unit 311 to perform arithmetic processing of the content previously specified from the main processor 20 on the high-precision digital signal stored in the data memory 32.
[0053]
Hereinafter, a case where a 4-point complex FFT operation is performed will be described as an example. FIG. 8 shows the data flow of the arithmetic processing.
In the figure, data a, b, c, and d are complex data, respectively, and have a real part (xxx.re) and an imaginary part (xxx.im). j is an imaginary unit, and W is a complex coefficient. The high-precision computing unit 311 performs butterfly computation on the data a, b, c, and d stored in the data area 322 of the data memory 32 in the order of (1) to (7) in the data flow shown in FIG. The complex multiplication with the complex coefficient W stored in the table area 321 is repeatedly performed by an in-place operation.
[0054]
That is, the butterfly operation is
(x + jy) + (u + jv) = (x + u) + j (y + v)
(x + jy) − (u + jv) = (xu) + j (yv)
Can be calculated. Each piece of data x, y, u, v is 24 bit 1 word data stored in the data memory 32.
[0055]
First, data x and u are fetched from the data memory 32 to the corresponding latches L0 and L1 of the latch circuit unit 3111 via the ports P0 and P1 shown in FIG. Next, the selectors 3112 and 3115 are respectively controlled to input the data X of the latch L0 to the adder 3116 and the subtracter 3117, respectively, and input the data u of the latch L1 to the adder 3116 and the subtracter 3117, respectively. Then, addition and subtraction are respectively performed. The addition output (x + u) and the subtraction output (xu) are once latched by latches 3118 and 3119, respectively, and then output to the data memory 32 by the selector 3120 via the ports P4 and P5. Is stored in the address area where was stored. Thereafter, the same calculation is performed for the data y and v. Thus, a butterfly operation is performed.
[0056]
The complex multiplication is
(x + jy) x (u-jv) = (xu + yv) + (yu-xv)
Can be calculated. Here, the reason why the imaginary part of the second term on the left side is negative is to reduce the calculation in the middle. Since the second term on the left side is the coefficient data W stored in the table area 321 of the data memory 32, there is no problem in calculation if a negative value is prepared in advance.
[0057]
First, data x, y, u, v are fetched from the data memory 32 to the latches L0, L1, L2, L3 via the ports P0, P1, P2, P3, respectively. Next, the selector 3112 is controlled so that the data x of the latch L0 is input to the multiplier 3113, the data u of the latch L2 is input to the multipliers 3113 and 3114, and the data y of the latch L1 is input to the multiplier 3114. Thus, the multipliers 3113 and 3114 are caused to perform multiplication. Then, the selector 3115 is controlled so that the multiplication output (x × u) of the multiplier 3113 is input to the adder 3116, and the multiplication output (y × u) of the multiplier 3114 is input to the subtractor 3117. The other input terminals of the adder 3116 and the subtractor 3117 are input with a “0” value to perform addition and subtraction, respectively. The addition output (x × u) and subtraction output (y × u) of the adder 3116 and subtractor 3117 are latched in latches 3118 and 3119, respectively.
[0058]
Next, the selector 3112 is controlled to input the data y of the latch L1 to the multiplier 3113, the data x of the latch L0 to the multiplier 3114, and the data v of the latch L3 to the multipliers 3113 and 3114, respectively. This causes the multipliers 3113 and 3114 to perform multiplication. Then, by controlling the selectors 3115 and 3120, the multiplication output (y × v) of the multiplier 3113 is input to the adder 3116, and the multiplication output (x × v) of the multiplier 3114 is input to the adder 3116. Further, the previously calculated data (y × u) of the latch 3119 is fed back to the subtractor 3117, and the data (x × u) of the latch 3118 is fed back to the adder 3116, respectively. Add and subtract. As a result, the adder 3116 and the subtracter 3117 output (y × v) + (x × u) and (y × u) − (x × v), respectively, and these values are respectively latched by the latches 3118 and 3119. Latched.
[0059]
Then, (y × v) + (x × u) and (y × u) − (x × v) latched by these latches 3118 and 3119 are sent to the data memory 32 via the ports P4 and P5 by the selector 3120. And stored in the address area where the data x and u are stored. Thus, a complex multiplication operation is performed.
[0060]
The operation data thus obtained is read from the data area 322 of the data memory 32, and the address conversion circuit 315 converts the data of 1 word 24 bits into 1 word 16 bits of data, and then the DMA controller 40. Is transferred to the main processor 20 and stored in the data memory 23.
[0061]
On the other hand, in a state where the above-described arithmetic processing is performed in the dedicated engine 30, a signal indicating a busy state is notified from the dedicated engine 30 to the main processor 20. When the main processor 20 detects that the dedicated engine 30 is busy based on the busy signal, the main processor 20 determines whether other processing can be executed without depending on the calculation result of the dedicated engine 30. If there is an executable process, the process is executed.
[0062]
On the other hand, when other processing cannot be executed, the supply of the clock to each module other than the control circuit 211 is cut off, and the main processor 20 is set to the sleep state. In this case, the supply of the operating power supply voltage Vcc to each module other than the control circuit 211 may be cut off.
In this way, the processing efficiency of the entire circuit can be increased, and further, power consumption can be reduced.
[0063]
As described above, in this embodiment, the dedicated engine 30 is provided in addition to the main processor 20, and the arithmetic unit 216 in the main processor 20 is used for normal-precision digital data, and the main data is used for high-precision digital data. The data is transferred from the data memory 23 of the processor 20 to the dedicated engine 30 by the DMA controller 40 so that the high-precision arithmetic unit 311 of the dedicated engine 30 performs the calculation, and the high-precision digital signal is sent to the data memory 23 of the main processor 20. When storing, one word is divided and stored in a free area.
[0064]
Therefore, according to this embodiment, since the calculation of the high-precision digital signal is performed by the dedicated engine 30 configured exclusively for it, a high-quality calculation result can always be obtained. Further, since it is not necessary to perform software arithmetic processing for compensating for the shortage of word length in the main processor 20, it is possible to prevent the occurrence of processing delay and to maintain the real-time property of signal processing.
[0065]
Further, since the main processor 20 does not need to perform high-precision digital data arithmetic processing, the size of the arithmetic unit 216 of the main processor 20 and the size of one address area of the data memory 23 correspond to normal-precision digital data. Can be limited to size. In addition, since the high-precision digital signals are stored in the data memory 23 in a packed state, useless empty areas do not occur and high-density storage is possible. Therefore, it is possible to reduce the capacity of the data memory 23, thereby reducing the circuit scale and price of the main processor 20.
[0066]
However, in this embodiment, there is a concern about the increase in the overall circuit scale due to the addition of the dedicated engine 30, but the high-precision computing unit 311 of the dedicated engine 30 is configured to exclusively perform routine operations such as FFT operations. Therefore, a relatively small circuit can be obtained, and it is sufficient for the data memory 32 to store the second digital data for a few bytes, and a small-capacity circuit can be used. For this reason, even if the dedicated engine 30 is added, it is possible to minimize the increase in the size of the entire hardware.
[0067]
In this embodiment, the dedicated engine 30 is provided with an address conversion circuit 315, and a high-precision digital signal stored in the data memory 23 of the main processor 20 is DMA-transferred to the dedicated engine 30 as it is, and the address conversion circuit 315 performs data transfer. After the conversion of the order, the data is stored in the data memory 32 in the dedicated engine 30. For this reason, it is not necessary for the main processor 20 to convert the data order of the high-precision digital signals, and therefore, overhead due to a plurality of addressing and the like can be prevented.
[0068]
Further, in this embodiment, when the dedicated processor 30 is busy (in operation), when the main processor 20 can execute a process that does not depend on the calculation result of the dedicated engine 30, the process is executed. When it is necessary to execute processing depending on the calculation result, the main processor 20 is set in the sleep state. For this reason, it is possible to improve the processing efficiency of the entire circuit and reduce power consumption.
[0069]
The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the data order is changed in the address conversion circuit 315 provided in the dedicated engine 30. However, the address conversion circuit may be provided in the DMA controller 40 to perform address conversion here. Good.
[0070]
In the embodiment, the case where the FFT operation is performed by the dedicated engine has been described as an example. However, the MDCT (Modified Discrete Cosine Transform) operation, the IMDCT (needed in the filtering process, the windowing process, and the audio signal encoding process are also described. Inverse MDCT) calculation may be performed.
[0071]
For example, in the case of the windowing process, the multiplication data is stored in the data area 322 of the data memory 32 and the multiplication coefficient is stored in the table area 321. This can be realized by sequentially reading out these data, performing multiplication, passing through addition and subtraction processing, and storing the multiplication result data in the original area of the data area 322.
[0072]
In many cases, the windowing process has a symmetrical window coefficient as shown in FIG. 9 as a multiplication coefficient (for example, sin data). In this case, when the coefficient data is transferred from the main processor 20 to the dedicated engine 30, the first half is transferred as usual (data transfer order A) and the windowing process is performed, and the second half is reverse to the first half (data transfer order). If the windowing process is performed by transferring in B), half of the coefficient data that must be retained is sufficient. In addition, if the processing control circuit of the dedicated engine adds and processes a reverse reading mode when coefficient data is fetched, the number of times of data transfer can be reduced.
[0073]
The circuit configuration of the main processor and the dedicated engine, the configuration of the data transfer means (not limited to the DMA transfer), the type and configuration of the communication device, and the like are variously modified without departing from the gist of the present invention. it can.
[0074]
【The invention's effect】
As described above in detail, in the present invention, in addition to the main arithmetic processing circuit corresponding to the first word length of the normal word length, a dedicated arithmetic processing circuit corresponding to the second word length of the long word length is provided, The digital signal is supplied to the arithmetic unit of the main arithmetic processing circuit to perform arithmetic processing, and the second digital signal is transferred to the dedicated arithmetic processing circuit to perform arithmetic processing, and the main arithmetic processing is performed. When the first digital signal is stored in the first memory of the circuit, the one word length is stored in the unit storage area of the first memory, and when the second digital signal is stored, the one word length is stored. Is divided and stored in a plurality of unit storage areas of the first memory.
[0075]
Therefore, according to the present invention, there is provided a digital signal processing circuit that reduces memory capacity, retains hardware resources in a small size and at low cost, and enables high-precision arithmetic processing for a plurality of types of digital signals having different word lengths. A communication device including a circuit can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram of a multimedia mobile communication terminal device, showing an embodiment of a communication device according to the present invention.
FIG. 2 is a block diagram showing a schematic configuration of a digital signal processing circuit for audio signal processing.
FIG. 3 is a circuit block diagram showing a configuration of an arithmetic core of the main processor.
FIG. 4 is a circuit block diagram showing a configuration of a high-precision arithmetic core of a dedicated engine.
FIG. 5 is a circuit block diagram illustrating a configuration example of a high-precision arithmetic unit that performs a four-point complex fast Fourier transform (FFT) operation;
FIG. 6 is a diagram showing an example of a storage state of high-precision digital signals in the data memory of the main processor.
FIG. 7 is a diagram showing an example when the data order of high-precision digital signals is changed.
FIG. 8 is a diagram showing a data flow of calculation processing when performing a 4-point complex FFT calculation;
FIG. 9 is a diagram for explaining a data inversion transfer operation in a case where a filtering operation with symmetrical characteristics is performed.
[Explanation of symbols]
1 ... Antenna
2 ... Radio part
3. Baseband processing unit
4 ... Demultiplexer
5 ... Audio signal processor
6 ... Video signal processor
7: Data processing section
8. Display control unit
9 ... Liquid crystal display (LCD)
10 ... Main control section
10: Demultiplexing unit
11 ... Battery
12 ... Power circuit section
13 ... Storage unit
14 ... Input section
20 ... main processor
21 ... Calculation core
22 ... Instruction memory (IMEM)
23 ... Data memory (DMEM)
30 ... Special engine
31 ... High-precision computing core
32 ... Data memory (DMEM)
40 ... DMA controller
50. External interface circuit
51. Speaker
52 ... Microphone
60 ... Control signal line
61 ... Camera
211 ... Control circuit
212 ... Program counter (PC)
213 ... Instruction memory interface (IMEM IF)
214 ... Decoding circuit
215: Register file
216 ... Calculator
311: High precision computing unit
312 ... Calculation control circuit
313: CALC MODE register
314: Data memory interface
315: Address conversion circuit
316: DMA MODE register
321 ... Table area
322 ... Data area
3111: Latch circuit section
3112, 3115, 3120 ... selector
3113, 3114 ... multiplier
3116: Adder
3117: Subtractor
3118, 3119 ... Latch

Claims (6)

In a digital signal processing circuit for performing arithmetic processing on a first digital signal having a first word length and a second digital signal having a second word length longer than the first word length,
A main arithmetic processing circuit and a dedicated arithmetic processing circuit connected to the main arithmetic processing circuit;
The main arithmetic processing circuit includes:
A main arithmetic unit having an arithmetic processing function corresponding to the first word length;
A first memory having a storage capacity of a unit storage area corresponding to the first word length;
When storing the first digital signal in the first memory, the one word length is stored in the unit storage area of the first memory, and when storing the second digital signal, the first digital signal is stored. Digital signal storage control means for dividing and storing one word length across a plurality of unit storage areas of the first memory;
Of the first and second digital signals stored in the first memory, the first digital signal is supplied to the main arithmetic unit to perform arithmetic processing, and the second digital signal is used as the dedicated digital signal. Arithmetic control means for transferring to the arithmetic processing circuit,
The dedicated arithmetic processing circuit is
A dedicated arithmetic unit having an arithmetic processing function corresponding to the second word length;
Dedicated arithmetic control means for supplying the second digital signal transferred from the main arithmetic processing circuit to the dedicated arithmetic unit to perform arithmetic processing, and transferring the arithmetic processing result to the main arithmetic processing circuit;
The storage capacity of the unit storage area is configured to correspond to the second word length, and temporarily holds the second digital signal transferred from the main arithmetic processing circuit and the arithmetic processing result obtained by the dedicated arithmetic unit. A digital signal processing circuit comprising: a second memory. At least one of the main arithmetic processing circuit and the dedicated arithmetic processing circuit converts the word length between the first word length and the second word length when transferring the second digital signal. The digital signal processing circuit according to claim 1, further comprising: At least one of the main arithmetic processing circuit and the dedicated arithmetic processing circuit further includes data order conversion means for converting the data order according to the processing content in the dedicated arithmetic unit when transferring the second digital signal. The digital signal processing circuit according to claim 1. 2. The main arithmetic processing circuit executes another process in a period from when the second digital signal is transferred to the dedicated arithmetic processing circuit until the arithmetic processing result is returned. The digital signal processing circuit described. The main arithmetic processing circuit sets itself to an operation pause state during a period from when the second digital signal is transferred to the dedicated arithmetic processing circuit until the arithmetic processing result is returned. Item 2. The digital signal processing circuit according to Item 1. In a communication device that performs predetermined signal processing for transmission on a digital signal and transmits the processed digital signal via a communication line.
A main arithmetic processing circuit and a dedicated arithmetic processing circuit connected to the main arithmetic processing circuit are provided. The first digital signal has a first word length and the second word length is longer than the first word length. A digital signal processing circuit for performing arithmetic processing for the transmission on each of the second digital signals,
The main arithmetic processing circuit includes:
A main arithmetic unit having an arithmetic processing function corresponding to the first word length;
A first memory having a storage capacity of a unit storage area corresponding to the first word length;
When storing the first digital signal in the first memory, the one word length is stored in the unit storage area of the first memory, and when storing the second digital signal, the first digital signal is stored. Digital signal storage control means for dividing and storing one word length across a plurality of unit storage areas of the first memory;
Of the first and second digital signals stored in the first memory, the first digital signal is supplied to the main arithmetic unit to perform arithmetic processing, and the second digital signal is used as the dedicated digital signal. Arithmetic control means for transferring to the arithmetic processing circuit,
The dedicated arithmetic processing circuit is
A dedicated arithmetic unit having an arithmetic processing function corresponding to the second word length;
Dedicated arithmetic control means for supplying the second digital signal transferred from the main arithmetic processing circuit to the dedicated arithmetic unit to perform arithmetic processing, and transferring the arithmetic processing result to the main arithmetic processing circuit;
The storage capacity of the unit storage area is configured to correspond to the second word length, and temporarily holds the second digital signal transferred from the main arithmetic processing circuit and the arithmetic processing result obtained by the dedicated arithmetic unit. A communication apparatus comprising a digital signal processing circuit, comprising: a second data memory.

Images