JP2002073586A - Arithmetic processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the product-sum operation of a real number and the multiplication/product-sum operation of a complex number in an arithmetic processing device provided with at least four product-sum operation units. SOLUTION: An adder 31 adds the contents of accumulators 33 and 36 with respect to a product-sum operation results stored in the accumulators 33 to 36 through a selector 40. The added result and the content of the accumulator 34 are added through selectors 38 and 39 by an adder/subtracter 30. The added result and the content of the accumulator 33 are added by an adder 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing unit suitable for use in a digital signal processor or a microprocessor.

[0002]

2. Description of the Related Art In recent years, microprocessors such as a digital signal processor (hereinafter abbreviated as DSP) and a microcomputer having a multimedia processing function have been developed, for example, in accordance with the digitization movement in the field of mobile communication, for example, portable telephones. It is often used as a processor built into devices. As the demand for multimedia data communication increases in these microprocessors, an increase in processing power is increasingly required.

In order to improve the processing performance of the microprocessor as described above, multiply-accumulate operations are performed in parallel, or complex multiplication and complex multiply-accumulate operations are efficiently executed.
It is necessary to speed up the processing.

[0004] As a conventional technique, for example, Japanese Patent Laid-Open No. 3-21
Japanese Patent Application Laid-Open No. 1604 discloses a digital signal processing device capable of performing parallel operations by connecting four product-sum operators in parallel. Further, for example, Japanese Patent Application Laid-Open No.
The publication discloses an arithmetic device that can provide two multipliers and perform complex number multiplication in two steps.

[0005]

However, the conventional arithmetic processing device has the following problems.

That is, in the digital signal processor disclosed in Japanese Patent Application Laid-Open No. 3-221604, common data is input to the inputs of the four sum-of-products arithmetic units, and the four products-sum arithmetic units are internally provided. It is configured such that different coefficient data can be summed up to obtain four sum-of-products calculation results in parallel. However, in this digital signal processing apparatus, when there are two to four product-sum operations that can be executed simultaneously, the processing can be performed in parallel to speed up the processing.
When only one product-sum operation can be performed at the same time, parallel operation cannot be performed, and it is difficult to achieve high-speed processing.

In the arithmetic device disclosed in Japanese Patent Application Laid-Open No. 5-174049, the operation speed of the complex multiplication is not sufficiently increased, and a complex multiply-accumulate operation for accumulating and adding the result of the complex multiplication is performed. No means are described.

The present invention has been made in view of the above points, and is an arithmetic processing device capable of performing parallel arithmetic even when only one desired product-sum operation is performed, and capable of performing complex number multiplication at high speed. The purpose is to provide.

[0009]

According to the present invention, there is provided an arithmetic processing unit which adds a multiplier for multiplying two data, an output of the multiplier and an output of an accumulator in which initial value data is set to 0. Parallel operation processing means comprising at least four product-sum operation units having an adder for storing the result in the accumulator in parallel, and m-th (m is 2 ≦ m ≦ n (m n is an integer of 4 or more)
A selecting means for selecting one of the output of the accumulator and the output of the (m-1) -th multiplier and outputting the selected output to the (m-1) -th adder.

According to this configuration, even if only one product-sum operation can be performed at the same time, by performing the product-sum operation in parallel, the processing can be speeded up without increasing the operation clock. Therefore, when the arithmetic processing unit of the present invention is realized by a semiconductor device, it can be operated at a low power supply voltage, and low power consumption can be achieved.

The arithmetic processing unit according to the present invention is the arithmetic processing unit according to the second aspect, further comprising an adder / subtractor instead of an adder, and the output of the k-th (k is a multiple of 2) accumulator. A configuration is provided that includes second selection means for selecting one of the outputs of the (k-1) th multiplier and outputting the selected output to the kth adder or the adder / subtractor.

According to this configuration, even when only one product-sum operation can be performed at the same time, not only the product-sum operation can be performed in parallel, but also complex multiplication and complex product-sum operation can be performed at high speed.

The arithmetic processing device of the present invention further comprises a multiplier for multiplying the two data, an output of the multiplier and an output of an accumulator in which initial value data is set to 0, and the result is added to the result. A first multiply-accumulate unit having an adder stored in an accumulator, a multiplier for multiplying two data, and an output of the multiplier and an output of an accumulator in which initial value data is set to 0 And a second sum-of-products unit having an adder-subtractor for storing the result in the accumulator. At least four second sum-of-products units are connected in parallel with the second sum-of-products unit being positioned second. A k-th (k is a multiple of 2) accumulator output and / or a (k-1) -th multiplier output of the parallel operation processing means. Output to the adder or adder / subtractor It adopts a configuration comprising a selection means that, the.

According to this configuration, not only the product-sum operation but also the complex number multiplication can be performed at high speed.

Further, the arithmetic processing device of the present invention is characterized in that
In the arithmetic processing device having the sum-of-products arithmetic unit, one of the output of the k-th accumulator and the output of the (k-1) -th multiplier is selected and output to the (k-1) -th adder. A configuration having two selection means is adopted.

According to this configuration, not only the product-sum operation but also the complex-number product-sum operation can be performed at high speed.

A microprocessor according to the present invention employs a configuration including the arithmetic processing unit. By including the arithmetic processing unit, it is possible to execute a product-sum operation, a complex number multiplication, and a complex number product-sum operation at high speed.

A microprocessor according to the present invention further comprises an arithmetic processing unit having the same function as the arithmetic processing unit, a baseband for demodulating and decoding a received modulation signal, and encoding and modulating a transmission signal. And a signal processing means. By providing an arithmetic processing unit having the same function as that of the arithmetic processing device, the product-sum operation, the complex multiplication, and the complex product-sum operation can be executed at a high speed, so that the performance of the applied device can be improved. In addition, since high-speed processing can be performed, the number of mounted microprocessors in an applied device can be reduced, and thus cost can be reduced.

In the microprocessor according to the present invention, the baseband signal processing means performs modulation and demodulation in a CDMA communication system.

A radio station apparatus according to the present invention employs a configuration including the microprocessor. By providing the microprocessor, the performance of the device can be improved. Further, since high-speed processing can be performed, if the functions are the same as those in the related art, the number of mounted microprocessors can be reduced, and the cost can be reduced.

Further, the radio station apparatus of the present invention employs a configuration including voice-to-electric conversion means for converting voice into an electric signal and electric-voice conversion means for converting an electric signal into voice.

Further, the radio station device of the present invention is a radio base station.

Further, the radio station device according to the present invention is a mobile station device.

The recording medium of the present invention stores data obtained by programming the functions of the arithmetic processing unit.
By using the recording medium, it is possible to use any device that performs a product-sum operation, a complex multiplication, and a complex product-sum operation in a device using a macro processor,
Performance can be improved by increasing the processing speed. Examples of the recording medium include a magnetic disk, a magneto-optical disk, and a ROM cartridge.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention is that a multiplier for multiplying two data, an output of the multiplier and an output of an accumulator in which initial value data is set to 0 are added, and the result is accumulated in the accumulator. And a sum-of-products arithmetic unit having an adder for storing the sum-of-products.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration example of an arithmetic processing unit according to Embodiment 1 of the present invention.

In this figure, the arithmetic processing unit according to the present embodiment comprises memories 1 to 8, registers 9 to 16,
7 to 24, multipliers 25 to 28, adders 29 and 31,
32, an adder / subtractor 30, and accumulators 33 to 36
, Selectors 37 to 45, and a bus 46.

The memories 1 to 8 store data to be operated. The registers 9 to 16 temporarily store the data read from the memories 1 to 8 and output the data. Bus 17-24
Transfers the data output from the registers 9 to 16. Multiplier (MUL, called first multiplier) 25
Performs multiplication of data transferred on the buses 17 and 19. Multiplier (MUL, called second multiplier) 26
Performs multiplication of data transferred on the bus 18 and data transferred on the bus 20.

The selector 42 selects and outputs one of the data transferred on the bus 18 and the data transferred on the bus 21. The selector 43 selects and outputs one of the data transferred on the bus 19 and the data transferred on the bus 22. A multiplier (MUL, a third multiplier) 27 multiplies data output from the selector 42 by data output from the selector 43. The selector 44 selects and outputs one of the data transferred on the bus 17 and the data transferred on the bus 23. The selector 45 selects and outputs one of the data transferred on the bus 20 and the data transferred on the bus 24.

A multiplier (MUL, a fourth multiplier) 28 multiplies the data output from the selector 44 by the data output from the selector 45. The selector 37 is one of selectors as selection means or second selection means, and selects one of the output of the first multiplier 25 and the output of the second accumulator (ACC) 34. Output. The selector 38 is one of selectors as second selection means or selection means, and selects and outputs one of the output of the first multiplier 25 and the output of the second accumulator 34.

The selector 39 is one of the selecting means.
The output of the second multiplier 26 and the third accumulator 3
5 is selected and output. The selector 40 is one of selectors as selection means or second selection means, and selects and outputs one of the output of the third multiplier 27 and the output of the fourth accumulator 36. The selector 41 is one of the selectors as the second selector, and selects and outputs one of the output of the third multiplier 27 and the output of the fourth accumulator.

The first adder 29 stores the data selected by the selector 37 and the first accumulator 3
3 and the accumulated data. The adder / subtractor 30
A second adder or an adder / subtracter as an adder / subtractor, adds or subtracts data selected by the selector 38 and data selected by the selector 39.
The adder 31 is a third adder, and adds the data stored in the third accumulator 35 and the data selected by the selector 40. The adder 32 is a fourth adder, and adds the data selected by the selector 41 and the data output from the fourth multiplier 28.

The accumulators 33 to 36 are the first to fourth accumulators, and include the adder 29 and the adder / subtractor 3
0, stores data output from the adders 31 and 32. The bus 46 transfers data output from the accumulators 33 to 36 to the memories 1 to 8.

(First Operation Example) Next, in the arithmetic processing unit having the above configuration, the product-sum operation Z = Σ (Xi × Yi), (i =
The operation in the case of performing 0 to 15) will be described step by step. In this operation example, the adder / subtractor 30 operates as an adder. In addition, accumulators 33 to 3
It is assumed that 6 has been reset to 0 in advance. The memories 1 to 8 store data as shown in FIG.

(1) Eight data {X0, X4, Y0, Y4, X8, Y8, X1 read from memories 1 to 8
2, Y12} are stored in registers 9 to 16. The multiplier 25 multiplies the data X0 and Y0 read from the registers 9 and 11 via the buses 17 and 19, respectively. The selector 37 selects and outputs the output of the multiplier 25. The adder 29 adds the output of the selector 37 and the output of the accumulator 33 and stores the result in the accumulator 33.

The multiplier 26 multiplies the data X4 and Y4 read from the registers 10 and 12 via the buses 18 and 20, respectively. The selector 38 selects and outputs the output of the accumulator 34. The selector 39 selects and outputs the output of the multiplier 26. The adder / subtractor 30 is connected to the selector 3
The outputs of 8 and 39 are added and stored in the accumulator 34. The selector 42 selects and outputs the data X8 read from the register 13 via the bus 21.

The selector 43 sends the signal from the register 14 to the bus 2
2 and selects and outputs the data Y8 read out.
The multiplier 27 outputs the data X output from the selectors 42 and 43.
8 is multiplied by Y8. The selector 40 selects and outputs the output of the multiplier 27. The adder 31 adds the output of the accumulator 35 and the output of the selector 40 and stores the result in the accumulator 35. The selector 44 selects the register 1
5 to select and output the data X12 read via the bus 23.

The selector 45 sends the signal from the register 16 to the bus 2
4 to select and output the read data Y12. The multiplier 28 multiplies the data X12 and the data Y12 output from the selectors 44 and 45. The selector 41 selects and outputs the output of the accumulator 36. The adder 32 adds the output of the accumulator 36 and the output of the multiplier 28 and stores the result in the accumulator 36. At this time, the accumulators 33 to 36
{X0 × Y0}, {X4 × Y4}, {X8 × Y8},
The result of {X12 × Y12} is stored.

(2) Eight data {X1, X5, Y1, Y5, X9, Y9, X1 read from memories 1 to 8
3, Y13} are stored in registers 9-16. The multiplier 25 multiplies the data X1 and the data Y1 read from the registers 9 and 11 via the buses 17 and 19, respectively. The selector 37 selects and outputs the output of the multiplier 25.
The adder 29 is provided between the output of the selector 37 and the accumulator 3.
3 are added and stored in the accumulator 33.

The multiplier 26 stores the data X5 and the data Y read from the registers 10 and 12 via the buses 18 and 20.
Multiply by 5. The selector 38 is connected to the accumulator 3
4 is selected and output. The selector 39 selects and outputs the output of the multiplier 26. The adder / subtractor 30 adds the outputs of the selectors 38 and 39 and stores the result in the accumulator 34. The selector 42 is connected to the bus 21 from the register 13.
, And selects and outputs the read data X9. The selector 43 selects and outputs the data Y9 read from the register 14 via the bus 22.

The multiplier 27 multiplies the data X9 and Y9 output from the selectors 42 and 43. The selector 40 is
The output of the multiplier 27 is selected and output. The adder 31
The output of the accumulator 35 and the output of the selector 40 are added and stored in the accumulator 35. Selector 44
Selects and outputs the data X13 read from the register 15 via the bus 23. The selector 45 selects and outputs the data Y13 read from the register 16 via the bus 24.

The multiplier 28 multiplies the data X13 and Y13 output from the selectors 44 and 45. Selector 41
Selects the output of the accumulator 36 and outputs it. The adder 31 adds the output of the accumulator 36 and the output of the multiplier 28 and stores the result in the accumulator 36. At this time, the accumulators 33 to 36 are sequentially given ｛Σ (Xi
× Yi), (i = 0, 1)｝, ｛Σ (Xi × Yi), (i
= 4,5)｝, {(Xi × Yi), (i = 8,9)},
The result of {(Xi × Yi), (i = 12, 13)} is stored.

(3) Eight data {X2, X6, Y2, Y6, X10, Y10,
X14, Y14} are stored in registers 9-16. The multiplier 25 multiplies the data X2 and Y2 read from the registers 9 and 11 via the buses 17 and 19, respectively. The selector 37 selects and outputs the output of the multiplier 25. The adder 29 is provided between the output of the selector 37 and the accumulator 33.
Are added and stored in the accumulator 33. The multiplier 26 multiplies the data X6 and the data Y6 read from the registers 10 and 12 via the buses 18 and 20.

The selector 38 selects and outputs the output of the accumulator 34. The selector 39 selects and outputs the output of the multiplier 26. The adder / subtractor 30 is connected to the selector 3
8 and the output of the selector 39 are added and the accumulator 34
To be stored. The selector 42 outputs the signal from the register 13 to the bus 2
1 to select and output the data X10 read out. The selector 43 selects and outputs the data Y10 read from the register 14 via the bus 22.

The multiplier 27 multiplies the data X10 output from the selectors 42 and 43 by the data Y10. The selector 40 selects and outputs the output of the multiplier 27. The adder 31 adds the output of the accumulator 35 and the output of the selector 40 and stores the result in the accumulator 35. The selector 44 selects and outputs the data X14 read from the register 15 via the bus 23. Selector 45
Selects and outputs the data Y14 read from the register 16 via the bus 24.

The multiplier 28 multiplies the data X14 and Y14 output from the selectors 44 and 45. Selector 41
Selects the output of the accumulator 36 and outputs it. The adder 31 adds the output of the accumulator 36 and the output of the multiplier 28 and stores the result in the accumulator 36. At this time, the accumulators 33 to 36 sequentially output ｛Σ (Xi ×
Yi), (i = 0 to 2)｝, ｛Σ (Xi × Yi), (i =
4-6)｝, {(Xi × Yi), (i = 8-10)},
The result of {(Xi × Yi), (i = 12 to 14)} is stored.

(4) Eight data {X3, X7, Y3, Y7, X11, Y11,
X15, Y15} are stored in the registers 9 to 16. The multiplier 25 multiplies the data X3 and the data Y3 read from the registers 9 and 11 via the buses 17 and 19, respectively.
The selector 37 selects and outputs the output of the multiplier 25. The adder 29 adds the output of the selector 37 and the output of the accumulator 33 and stores the result in the accumulator 33.

The multiplier 26 stores data X7 and data Y read from the registers 10 and 12 via the buses 18 and 20.
Multiply by 7. The selector 38 is connected to the accumulator 3
4 is selected and output. The selector 39 selects and outputs the output of the multiplier 26. The adder / subtractor 30 adds the outputs of the selectors 38 and 39 and stores the result in the accumulator 34. The selector 42 is connected to the bus 21 from the register 13.
, And selects and outputs the read data X11.

The selector 43 sends a signal from the register 14 to the bus 2
2 to select and output the read data Y11. The multiplier 27 multiplies the data X11 and Y11 output from the selectors 42 and 43. The selector 40 selects and outputs the output of the multiplier 27. The adder 31 adds the output of the accumulator 35 and the output of the selector 40 and stores the result in the accumulator 35.

The selector 44 sends a signal from the register 15 to the bus 2
3, and selects and outputs the data X15 read out. The selector 45 selects and outputs the data Y15 read from the register 16 via the bus 24. The multiplier 28 outputs the data X15 output from the selectors 44 and 45,
Y15 is multiplied. The selector 41 selects and outputs the output of the accumulator 36.

The adder 31 adds the output of the accumulator 36 and the output of the multiplier 28 and stores the result in the accumulator 36. At this time, the accumulators 33 to 36 sequentially have {(Xi × Yi), (i = 0 to 3)} and ｛Σ (Xi
× Yi), (i = 4-7)｝, ｛Σ (Xi × Yi), (i
= 8-11)｝, ｛Σ (Xi × Yi), (i = 12-1)
5) The result of｝ is stored.

(5) The selector 40 is the accumulator 3
6 is selected and output. The adder 31 adds the output of the accumulator 35 and the output of the selector 40 and stores the result in the accumulator 35. At this point, the result of {(Xi × Yi), (i = 8 to 15)} is stored in the accumulator 35.

(6) The selector 39 is connected to the accumulator 3
5 is selected and output. The selector 38 selects and outputs the output of the accumulator 34. Adder / subtractor 30
Add the outputs of the selectors 38 and 39 and store the sum in the accumulator 34. At this point, the accumulator 34 stores the result of {(Xi × Yi), (i = 4 to 15)}.

(7) The selector 37 is the accumulator 3
4 is selected and output. The adder 29 adds the output of the accumulator 33 and the output of the selector 37, and provides the accumulator 33 with ｛Σ (Xi × Yi), (i = 0 to 1).
5) The result of｝ is stored.

By the above operation, the product-sum operation Z = Σ
The result of (Xi × Yi) (i = 0 to 15) can be obtained in seven steps. In the above operation example, the product-sum operation for cumulatively adding 16 multiplication results has been described. In general, the product-sum operation for cumulatively adding n multiplication results is (n / 4 +
3) The result can be obtained in steps.

As described above, even when only one product-sum operation can be performed at the same time, the product-sum operation can be performed in parallel, and the processing speed can be increased. In addition, since the operation speed can be increased without increasing the operation clock by the parallel operation, when the operation processing device is realized by a semiconductor device, it can be operated with a lower power supply voltage than the conventional operation processing device, and the power consumption of the device is reduced. The effect that power can be achieved is also obtained.

(Second Operation Example) Hereinafter, in the arithmetic processing unit of FIG. 1, a complex number multiplication (A0 + jB0) (C0 + jD
0) = (A0C0−B0D0) + j (B0C0 + A0D
The operation when (0) is performed will be described step by step. In this operation example, the adder / subtractor 30 operates as a subtractor. It is assumed that the accumulators 33 to 36 have been reset to 0 in advance. In addition, the memories 1 to 4 store data as shown in FIG.

The four data {A0, B0, C0, D0} read from the memories 1 to 4 are stored in the registers 9 to 12. Multiplier 25 is connected to buses 17,
The multiplication of the data A0 and C0 read via the line 19 is performed. Multiplier 26 is connected to buses 18 from registers 10 and 12,
Multiplication of the data B0 and D0 read out via 20 is performed.

The selector 38 selects and outputs the output of the multiplier 25. The selector 39 selects and outputs the output of the multiplier 26. The adder / subtractor 30 subtracts the output of the selector 39 from the output of the selector 38 and stores the result in the accumulator 34. The selector 42 selects and outputs the data B0 read from the register 10 via the bus 18. The selector 43 selects and outputs the data C0 read from the register 11 via the bus 19.

The multiplier 27 multiplies the data B0 output from the selectors 42 and 43 by the data C0. Selector 4
4 selects and outputs the data A0 read from the register 9 via the bus 17. The selector 45 selects and outputs the data D0 read from the register 12 via the bus 20. The multiplier 28 multiplies the data A0 output from the selectors 44 and 45 by the data D0.

The selector 41 selects and outputs the output of the multiplier 27. The adder 31 adds the output of the selector 41 and the output of the multiplier 28 and stores the result in the accumulator 36. At this point, the accumulators 34 and 36 have ｛A
0C0-B0D0} and {B0C0 + A0D0} are stored.

With the above operation, complex number multiplication (A
0 + jB0) (C0 + jD0) = (A0C0−B0D)
0) + j (B0C0 + A0D0) can be obtained in one step.

As described above, even when only one product-sum operation can be performed at the same time, the product-sum operation can be performed in parallel to increase the processing speed, and the result of complex number multiplication can be performed in one step. The effect that can not be obtained in the conventional example can be obtained. In addition, since the operation speed can be increased without increasing the operation clock by the parallel operation, when the operation processing device is realized by a semiconductor device, the operation processing device can be operated with a lower power supply voltage than before, and the power consumption of the device can be reduced. The effect is also obtained.

(Third Operation Example) Hereinafter, in the arithmetic processing device of FIG. 1, a complex multiplication product-sum operation Σ (Ai + jBi)
(Ci + jDi) = {(AiCi-BiDi) + j}
The operation when (BiCi + AiDi) and (i = 0 to 3) are performed will be described step by step. In this operation example, the adder / subtractor 30 operates as a subtractor. In addition,
It is assumed that the accumulators 33 to 36 have been reset to 0 in advance. The memories 1 to 4 store data as shown in FIG.

(1) The four data {A0, B0, C0, D0} read from the memories 1 to 4 are stored in the registers 9 to 12.
To be stored. The multiplier 25 includes the register 9 and the register 11
Are multiplied by the data A0 and the data C0 read out from the bus via the buses 17 and 19. The multiplier 26 is provided in the register 10
And data D0 read from the register 12 via the bus 18 and the bus 20 and the data D0. The selector 38 selects and outputs the output of the multiplier 25. The selector 39 selects and outputs the output of the multiplier 26.

The adder / subtractor 30 subtracts the output of the selector 39 from the output of the selector 38 and stores the result in the accumulator 34. The selector 42 selects and outputs the data B0 read from the register 10 via the bus 18. The selector 43 selects and outputs the data C0 read from the register 11 via the bus 19.

The multiplier 27 includes a selector 42 and a selector 43
Is multiplied by the data B0 and the data C0 output by. The selector 44 selects and outputs the data A0 read from the register 9 via the bus 17. The selector 45 outputs the data D0 read from the register 12 via the bus 20.
Select and output. The multiplier 28 multiplies the data A0 and the data D0 output from the selectors 44 and 45.

The selector 41 selects and outputs the output of the multiplier 27. The adder 31 adds the output of the selector 41 and the output of the multiplier 28 and stores the result in the accumulator 36. At this point, the accumulator contains 0, ｛A0C0-
The result of B0D0, 0, {B0C0 + A0D0} is stored.

(2) The four data {A1, B1, C1, D1} read from the memories 1-4 are stored in the registers 9-12.
To be stored. The multiplier 25 includes the register 9 and the register 11
A1 read out from the bus 17 via the bus 17 and the bus 19
And the data C1 are multiplied. The multiplier 26 multiplies data B1 and data D1 read from the registers 10 and 12 via the buses 18 and 20. The selector 37 selects and outputs the output of the accumulator 34. The adder 29 adds the output of the selector 37 and the output of the accumulator 33 and stores the result in the accumulator 33.

The multiplier 26 includes the register 10 and the register 1
Data B read from the bus 2 via the bus 18 and the bus 20
1 is multiplied by the data D1. The selector 38 selects and outputs the output of the multiplier 25. The selector 39 selects and outputs the output of the multiplier 26.

The adder / subtractor 30 subtracts the output of the selector 39 from the output of the selector 38 and stores the result in the accumulator 34. The selector 42 selects and outputs the data B1 read from the register 10 via the bus 18. The selector 43 selects and outputs the data C1 read from the register 11 via the bus 19. Multiplier 27 multiplies data B1 and data C1 output from selectors 42 and 43.

The selector 40 selects and outputs the output of the accumulator 36. The adder 31 includes the accumulator 3
5 is added to the output of the selector 40 and stored in the accumulator 35. The selector 44 selects and outputs the data A1 read from the register 9 via the bus 17. The selector 45 selects and outputs the data D1 read from the register 12 via the bus 20.

The multiplier 28 includes a selector 44 and a selector 45
Is multiplied by the data A1 and the data D1 output by. The selector 41 selects and outputs the output of the multiplier 27. The adder 31 adds the output of the selector 41 and the output of the multiplier 28 and stores the result in the accumulator 36. At this point, the accumulators 33 to 36 have ｛Σ (AiCi-BiD
i), (i = 0)}, {A1C1-B1D1},
(BiCi + AiDi)｝, (i = 0)｝, {B1C1
+ A1D1} is stored.

(3) The four data {A2, B2, C2, D2} read from the memories 1 to 4 are stored in the registers 9 to 12
To be stored. The multiplier 25 includes the register 9 and the register 11
A2 read from the bus 17 via the bus 17 and the bus 19
And the data C2. The multiplier 26 multiplies the data B2 and the data D2 read from the registers 10 and 12 via the buses 18 and 20. The selector 37 selects and outputs the output of the accumulator 34. The adder 29 adds the output of the selector 37 and the output of the accumulator 33 and stores the result in the accumulator 33.

The multiplier 26 includes the register 10 and the register 1
Data B read from the bus 2 via the bus 18 and the bus 20
2 is multiplied by the data D2. The selector 38 selects and outputs the output of the multiplier 25. The selector 39 selects and outputs the output of the multiplier 26. The adder / subtractor 30 subtracts the output of the selector 39 from the output of the selector 38 and stores the result in the accumulator 34. The selector 42 selects and outputs the data B2 read from the register 10 via the bus 18.

The selector 43 sends the signal from the register 11 to the bus 1
9 and outputs the selected data C2.
The multiplier 27 multiplies the data B2 and the data C2 output from the selectors 42 and 43. The selector 40 selects and outputs the output of the accumulator 36. Adder 3
1 adds the output of the accumulator 35 and the output of the selector 40 and stores the result in the accumulator 35. The selector 44 selects and outputs the data A2 read from the register 9 via the bus 17.

The selector 45 sends a signal from the register 12 to the bus 2
And selects and outputs the data D2 read via the "0".
The multiplier 28 multiplies the data A2 and the data D2 output from the selectors 44 and 45. The selector 41 selects and outputs the output of the multiplier 27. The adder 31 adds the output of the selector 41 and the output of the multiplier 28 and stores the result in the accumulator 36. At this time, the accumulators 33 to 36 have ｛Σ (AiCi-BiDi), (i =
0, 1)}, {A2C2-B2D2}, {(BiCi
+ AiDi)｝, (i = 0, 1)｝, {B2C2 + A2
D2} is stored.

(4) The four data {A3, B3, C3, D3} read from the memories 1-4 are stored in the registers 9-12.
To be stored. The multiplier 25 includes the register 9 and the register 11
A3 read from the bus 17 via the bus 17 and the bus 19
And the data C3. The multiplier 26 multiplies data B3 and data D3 read from the registers 10 and 12 via the buses 18 and 20. The selector 37 selects and outputs the output of the accumulator 34. The adder 29 adds the output of the selector 37 and the output of the accumulator 33 and stores the result in the accumulator 33.

The multiplier 26 includes the register 10 and the register 1
Data B read from the bus 2 via the bus 18 and the bus 20
3 and data D3. The selector 38 selects and outputs the output of the multiplier 25. The selector 39 selects and outputs the output of the multiplier 26. The adder / subtractor 30 subtracts the output of the selector 39 from the output of the selector 38 and stores the result in the accumulator 34. The selector 42 selects and outputs the data B3 read from the register 10 via the bus 18.

The selector 43 sends a signal from the register 11 to the bus 1
9 to select and output the read data C3.
The multiplier 27 outputs the data B3 output from the selectors 42 and 43.
And data C3. The selector 40 selects and outputs the output of the accumulator 36. The adder 31 adds the output of the accumulator 35 and the output of the selector 40 and stores the result in the accumulator 35.

The selector 44 operates from the register 9 to the bus 17
, And selects and outputs the data A3 read out. The selector 45 selects and outputs the data D3 read from the register 12 via the bus 20. The multiplier 28 multiplies the data A3 output from the selectors 44 and 45 by the data D3. The selector 41 selects and outputs the output of the multiplier 27.

The adder 31 adds the output of the selector 41 and the output of the multiplier 28 and stores the result in the accumulator 36. At this time, the accumulators 33 to 36 have ｛Σ
(AiCi-BiDi), (i = 0-2)}, {A3C
3-B3D3}, {(BiCi + AiDi)}, (i
= 0 to 2)} and {B3C3 + A3D3} are stored.

(5) The selector 37 is the accumulator 34
Select the output and output. The adder 29 is a selector 37
And the output of the accumulator 33 are added and stored in the accumulator 33. The selector 40 selects and outputs the output of the accumulator 36.

The adder 31 adds the output of the accumulator 35 and the output of the selector 40, and
To be stored. At this time, the accumulator 33 stores the real part ｛Σ (AiCi-BiDi) of the complex number product-sum operation result,
(I = 0-3)} is stored, and the accumulator 3
3 has an imaginary part ｛Σ (BiCi + A
iDi) {, (i = 0-3)} are stored.

With the above operation, the complex number multiply-accumulate operation Σ (Ai + jBi) (Ci + jDi) = Σ (AiC
(i-BiDi) + jΣ (BiCi + AiDi), (i =
The results of 0 to 3) can be obtained in 5 steps. In the above operation example, the complex number product-sum operation for cumulatively adding the four complex number multiplication results is described. However, in general, the complex number product-sum operation for cumulatively adding n complex number multiplication results is (n + 1)
The results can be determined in steps.

As described above, even when only one product-sum operation can be performed at the same time, the product-sum operation can be performed in parallel and the processing speed can be increased. This is an effect which cannot be obtained in the conventional example. Since the operation speed can be increased without increasing the operation clock by the parallel operation, when this operation processing device is realized by a semiconductor device, it can be operated with a lower power supply voltage than before, and the effect of reducing the power consumption of the device is also achieved. can get.

(Embodiment 2) In Embodiment 2, a DSP provided with the arithmetic processing unit of Embodiment 1 will be described. The DSP is a one-chip microprocessor dedicated to digital signal processing. DS of this embodiment
In P60, as shown in FIG.
An input / output unit 62 for inputting / outputting data to / from the outside, a control unit 63 for controlling the arithmetic processing unit 61 and the input / output unit 62,
A memory 64 for supplying an instruction to the control unit is provided in one chip.

As described above, if the instruction sequence for controlling the arithmetic processing unit according to the first embodiment is stored in a storage medium such as the memory 64 and executed by the DSP 60, the sum of products which can be calculated simultaneously can be obtained. Even in the case of only one operation, by performing the multiply-accumulate operation in parallel, the processing can be speeded up, and the result of complex multiplication or complex multiply-accumulate operation can not be obtained at high speed. The effect is obtained. Since the operation speed can be increased without increasing the operation clock by the parallel operation, when the DSP 60 is realized by a semiconductor device, the DSP 60 can be operated with a lower power supply voltage than before, and the effect of reducing the power consumption of the device is also obtained. Can be

(Embodiment 3) In Embodiment 3, DS
A wireless mobile station incorporating P will be described.

As shown in FIG. 6, this radio mobile station apparatus 7
00 is an antenna unit 710 for both transmission and reception, and a reception unit 72
1; a radio unit 720 including a transmission unit 722; a baseband processing unit 730 that performs modulation and demodulation and encoding and decoding of a signal; a speaker 751 that emits sound; a microphone 752 that inputs sound; A data input / output unit 753 for inputting / outputting data to be transmitted / received to / from an external device; a display unit 754 for displaying an operation state;
5 and a control unit 760 for controlling the antenna unit 710, the radio unit 720, the baseband signal processing unit 730, the display unit 754, the operation unit 755, and the like.

Further, the baseband signal processing section 730
The demodulation unit 731 demodulates a received signal, the modulation unit 735 modulates a transmission signal, and a one-chip DSP 740. The DSP 740 includes the arithmetic processing unit according to the first embodiment. 743, an audio codec unit 744 that performs codec decoding of the audio signal, and transmits the received signal from the demodulation unit 731 to the error correction decoding unit 742 while measuring the transmission and reception timing, while transmitting the transmission signal to the error correction encoding unit 74.
3 and a timing control unit 741 sent to the modulation unit 735 are realized by software.

Control section 760 of radio mobile station apparatus 700
Controls the operation of the entire wireless mobile station device 700, for example, to display a signal input from the operation unit 755 on the display unit 754, or to perform an incoming / outgoing call operation by receiving a signal input from the operation unit 755. The control signal is output to the antenna unit 710, the radio unit 720, the baseband signal processing unit 730, and the like according to the communication sequence.

When voice is transmitted from radio mobile station apparatus 700, voice signal input from microphone 752 is
D-converted (not shown) and the codec unit 7 of the DSP 740
44, and the coded data is input to the error correction coding unit 743. When data is transmitted, data input from outside is transmitted to the data input / output unit 753.
Is input to the error correction coding unit 743 via the. The error correction coding unit 743 performs error correction coding on the input data, and outputs the data to the timing control unit 741.

[0095] Timing control section 741 rearranges the input data and adjusts the transmission output timing, and outputs the result to modulation section 735.

The data input to the modulation section 735 is digitally modulated and D / A converted (not shown).
Is output to the transmission unit 722 of Transmitting section 722 converts this into a radio signal, sends it to antenna section 710, and transmits it as a radio wave from the antenna.

On the other hand, at the time of reception, a radio wave received by the antenna unit 710 is received by the reception unit 721 of the radio unit 720, subjected to A / D conversion, and output to the demodulation unit 731 of the baseband signal processing unit 730. The data demodulated by the demodulation unit 731 is input to the error correction decoding unit 742 after the data is rearranged by the timing control unit 741, and is decoded here.

The data decoded by the error correction decoding unit 742 is as follows. At the time of voice communication, voice is decoded by the voice codec unit 744, DA-converted, and then output from the speaker 751 as voice. During data communication, the data decoded by the error correction decoding unit 742 is transmitted to the data input / output unit 7.
It is output to the outside via 53.

FIG. 7 shows a CDMA system in which the configuration of the radio mobile station apparatus shown in FIG. 6 is partially changed, in which a spreading section 737 is provided in modulation section 735A and a despreading section 733 is provided in demodulation section 731A.
2 shows a wireless mobile station device of a communication system. This device can perform CDMA communication by including the spreading unit 737 and the despreading unit 733.

As described above, in the radio mobile station apparatuses 700 and 700A, the error correction decoding unit 742, the error correction encoding unit 743, the audio codec unit 744, and the timing control unit 741 are formed by the software of the one-chip DSP 740. As a result, it can be assembled with a small number of parts. In addition, an effect which cannot be achieved by a conventional example that the baseband signal processing unit can be more effectively reduced in power consumption at low cost can be obtained.

Note that, also here, the demodulation units 731 and 731A
And the modulation units 735 and 735A can be constituted by software of the DSP 740. The DSP of the second embodiment is used as the DSP, and the error correction encoding unit 74
3 and the timing control unit 741 can also be configured as separate components.

(Embodiment 4) In Embodiment 4, a radio base station apparatus incorporating a DSP for performing error correction coding will be described.

As shown in FIG. 8, radio base station apparatus 800
Is an antenna unit 810 having a transmitting antenna 812 and a receiving antenna 811, a receiving unit 821 and a transmitting unit 82
And a baseband signal processing unit 830 that performs modulation and demodulation, encoding and decoding of signals.
A data input / output unit 853 for inputting / outputting data to be transmitted / received to / from a wired line; an antenna unit 810;
0, and a control unit 860 that controls the baseband signal processing unit 830 and the like.

Further, the baseband signal processing section 830
A demodulation unit 831 for demodulating a reception signal, a modulation unit 835 for modulating a transmission signal, and a one-chip DSP 840 are provided. The DSP 840 includes the arithmetic processing unit according to the first embodiment, and performs error correction coding. A timing control unit 841 for transmitting a reception signal from the demodulation unit 831 to the error correction decoding unit 842 while measuring the timing of the voice signal and transmission / reception of the unit 843 and transmitting the transmission signal from the error correction encoding unit 843 to the modulation unit 835; Each is realized by software.

In the radio base station apparatus 800, the control unit 8
Transmission / reception operations are performed under the control of 60, and data input from a wired line is input to an error correction encoding unit 843 via a data input / output unit 853. The error correction coding unit 843 performs error correction coding on the input data,
Output to the timing control unit 841.

The timing control unit 841 rearranges the input data and adjusts the transmission output timing,
Output to the modulation unit 835. The data input to the modulation unit 835 is digitally modulated, D / A converted (not shown), and output to the transmission unit 822 of the wireless unit 820. The transmitting section 822 converts the signal into a radio signal and transmits the radio signal to the radio base station via the transmission antenna 812.

On the other hand, at the time of reception, the radio wave received by the receiving antenna 811 is received by the receiving unit 821 of the radio unit 820, and is subjected to A / D conversion to obtain the baseband signal processing unit 830.
Is output to the demodulation unit 831 of. The data demodulated by the demodulation unit 831 is input to the error correction decoding unit 842 after the data is rearranged by the timing control unit 841, and the like.
It is decrypted here. What is the data decoded by the error correction decoding unit 842? The data is output to a wired line via the data input / output unit 853.

FIG. 9 is a diagram showing a configuration in which a part of the configuration of radio base station apparatus 800 in FIG. 8 is modified to provide a spreading section 837 in modulation section 835A and a despreading section 833 in demodulation section 831A.
The figure shows a wireless base station device 800A of the DMA communication system. Since the radio base station apparatus 800A includes the spreading unit 837 and the despreading unit 833, CDMA communication can be performed.

As described above, in the radio base station apparatuses 800 and 800A, the error correction decoding unit 842, the error correction encoding unit 843, and the timing control unit 841 are formed by one-chip DSP 840 software. It can be assembled with a small number of parts. In addition, an effect which cannot be achieved by a conventional example that the baseband signal processing unit can be more effectively reduced in power consumption at low cost can be obtained.

Note that, also in the eighth embodiment, the demodulation unit 83
1, 831A and modulation sections 835, 835A
0 software, and
It is also possible to use the DSP of the second embodiment as a DSP, and configure the error correction encoding unit 843 and the timing control unit 841 as separate components.

[0111]

As described above, according to the present invention,
Even when only one product-sum operation can be performed at the same time, by performing the product-sum operation in parallel, not only can the processing be speeded up, but also the results of complex multiplication and complex product-sum operation can be obtained at high speed. The effect that cannot be obtained in the conventional example can be obtained. In addition, since the operation speed can be increased without increasing the operation clock by the parallel operation, the operation processing device can be operated at a lower power supply voltage than before when the operation processing device is realized by a semiconductor device. This has the effect of reducing power consumption of the utilization device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arithmetic processing device according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating a data arrangement in a memory of the arithmetic processing unit according to the first embodiment of the present invention;

FIG. 3 is a diagram illustrating a data arrangement in a memory of the arithmetic processing device according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating a data arrangement in a memory of the arithmetic processing unit according to the first embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a microprocessor device according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a radio mobile station apparatus according to Embodiment 3 of the present invention.

FIG. 7 is a block diagram showing a configuration of a radio mobile station apparatus according to Embodiment 3 of the present invention.

FIG. 8 is a block diagram showing a configuration of a radio base station apparatus according to Embodiment 4 of the present invention.

FIG. 9 is a block diagram showing a configuration of a radio base station apparatus according to Embodiment 4 of the present invention.

[Explanation of symbols]

 1 to 8 memory 9 to 16 register 17 to 24 bus 25 to 28 multiplier 29, 31, 32 adder 30 adder / subtractor 33 to 36 accumulator 37 to 45 selector 46 bus 60 DSP 700 wireless mobile station device 700A wireless mobile station device 800 Wireless base station device 800A Wireless base station device

Claims (12)

[Claims] 1. A multiplier for multiplying two data, and an adder for adding an output of the multiplier and an output of an accumulator in which initial value data is set to 0 and storing the result in the accumulator. Parallel operation processing means comprising at least four product-sum operation units provided in parallel, and m-th (m is 2 ≦ m ≦ n (n is 4
Selecting means for selecting one of the output of the integer) th accumulator and the output of the (m-1) th multiplier of the above (integer) and outputting the selected output to the (m-1) th adder. An arithmetic processing device characterized by the above-mentioned. 2. An apparatus according to claim 1, further comprising an adder / subtracter in place of the second adder, and one of an output of a k-th (k is a multiple of 2) accumulator and an output of a (k-1) -th multiplier. And a second selecting means for selecting the selected signal and outputting the selected signal to a k-th adder or an adder / subtractor.
An arithmetic processing unit according to any one of the preceding claims. 3. A multiplier that multiplies two data, and an adder that adds an output of the multiplier and an output of an accumulator whose initial value data is set to 0 and stores the result in the accumulator. A first sum-of-products arithmetic unit, 2
A second product comprising: a multiplier for multiplying the number of data; and an adder / subtracter for adding an output of the multiplier and an output of an accumulator in which initial value data is set to 0 and storing the result in the accumulator. A second calculator, and the second
And at least four of the sum-of-products arithmetic units are connected in parallel, and the output of the k-th (k is a multiple of 2) accumulator of the parallel arithmetic processing unit and k-th Selecting means for selecting any one of the outputs of the first multiplier and outputting the selected output to the k-th adder or adder / subtractor. 4. The output of the k-th accumulator and the k-th accumulator
-Select one of the outputs of the first multiplier to determine
4. The arithmetic processing device according to claim 3, further comprising a second selection unit that outputs the signal to the (-1) -th adder. 5. A microprocessor comprising the arithmetic processing device according to claim 1. Description: 6. An arithmetic processing unit having a function equivalent to that of the arithmetic processing device according to claim 1.
While demodulating and decoding the received modulated signal, baseband signal processing means for encoding and modulating the transmission signal,
A microprocessor comprising: 7. The baseband signal processing means includes:
7. The microprocessor according to claim 6, wherein modulation and demodulation of a communication method are performed. 8. A radio station device comprising the microprocessor according to claim 5. Description: 9. The apparatus according to claim 8, further comprising voice / electric conversion means for converting voice into an electric signal, and electric / voice conversion means for converting an electric signal into voice, and transmitting / receiving voice. Radio station equipment. 10. The radio station device according to claim 8, wherein the radio station device is a radio base station. 11. The radio station device according to claim 8, wherein the radio station device is a mobile station device. 12. A recording medium storing data obtained by programming the functions of the arithmetic processing device according to claim 1. Description: