JP3735219B2 - I / O buffer to reduce ringback effect - Google Patents

Description

[0001]
Background of the Invention
1. Field of the Invention The present invention relates to an input / output buffer that reduces the ringback effect specifically designed for use with a data transmission bus for transmitting high frequency, low amplitude data signals.
[0002]
2. 2. Description of Related Art Due to advances in semiconductor technology, today's integrated circuits are configured with higher power density and higher density with lower power consumption. As a result, data transmission buses that connect the various integrated circuits of a computer system must transmit high frequency, low amplitude data signals. An example of this type of data transmission bus is the GTL + bus.
[0003]
FIG. 1 is a circuit diagram showing a configuration of a conventional GTL + bus. As shown, the conventional GTL + bus includes a first GTL + input / output buffer IC1, a second GTL + input / output buffer IC2, a first transmission line 10, a second transmission line 12, and a termination resistor _rt1. (The resistance value is generally 50Ω). One terminal of the termination resistor r _t1 is connected to the system voltage V _tt and the other terminal is connected to the second transmission line 12. The other terminal of the second transmission line 12 is connected to both the IC 1 and the first transmission line 10. The other terminal of the first transmission line 10 is connected to IC2.
[0004]
When IC1 serves as an input terminal and IC2 serves as an output terminal, the ringback effect in the input / output buffer is not important. It IC1 input terminals is because in close proximity to the termination resistor r _t1. On the other hand, since there is no termination resistor close to IC2, when IC2 serves as an input terminal and IC1 serves as an output terminal, an undesired ringback effect at node 16 between IC2 and transmission line 10 is obvious.
[0005]
The ringback effect on the input data signal to IC2 at node 16 is illustrated in FIG. As shown here, when the input data signal switches from 1.5 V (high voltage logic state) to V _OL (low voltage logic state, about 0.2 V), point 18 close to V _{OL due} to the ringback effect. A bounce occurs in the waveform. The rebound voltage level at point 18 is 0.8V, a level very close to the reference voltage V _ref = 1.0V. Therefore, the output logical value of the input / output buffer may be affected.
[0006]
A conventional solution to the above-described problem is shown in FIG. 1, with a node 16 between IC2 and transmission line 10 and a 50 ohm resistor r _t2 between transmission line 14 and system voltage V _tt. To the transmission line 14. This arrangement reduces the ringback effect when IC2 serves as an input terminal and IC1 serves as an output terminal. However, since the input / output buffer includes resistors r _t1 and r _t2 , a pull-up effect can appear in the waveform of the data signal of IC1. The effect of pull-up is a phenomenon in which the waveform of the data signal of IC1 is raised more rapidly than usual and lowered later. Furthermore, the added resistance r _t2 causes an increase in power consumption in the entire input / output buffer. One way to reduce power consumption is to replace a 50Ω resistor with a resistor with a larger resistance. However, this solution only stabilizes the ripple of the waveform signal due to the ringback effect by about 0.1V. If one 50Ω resistor is provided for each IC 2 on the board, a large space is required on the board, and the overall power consumption is greatly increased, resulting in higher manufacturing and operating costs. .
[0007]
SUMMARY OF THE INVENTION It is an object of the present invention to provide an input / output buffer that reduces the ringback effect. This input / output buffer is suitable for use with a data transmission bus such as a GTL + bus to transmit high frequency, low amplitude data signals. This is to reduce the ringback effect on the input / output buffer when the input signal switches from the high voltage logic state to the low voltage logic state.
[0008]
Another object of the present invention is to provide an input / output buffer that reduces the ringback effect. This input / output buffer is suitable for use with a data transmission bus such as a GTL + bus for transmitting high frequency and low amplitude data signals. This makes it possible to reduce the power consumption of the input / output buffer without adding resistance to each transmission line.
[0009]
In accordance with the foregoing and other objectives, an input / output buffer is provided that reduces ringback effects. The input / output buffer of the present invention is designed for a data transmission bus such as a GTL + bus for transmitting high frequency and low amplitude data signals. This input / output buffer includes the following components.
[0010]
An input / output pad that receives data signals from the data transmission bus.
[0011]
An output transistor having a first terminal connected to the input / output pad and a second terminal grounded. Therefore, when the input / output buffer operates in the input mode or the high voltage output mode, the output transistor is cut off. When the input / output buffer operates in the low voltage output mode, the output transistor switches to a conductive state.
[0012]
A signal level detector that detects the signal strength of a data signal and generates a level indicating signal that takes a first logic state if the input signal is higher than a predetermined reference voltage and takes a second logic state if the input signal is lower than the reference voltage. .
[0013]
A resistance regulator that generates a resistance adjustment signal in response to a level instruction signal.
[0014]
A variable resistor in which the first terminal is connected to the system voltage having the same signal strength as the high voltage logic state of the data signal, and the second terminal is connected to the input / output pad. The variable resistor is switched to a low resistance value when the signal strength of the data signal is higher than the reference voltage, and to a nearly infinite resistance value when the signal strength is low, according to the resistance matching signal from the resistance regulator. And switch between almost infinite resistance values.
[0015]
And a signal level detector including an analog comparator for comparing the predetermined reference voltage with the data signal. The comparator transmits a high voltage logic signal when the data signal has a signal strength greater than the reference voltage, and a low voltage logic signal when the data signal is lower than the reference voltage. The high voltage logic signal transmitted from the comparator causes the resistance regulator to switch the variable resistor to a low resistance value. Conversely, the low voltage logic signal transmitted from the comparator causes the resistance regulator to switch the variable resistor to an almost infinite resistance value.
[0016]
The aforementioned input / output buffer is used together with a data transmission bus for high frequency and low amplitude data signals such as a GTL + bus. A feature of the invention resides in the provision of a variable resistor that reduces the ringback effect in the input / output buffer. Compared to the prior art, it benefits from the reduced design area on the substrate and lower power consumption.
[0017]
FIG. 3 is a circuit diagram showing a circuit structure of an input / output buffer in which the ringback effect is reduced by the invention. The input / output buffer of the present invention is specially designed for use as the IC 2 of FIG. 1 to reduce the ringback effect described in the background of this specification. This input / output buffer is suitable for use with a data transmission bus such as a GTL + bus to transmit high frequency, low amplitude data signals.
[0018]
As shown in FIG. 3, the input / output buffer of the present invention includes an input / output pad 30, a signal level detector 20 (also used as an input buffer), an output buffer 22, and an input / output control logic circuit 24. The output buffer 22 further, the regulator 26 includes an output transistor 28, the variable resistor _{R 1} connected NMOS (N-type metal oxide semiconductor) transistor, and a between output pad 30 system voltage _{V tt} Examples .
[0019]
The system voltage V _tt is set to a voltage level equal to the high voltage logic state of the data signal received at the input / output buffer, for example 1.5V. In this embodiment, the signal level detector 20 is an analog comparator having a positive input terminal (+) connected to the input / output pad 30 and a negative input terminal (−) connected to the reference voltage V _ref. . The signal level detector 20 emits a level instruction signal indicating the level of the data signal received at the input / output pad 30. For example, the level indication signal is switched to a high voltage logic state if the data signal has a signal strength higher than the reference voltage V _{ref and} to a low voltage logic state if the data signal has a low signal strength. The level instruction signal is transmitted from the signal level detector 20 to the resistance regulator 26. Depending on the level indication signal from the signal level detector 20, and if the output enable signal OEN from outside is enabled, the resistance regulator 26 to control the resistance of the variable resistor R ₁ emits a resistance adjustment signal. In this embodiment, the resistance of the variable resistor R ₁ can be switched from a low resistance between 200Ω from 100 to near infinity (approximately cut-off state), and vice versa.
[0020]
When the input / output buffer operates in the input mode, the input / output control logic circuit 24 outputs to the output transistor 28 a 0V control signal that switches the output transistor 28 to the cutoff state. Similarly, when the input / output buffer operates in the high voltage output mode, the output transistor 28 switches to a conductive state. When operating in the input mode, if the input / output pad 30 receives an input data signal having a signal strength higher than the reference voltage V _ref , the signal level detector 20 connects the variable resistor R ₁ from 100 to the resistance regulator 26. A high voltage logic signal adapted to a low resistance value between 200Ω is output. As a result, the system voltage V _tt is set 1.5V, the when the data signal at output pad 30 is stable at 1.5V (high voltage logic state), a variable resistor R ₁ current Not flowing. This is because both ends of the variable resistor R ₁ is in the equipotential, so that the power consumption is zero.
[0021]
In this embodiment, the reference voltage V _ref sent to the analog comparator of the signal level detector 20 is set to 1.0V. Therefore, when the input data signal at the input / output pad 30 is switched from 1.5 V (high voltage logic state) to less than 1.0 V (low voltage logic state), the signal level detector 20 outputs a low voltage logic signal. . This signal is adjusted to substantially infinite resistance value resistor of the variable resistor R ₁ to the resistance regulator 26, output pads 30 therefor are electrically isolated from the system voltage V _tt (i.e. open circuit). As a result, the variable resistor R ₁ no current flows, power consumption is zero.
[0022]
As shown in FIG. 5, in this embodiment, a PMOS (P-type metal oxide semiconductor) transistor 38 connected to the resistor R ₃ can be used as the variable resistor R ₁ . When the input / output pad 30 is receiving an input data signal in a high voltage logic state between 1.0V and 1.5V, the signal level detector 20 issues a high voltage logic signal. In response to the high voltage logic signal, the resistor regulator 26 issues a 0V control signal to the gate of the PMOS transistor 38, thereby switching the PMOS transistor 38 to a conductive state. In the conductive state, the equivalent resistance between the source and drain of the PMOS transistor 38 is about 100Ω to 200Ω.
[0023]
On the other hand, when the input / output pad 30 receives an input data signal having a signal strength of less than 1.0 V, the signal level detector 20 generates a low voltage logic signal. In response to the low voltage logic signal, the resistor regulator 26 issues a high voltage signal to the gate of the PMOS transistor 38, which causes the PMOS transistor 38 to be switched to a cut-off state. According to the original characteristics of the PMOS transistor 38, about 5 to 10 ns (nanoseconds) is required to completely switch to the cut-off state. In the conductive state, the equivalent resistance between the source and drain of the PMOS transistor 38 is almost infinite.
[0024]
The variable resistor R ₁ having the active switching characteristic can reduce the ringback effect to less than 0.4V. As depicted in FIG. 4, when the input data signal is switched from 1.5 V (high voltage logic state) to V _OL (low voltage state, about 0.2 V), the point 29 bounces due to the ringback effect. about 0.4V in very close value to the V _OL (approximately 0.2V). It is clear that the invention is making progress when compared to the 0.8V bounce in the prior art.
[0025]
FIG. 5 is a circuit diagram showing a detailed circuit structure of the resistance regulator 26 used in the input / output buffer of FIG. As shown here, the resistance regulator 26 includes three NMOS transistors (first NMOS transistor 32, second NMOS transistor 34, and third NMOS transistor 36) and three PMOS transistors (first NMOS transistor 36). 1 PMOS transistor 40, second PMOS transistor 42, and third PMOS transistor 44). The variable resistor R ₁ includes a PMOS transistor 38 and a resistor R ₃ .
[0026]
Three transistors 40, 42, 44, a source are all connected to the system voltage _{V tt,} drains are all connected together to the gate of the PMOS transistor 38 of the variable resistor _{R 1.} However, the gate of the first PMOS transistor 40 is connected to both the gate of the second NMOS transistor 34 and the inversion of the control signal A · OEN, and the second PMOS transistor 42 is connected to the gate of the third NMOS transistor 36 and the control. Connected to the signal ZI + OEN, the gate of the third PMOS transistor 44 is connected to the gate of the first NMOS transistor 32 and the control signal PEN.
[0027]
The source of the first NMOS transistor 32 is grounded, the drain is connected to the source of the second NMOS transistor 34, and the gate is connected to the control signal PEN. The second NMOS transistor 34 has a source connected to the drain of the first NMOS transistor 32, a drain connected to the source of the third NMOS transistor 36, and a gate connected to the inversion of the control signal A · OEN. The third NMOS transistor 36 has a source connected to the drain of the second NMOS transistor 34, the drain is connected to the gate of the three drain and the variable resistor _{R 1} of the PMOS transistor 38 of the PMOS transistor 40, 42, 44 The gate is connected to the control signal ZI + OEN.
[0028]
The control signal PEN is used to monitor and is switched to a high voltage logic state to activate the PMOS transistor 38 while the input / output buffer is active. The control signal OEN is an output enable signal used to enable the output of the GTL + IO pad buffer. The control signal ZI is the output of the signal level detector 20 shown in FIG.
[0029]
When it is requested to PMOS transistor 38 is switched to the conducting state, that is, when the resistance through the variable resistor R ₁ is switched to a low resistance value must switched NMOS transistor 32, 34, 36 wholly conductive. When it is requested to PMOS transistor 38 is switched to the blocking state, i.e. when the resistance through the variable resistor _{R 1} is switched to the resistance value of the almost infinite, in one of cut-off state of the NMOS transistors 32, 34, 36 It must be switched. In other words, when the gate voltage of one of the PMOS transistors 40, 42, 44 is switched to the low voltage state, the PMOS transistor 38 is sufficiently switched to the cutoff state.
[0030]
The second PMOS transistor 42 is a weak type that requires 5 to 10 ns to raise the gate voltage of the PMOS transistor 38 of the variable resistor R ₁ higher than the initial voltage, thereby switching the PMOS transistor 38 to the cut-off state. . As a result, the variable resistor R ₁ at both ends is switched almost infinite resistance value, the current power consumption not flow decreases.
[0031]
In conclusion, the input / output buffer of the present invention can be used with a data transmission bus that can handle high frequency, low amplitude data signals such as a GTL + bus. The input / output buffer of the present invention is characterized by providing a variable resistor that reduces the ringback effect of the input / output buffer. This can reduce the design area on the substrate and provide the benefit of low power consumption compared to the prior art.
[0032]
The present invention has been described using preferred embodiments. However, the scope of the present invention is not limited to the scope described in the above embodiment. Rather, it includes many variations and similar devices. Accordingly, the claims should be accorded the broadest interpretation so as to include all such modifications and similar devices.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a conventional GTL + bus.
2 is a waveform diagram showing bounce in the waveform of a data signal received by the IC 2 in FIG. 1; FIG.
FIG. 3 is a circuit diagram showing a circuit structure of an input / output buffer in which the ringback effect is reduced according to the invention.
4 is a waveform diagram showing a waveform of a data signal received by the input / output buffer of FIG. 3. FIG.
5 is a circuit diagram showing a detailed circuit structure of a resistance regulator used in the input / output buffer of FIG. 3. FIG.

Claims (4)

An input / output buffer for a data transmission bus for transmitting high-frequency and low-amplitude data signals,
A signal level detector that detects the signal strength of the data signal and emits a level indicating signal that takes a first logic state if the signal is higher than a reference voltage and takes a second logic state if the signal strength is lower;
A resistance regulator that generates a resistance adjustment signal in response to the level instruction signal;
A variable resistor having a first terminal connected to a system voltage having a signal strength equal to a high voltage logic state of the data signal and a second terminal connected to an input terminal of the input / output buffer;
The variable resistor is configured to switch between a predetermined low resistance value and a substantially infinite resistance value so that the variable resistance value is switched to a low resistance value when the data signal has a signal strength higher than a reference voltage, and to a substantially infinite resistance value when the data signal is low. An input / output buffer that switches according to a resistance adjustment signal from a resistance regulator. The signal level detector includes an analog comparator that compares the reference voltage with the data signal, the comparator including a high voltage logic signal when the data signal has a signal strength higher than the reference voltage, and a low voltage when low. The input / output buffer according to claim 1, which transmits a logic signal. The high voltage logic signal from the comparator causes the resistance regulator to switch the variable resistor to a low resistance value range between 100 and 200Ω, and the low voltage logic signal from the comparator causes the resistance regulator to The input / output buffer according to claim 2, wherein the variable resistor is switched to an almost infinite resistance value. And further comprising an output transistor having a first terminal connected to the input terminal of the input / output buffer and a second terminal grounded, the output transistor being cut off when the input / output buffer operates in an input mode or a high voltage output mode. The input / output buffer of claim 1, wherein the input / output buffer is switched to a conductive state when switched to a state and operates in a low voltage output mode.

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