JP3730455B2 - 情報処理装置及び情報処理方法 - Google Patents

情報処理装置及び情報処理方法 Download PDF

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Publication number
JP3730455B2
JP3730455B2 JP28195799A JP28195799A JP3730455B2 JP 3730455 B2 JP3730455 B2 JP 3730455B2 JP 28195799 A JP28195799 A JP 28195799A JP 28195799 A JP28195799 A JP 28195799A JP 3730455 B2 JP3730455 B2 JP 3730455B2
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Japan
Prior art keywords
instruction
basic
unit
configuration
word
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JP28195799A
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English (en)
Japanese (ja)
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JP2001100997A5 (enExample
JP2001100997A (ja
Inventor
英雄 三宅
敦浩 須賀
泰基 中村
好正 竹部
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Fujitsu Ltd
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Fujitsu Ltd
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Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP28195799A priority Critical patent/JP3730455B2/ja
Priority to US09/654,527 priority patent/US7401204B1/en
Priority to DE60045208T priority patent/DE60045208D1/de
Priority to EP00307646A priority patent/EP1089168B1/en
Priority to KR1020000056946A priority patent/KR100689717B1/ko
Publication of JP2001100997A publication Critical patent/JP2001100997A/ja
Publication of JP2001100997A5 publication Critical patent/JP2001100997A5/ja
Application granted granted Critical
Publication of JP3730455B2 publication Critical patent/JP3730455B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP28195799A 1999-10-01 1999-10-01 情報処理装置及び情報処理方法 Expired - Fee Related JP3730455B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP28195799A JP3730455B2 (ja) 1999-10-01 1999-10-01 情報処理装置及び情報処理方法
US09/654,527 US7401204B1 (en) 1999-10-01 2000-09-01 Parallel Processor efficiently executing variable instruction word
DE60045208T DE60045208D1 (de) 1999-10-01 2000-09-05 Prozessor mit sehr langem Befehlswort
EP00307646A EP1089168B1 (en) 1999-10-01 2000-09-05 Very long instruction word processor
KR1020000056946A KR100689717B1 (ko) 1999-10-01 2000-09-28 병렬 처리 프로세서

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28195799A JP3730455B2 (ja) 1999-10-01 1999-10-01 情報処理装置及び情報処理方法

Publications (3)

Publication Number Publication Date
JP2001100997A JP2001100997A (ja) 2001-04-13
JP2001100997A5 JP2001100997A5 (enExample) 2004-12-02
JP3730455B2 true JP3730455B2 (ja) 2006-01-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP28195799A Expired - Fee Related JP3730455B2 (ja) 1999-10-01 1999-10-01 情報処理装置及び情報処理方法

Country Status (5)

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US (1) US7401204B1 (enExample)
EP (1) EP1089168B1 (enExample)
JP (1) JP3730455B2 (enExample)
KR (1) KR100689717B1 (enExample)
DE (1) DE60045208D1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7100026B2 (en) * 2001-05-30 2006-08-29 The Massachusetts Institute Of Technology System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
JP2002318687A (ja) * 2001-04-18 2002-10-31 Fujitsu Ltd 情報処理装置及び計算機システム
JP4542722B2 (ja) 2001-04-25 2010-09-15 富士通株式会社 命令処理方法
KR100867269B1 (ko) 2007-02-22 2008-11-06 삼성전자주식회사 프로세서의 추론적 로드 명령 실행 방법 및 상기 방법을채용한 프로세서
KR100875836B1 (ko) 2007-03-23 2008-12-24 삼성전자주식회사 병렬 처리 ｖｌｉｗ 컴퓨터를 위한 인스트럭션 명령어 압축장치 및 그 방법
US8578387B1 (en) 2007-07-31 2013-11-05 Nvidia Corporation Dynamic load balancing of instructions for execution by heterogeneous processing engines
US9304775B1 (en) * 2007-11-05 2016-04-05 Nvidia Corporation Dispatching of instructions for execution by heterogeneous processing engines
JP2010257199A (ja) * 2009-04-24 2010-11-11 Renesas Electronics Corp プロセッサ及びプロセッサにおける命令発行の制御方法
US8443343B2 (en) * 2009-10-28 2013-05-14 Intel Corporation Context-sensitive slicing for dynamically parallelizing binary programs
CN109324981B (zh) * 2017-07-31 2023-08-15 伊姆西Ip控股有限责任公司 高速缓存管理系统和方法
CN113867797A (zh) * 2020-06-30 2021-12-31 上海寒武纪信息科技有限公司 计算装置、集成电路芯片、板卡、电子设备和计算方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
JPH0440525A (ja) 1990-06-06 1992-02-10 Seiko Epson Corp 並列処理型マイクロプロセッサ
JPH052484A (ja) 1991-06-24 1993-01-08 Mitsubishi Electric Corp スーパースカラプロセツサ
US5787303A (en) 1991-10-31 1998-07-28 Kabushiki Kaisha Toshiba Digital computer system capable of processing a plurality of instructions in parallel based on a VLIW architecture
JP2928684B2 (ja) 1991-10-31 1999-08-03 株式会社東芝 Ｖｌｉｗ型演算処理装置
JP3569338B2 (ja) 1995-02-24 2004-09-22 富士通株式会社 並列処理プロセッサ
US5758114A (en) * 1995-04-12 1998-05-26 Advanced Micro Devices, Inc. High speed instruction alignment unit for aligning variable byte-length instructions according to predecode information in a superscalar microprocessor
JP2931890B2 (ja) 1995-07-12 1999-08-09 三菱電機株式会社 データ処理装置
US5787302A (en) * 1996-05-15 1998-07-28 Philips Electronic North America Corporation Software for producing instructions in a compressed format for a VLIW processor
US5852741A (en) * 1996-05-15 1998-12-22 Philips Electronics North America Corporation VLIW processor which processes compressed instruction format
US5941980A (en) * 1996-08-05 1999-08-24 Industrial Technology Research Institute Apparatus and method for parallel decoding of variable-length instructions in a superscalar pipelined data processing system
JPH1074145A (ja) 1996-08-30 1998-03-17 Oki Electric Ind Co Ltd 命令供給装置
US5870576A (en) 1996-12-16 1999-02-09 Hewlett-Packard Company Method and apparatus for storing and expanding variable-length program instructions upon detection of a miss condition within an instruction cache containing pointers to compressed instructions for wide instruction word processor architectures
JPH10232779A (ja) 1997-01-24 1998-09-02 Texas Instr Inc <Ti> 命令並列処理方法及び装置
US5881307A (en) * 1997-02-24 1999-03-09 Samsung Electronics Co., Ltd. Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor
JP3790607B2 (ja) * 1997-06-16 2006-06-28 松下電器産業株式会社 Ｖｌｉｗプロセッサ
US6151668A (en) * 1997-11-07 2000-11-21 Billions Of Operations Per Second, Inc. Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication
US6173389B1 (en) * 1997-12-04 2001-01-09 Billions Of Operations Per Second, Inc. Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
JP3451921B2 (ja) 1998-03-30 2003-09-29 松下電器産業株式会社 プロセッサ
US6738892B1 (en) * 1999-10-20 2004-05-18 Transmeta Corporation Use of enable bits to control execution of selected instructions

Also Published As

Publication number Publication date
US7401204B1 (en) 2008-07-15
EP1089168A3 (en) 2001-10-17
KR20010050693A (ko) 2001-06-15
EP1089168A2 (en) 2001-04-04
JP2001100997A (ja) 2001-04-13
EP1089168B1 (en) 2010-11-10
DE60045208D1 (de) 2010-12-23
KR100689717B1 (ko) 2007-03-09

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