JP3725632B2 - Incremental encoder - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an incremental encoder used for detecting a displacement amount and speed of a rotating body such as a motor.
[0002]
[Prior art]
FIG. 9 shows the configuration of a conventional optical incremental encoder. The incremental encoder includes a light emitting element 1 such as an LED, a code plate 2, a detection element 3, a waveform shaping circuit 4, a power supply voltage monitoring circuit 5, a direction determination circuit 6, an up / down (U / D) counter 7, and a data latch circuit 17. And the serial signal conversion circuit 18.
[0003]
The light emitting element 1 is composed of a semiconductor light emitting element such as an LED, an incandescent bulb, etc., and the code plate 2 is made of a slit, a metal having a notch, a synthetic resin, or the like that provides an A phase, B phase phase difference signal, a Z phase origin signal, The disk operates following the operation of the rotating body that is the object to be measured. The detection element 3 includes a photodiode, a phototransistor, and the like, and detects light transmitted through the slits / notches of the code plate 2. The waveform shaping circuit 4 adjusts the output waveform of the detection element 3 to a waveform suitable for the subsequent processing.
[0004]
Further, the direction discriminating circuit 6 discriminates the rotation direction from the A-phase pulse and the B-phase pulse which are two phase difference signals, and outputs an up count (UPP) or down count (DOP) pulse according to the rotation direction. . The up / down (U / D) counter 7 increments or decrements internal data in accordance with the input up count (UPP) or down count (DOP) pulse. Further, the internal data is cleared to zero by a reset signal from the power supply voltage monitoring circuit. The data latch circuit 17 holds the output signal (DI) of the up / down (U / D) counter 7 and the origin signal Z in accordance with the serial data transfer cycle. The serial data conversion circuit 18 converts the count data (DIo) and the origin signal (Zo) from the data latch circuit 17 into serial data (SD) and outputs it, and also gives a latch timing pulse (LTS) to the data latch circuit. .
[0005]
Next, the operation of such an incremental encoder will be described.
[0006]
FIG. 10 is a time chart showing the operation of the incremental encoder of FIG. When the code plate 2 rotates, A-phase and B-phase pulses having different phase states appear according to the rotation direction. Considering the case where the code plate 2 is rotating in the reverse direction (CCW), A and B phase pulses shown in the CCW region of FIG. 10 are generated.
[0007]
Here, it is assumed that the direction discriminating circuit 6 generates an output signal by the logical product (AND) of the rising and falling edges of the A-phase and B-phase pulses and the level. In the example of (1), the case where the processing time of the logical product (AND) is very short is shown, and in the example of (2), the case where TF is required for the AND processing time is shown. In addition, the section indicated by (A) is in a normal phase state, and the sections indicated by (B) and (C) are out of phase, so the signal width of one section (B) is shortened to the standard minimum value. The sections indicated by (2) show the cases where noise occurs.
[0008]
In the example of (1), since the processing time is short, miscounting occurs following the noise (... N + 4, n + 3, n + 4, n + 3...). However, in this case, since the phase relationship between the A phase and the B phase is apparently reversed, one up count signal and one down count signal are generated, and as a result, the contents of the counter are normal values. In the example of (2), since the processing time is delayed by TF, it will not follow the noise, but it will not be able to follow the rise of the B phase in the section (b), and the signal within the standard value will be missed. Producing a count
[0009]
[Problems to be solved by the invention]
Thus, in the conventional incremental encoder, when the signal period T is 1, the phase difference accuracy of the A and B phase signals is the phase difference Xn ≧ 0.125T (n = 1, 2, 3). 4 ...). When detecting individual edges of the phase difference A and B phase signals and counting the signal period (response frequency) by four, the processing speed is at least eight times the signal period (response frequency). It is necessary, and therefore it is easy to follow the noise component.
[0010]
Also, when the Z-phase signal is converted into a serial signal and output, if the Z-phase signal width is shorter than the serial signal transfer cycle Tcyc (such as during high-speed rotation), the Z-phase cannot be detected and the serial signal cannot be transmitted. A state arises. On the other hand, if noise occurs on the transmission line during serial signal transfer, the Z-phase signal data may not be recognized on the receiving side, causing a serious malfunction due to unidentified origin.
[0011]
In addition, since individual data is intermittently output as serial signals, signal processing (data discrimination, calculation, etc.) at the receiving device is complicated, and there is a disadvantage that the circuit becomes complicated.
[0012]
Furthermore, the data of the up / down counter with respect to the moving position is different every time the power is turned on, making it difficult to process data in the receiving device.
[0013]
An object of the present invention is to provide an incremental encoder that prevents counting errors due to noise and that has a high response processing speed.
[0014]
Another object of the present invention is to provide an incremental encoder that can easily process data received by a receiving device or process power-on data.
[0015]
Another object of the present invention is to provide an incremental encoder capable of reliably detecting and recognizing a Z phase with respect to a receiving device.
[0016]
[Means for Solving the Problems]
The above object is achieved by the following configuration.
(1) A code signal generation unit that provides a phase difference 2 signal and an origin signal according to at least the rotation of the object to be measured, and a data count unit that counts incremental data obtained from the phase difference 2 signal from the code signal generation unit Have
The data counting unit discriminates the rotational direction based on the phase difference 2 signal and generates a count signal for the change point of one of the signals, and the counting unit counts the count signal from the direction discriminating means. Low-order data generation means for generating low-order 2-bit data from the phase difference 2 signal, and when the time from the change point of one of the phase difference 2 signals to the next change point is equal to or longer than a predetermined time TF Timing means for providing only the read timing, and giving the weight of 3 bits or more from the least significant bit to the data of the counting means so as to be integrated with the data of the lower 2 bits, and reading this data at the read timing from the timing means An incremental encoder comprising data holding means for counting data.
(2) The incremental encoder according to (1), wherein the predetermined time TF of the timing means has a maximum value less than a quarter cycle of the A-phase and B-phase pulses which are two phase difference signals.
(3) A code signal generation unit that provides a phase difference 2 signal and an origin signal according to at least the rotation of the object to be measured, and a data count unit that counts incremental data obtained from the phase difference 2 signal from the code signal generation unit And a data continuity determination unit for determining the continuity of data when transferring the count data,
The data continuity determination unit compares data holding means for holding previously transferred data and data to be transferred at the present time with data transferred at the previous time obtained from the data holding means and the data to be transferred at present. Incremental encoder having data comparison means for judging whether or not the value is equal to or less than a reference value K and outputting the result.
(4) The incremental encoder according to (3), wherein the data count unit is the data count unit according to (1) or (2).
(5) The incremental encoder according to (1), further including an origin signal normalization unit that sends out the signal as the predetermined signal width N + 1 when the signal width of the origin signal is less than the predetermined signal width N + 1.
(6) The origin signal normalization unit includes a Z-phase signal synchronization means for synchronizing the Z-phase signal to one of the four divided areas of the A and B phases, and a sampling signal for transferring the count data as a serial signal. Z0 signal processing means for outputting as a signal length corresponding to the predetermined number N + 1 when the number of times the input and the output from the Z-phase signal synchronizing means are recognized by the sampling signal is less than or equal to the predetermined number N The incremental encoder according to (5) above.
(7) The incremental encoder according to (6), wherein the Z0 signal processing means inputs rotational direction data obtained from the A and B phase signals and stops sending the origin signal when the rotational direction changes.
(8) The data continuity determining unit of (3) is provided, and the origin signal normalizing unit recognizes that there is no continuity of the transfer data based on the output from the data continuity determining unit. The incremental encoder according to (7), which stops sending.
(9) The counter means data is cleared to zero when the counter clear signal CLR and the Z-phase / or alternative signal are input from the outside, or when the Z-phase / or alternative signal is input after the counter clear signal CLR is input. Incremental encoder according to any one of (1) to (8), further comprising count data matching means 13 for performing the above.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
The incremental encoder according to the present invention includes a code signal generation unit 21 that provides a phase difference 2 signal and an origin signal in accordance with the rotation of the object to be measured, and a phase difference 2 signal from the code signal generation unit. Direction discriminating means 6 for outputting a count signal, UPP (logical negation / inversion symbol omitted) or DOP (logical negation / inversion symbol omitted), and counting means 7 for counting this signal and outputting count data And lower data generating means 9 for generating lower 2 bit data from the phase difference 2 signal, and the time from the change point of any one of the phase difference 2 signals to the next change point is a predetermined time TF or more Timing means 8 for providing a read signal as a read timing only to the data, and giving the weight of 3 bits or more from the least significant bit to the data of the counting means 7 in the lower order And integral with the bit data, and has read the data count unit 22 and a data holding means 12 for the count data with this data by reading the signal from the timing means. The predetermined time TF of the timing means has a maximum value less than 1/4 of one cycle of the A-phase and B-phase pulses, which are two phase difference signals.
[0018]
Further, the data holding means 14 and 15 for holding the previously transferred data DA and the currently transferred data DB are compared with the previously transferred data obtained from the data holding means 14 and 15 and the currently transferred data. It has a data continuity determination unit 24 that includes data comparison means 16 that determines whether or not the difference is equal to or less than a predetermined reference value K and outputs the result.
[0019]
In addition, when the signal width of the origin signal (Z-phase signal) is equal to or less than a predetermined signal width (≦ N), the origin signal normalization unit 23 that transmits the signal as a predetermined signal width (N + 1) is provided. The signal normalization unit 23 inputs the Z-phase signal synchronization means 10 for synchronizing the Z-phase signal to one of the four divided regions of the A and B phases, and the sampling signal LTS for transferring the count data as a serial signal. Z0 signal processing means 11 for outputting the signal length Z1 corresponding to the predetermined number N + 1 when the number of times the output from the Z-phase signal synchronizing means 10 is recognized by the sampling signal LTS is equal to or less than the predetermined number N; Prepare.
Further, when the counter clear signal CLR and the Z0 signal from the Z-phase signal synchronization means 10 (signal replacing the Z-phase signal) are input from the outside, or when the Z0 signal is input after the counter clear signal CLR is input, the counting means Count data matching means 13 for clearing data to zero is provided.
[0020]
【Example】
Next, a more specific configuration of the present invention will be described.
[0021]
FIG. 1 is a block diagram showing the basic configuration of an incremental encoder according to the present invention. This incremental encoder includes a light emitting element 1 as a code signal generation unit 21, a code plate 2, a detection element 3, and a waveform shaping circuit 4, a power supply voltage monitoring circuit 5, and a direction determination circuit 6 as a data count unit 22. , An up / down (U / D) counter 7, a timing processing circuit 8, a sign conversion circuit 9, and a data latch circuit 12, and a Z0 signal synchronization gate 10 and a Z0 signal processing circuit 11 as an origin signal normalization unit 23. A data latch circuit 14, a data latch circuit 15, and a data comparison circuit 16 as a data continuity determination unit 24; a data latch circuit 17 and a serial signal conversion circuit 18 as a serial signal transmission unit 25; and a counter A clear circuit 13 is provided.
[0022]
The light-emitting element 1 is composed of a semiconductor light-emitting element such as an LED or LD, an incandescent bulb, a cold cathode tube, a plasma light-emitting element, a fluorescent light emitter, etc., and the code plate 2 is a phase difference signal of A phase or B phase or an origin signal of Z phase. It is a disk made of a metal having a slit / notch for providing the like, a synthetic resin, etc., and follows the operation of the rotating body as the object to be measured. The detection element 3 is composed of a light / electric conversion element such as a photodiode or a phototransistor, is located at a position corresponding to the light emitting element via the code plate 2, and detects light transmitted through the slit / notch of the code plate 2. The waveform shaping circuit 4 adjusts the output waveform of the detection element 3 to a waveform having a level suitable for the subsequent processing.
[0023]
Further, the direction discriminating circuit 6 discriminates the rotation direction from the A-phase pulse and the B-phase pulse which are two phase difference signals, and at the rising or falling edge of the A-phase (or B-phase) 1 pulse according to the rotation direction. Correspondingly, an up-count (UPP: logic negation / inversion symbol is omitted; the same applies hereinafter) or down-count (DOP) pulses are output. The up / down (U / D) counter 7 increments or decrements the internal data according to the input up count (UPP) or down count (DOP: logic negation / inversion symbol is omitted; the same applies hereinafter) pulses. Further, the internal data is cleared to zero by a reset signal RES from the power supply voltage monitoring circuit 5 or a data clear signal CLD from a counter clear circuit 13 for processing an external counter clear signal CLR and an origin signal Z0 as will be described later. The power supply voltage monitoring circuit 5 outputs a reset signal RES when the power supply voltage becomes lower than a predetermined value or when the power is turned on.
[0024]
The code conversion circuit 9 converts the codes of the A-phase and B-phase pulses and outputs them as 2-bit data DLSB from the LSB side. The timing processing circuit 8 detects each change edge of the A-phase and B-phase pulses, and outputs the read signal LTI only when the time from one change point to the next change point is equal to or longer than a predetermined time TF. The data latch circuit 12 outputs the output DC from the up / down (U / D) counter 7 to 2 ² The output from the sign conversion circuit DLSB is 2 ⁰ And 2 ¹ Is latched by the read signal LTI from the timing processing circuit.
[0025]
The data latch circuit 14 latches the output DI from the data latch circuit 12 with the signal LTS in synchronization with the serial signal transfer cycle. Further, the data latch circuit 15 latches the output DB from the data latch circuit 14 by the data latch signal LTS. The data comparison circuit 16 compares the output data DB of the data latch circuit 14 with the output data DA of the data latch circuit 15, determines whether the difference is the reference value K or less, or K + 1 or more, and confirms the result for continuity. Output as signal SC. Here, the reference value K is K ≧ 0, and is a value appropriate for determining the amount of delay due to the serial signal transfer cycle, and is set in advance.
[0026]
For example, as shown in FIG. 2, the Z0 signal synchronization gate 10 synchronizes the Z phase signal with any one of the four regions (X1, X2, X3, X4) obtained by the phase difference pulses of the A and B phases. The signal Z0 is output. The Z0 signal processing circuit receives the output DIR from the output Z0 direction discriminating circuit of the Z0 signal synchronization gate 10 and the sampling pulse LTS synchronized with the serial signal transfer cycle, and detects the Z0 signal by this sampling pulse LTS. The Z0 signal detected in the rotation speed range is set as a pulse 2Z0 having a detection count length, and the Z0 signal detected in a predetermined high rotation speed range is equal to or less than the set count N is set as a pulse 1Z0 having an N + 1 detection count length, and only in the gap of the sampling pulse LTS. The detected Z0 signal is set to a pulse 0Z0 having a length of N + 1 detection times, a change in rotation direction is judged by the DIR input, the input conditions are canceled, and a logical sum (OR) signal of the pulses 2Z0, 1Z0, 0Z0 Z1 is output. That is, when the Z0 signal is detected, the origin detection information is transferred by the serial signal N + 1 times from the timing of the nearest sampling pulse LTS. Further, the continuity confirmation signal SC is input during the origin return operation or the like, and when the SC signal exceeding the continuity is detected, the sending of the Z1 signal is stopped so that the reliable origin return operation can be performed.
[0027]
The data latch circuit 17 transfers the output signal DB of the data latch circuit 14, which is data from the up / down (U / D) counter, the output signal SC of the data comparison circuit 16, and the output Z1 of the Z0 signal processing circuit 11 as serial signals. The signal is latched by a sampling pulse LTS synchronized with the period, and output as latch signals DIo, SCo, and Z1o, respectively. The serial signal conversion circuit 18 converts a signal input every predetermined transfer cycle Tcyc into a serial signal SD and sends it out, and outputs a sampling signal LTS that gives input (latch) timing of data to be transferred.
[0028]
Next, the operation of each part of the encoder of the present invention will be described in more detail.
[0029]
<Data count part>
FIG. 3 is a timing chart showing the operation of the data count unit 22.
[0030]
Here, the 2-bit signal DLSB from the LSB given by the code conversion circuit 9 is obtained from the phase difference between the A-phase and B-phase pulses as shown in FIG. 2, and is converted into the sign of the absolute position data bit0, bit1. is there. And this 2-bit signal DLSB is the lower 2 bits, that is, 2 ⁰ And 2 ¹ It becomes the data of the place. The output from the direction discriminating circuit 6 is UPP or DOP (the logic negation / inversion symbol is omitted. The same applies hereinafter) corresponds to the change point of the A-phase pulse which is one of the phase difference signals in this example, and in the rotational direction. Either one is output in response. The output data DC of the up / down (U / D) counter 7 that receives and counts the UPP or DOP signal is handled as a signal that is equal to or higher than the DLSB that is the lower 2 bits. That is, 2 ² A weight greater than or equal to is given. Accordingly, in FIG. 3, since the encoder rotates in the CCW direction, both the data DLSB and DC decrease.
[0031]
Here, the section indicated by (A) is in a normal phase state, and the sections indicated by (B) and (C) are short of the signal width of one section (B) to the standard minimum value because the phase is shifted. The section indicated by (2) indicates the case where noise occurs. The output LTI of the timing processing circuit 8 is output when a predetermined time TF or more from the change point of either the A phase or the B phase to the next change point. Therefore, in the A phase malfunction signal due to the noise generated in the section (2), the output DC of the up / down (U / D) counter 7 and the output DLSB of the sign conversion circuit 9 change, but the data latch signal LTI is output. Since it is not performed (signal width is TF or less), it is not input to the data latch circuit 12. When the normal signal state is restored, the output DC of the up / down (U / D) counter 7 and the output DLSB of the sign conversion circuit 9 become normal values. At this time, the data latch signal LTI is output and normal data is stored. Is output.
[0032]
In addition, when the signal width of the standard value is minimum in the section (b), the data latch signal LTI is not output, but the output DLSB of the sign conversion circuit 9 changes (3 → 2), and the next data latch signal LTI In FIG. 5, data (n + 3 → n + 1) in a further changed state is latched.
[0033]
As described above, the delay time of the signal processing, which has been conventionally defined as less than 0.125 T, is less than 0.25 T, and the allowable value of the malfunction level of the up / down (U / D) counter 7 can be increased (here, T Is the signal period of the A and B phase pulses).
[0034]
The total count of the data DI is such that the maximum response frequency is FAB (Hz) when the number of pulses within one rotation of the A and B phase signals is P (pulse / revolution) and the maximum rotation number is M (r / min). ), The signal period at this time is TAB (s), the data transfer period of the serial signal is TCYC (s), and the number of revolutions where there is no problem even if the serial signal continues to malfunction due to noise is N,
Total count> TCYC · N · 2 / TAB
(TAB = 1 / FAB = 60 / P · M · 4)
It is obtained by. By preparing the data latch circuit 12 (up / down (U / D) counter total count is ¼) having the total count of the data DI and the serial signal conversion circuit 18, the serial signal is noised N times continuously. Even if malfunction occurs due to the above, the normal value can be determined from the data before and after the serial signal receiving side.
[0035]
<Data continuity determination unit>
FIG. 4 is a timing chart showing the operation of the data continuity determination unit 24.
[0036]
The output DI of the data latch circuit 12 having the data of the up / down (U / D) counter 7 is sampled for each sampling pulse LTS of the serial signal conversion circuit 18 and output as serial data SD, and also to the data latch circuit 14. The data DB is retained. As for the output DB of the data latch circuit 14, the data at the previous serial transfer is held in the data latch circuit 15 and becomes data DA. The data comparison circuit 16 compares the output DA of the data latch circuit 15 as the previous transmission data with the output DB of the data latch circuit 14 as the current transmission data. A reference value K that is an allowable range is set in advance in the data comparison circuit 16. If the difference between the two data DB and DA is equal to or less than K, it is determined that the data has continuity. Is output as a sex signal SC. In this example, when there is no continuity (when K + 1 or more), the level is high. Thus, by selecting an appropriate value for the reference value K, the delay amount and delay time of the serial data transfer cycle TCYC can be easily predicted.
[0037]
<Origin signal normalization unit>
5 and 6 are timing charts showing the operation of the origin signal normalization unit 23. FIG. 5 shows a case where the rotation direction determination signal DIR from the rotation direction determination circuit 6 does not change, and FIG. Shows the case.
[0038]
In FIG. 5, the normal A-phase, B-phase pulse and Z-phase signal are not synchronized. However, as shown in FIG. 2, it is possible to synchronize with any of the four regions (X1, X2, X3, X4) defined by the A and B phase pulses and their phase differences. This is performed by the Z0 signal synchronization gate 10, and the Z phase signal is synchronized to become the Z0 signal. Then, the Z0 signal processing circuit 11 detects the Z0 signal using the sampling pulse LTS synchronized with the serial signal transfer cycle. Here, in the entire speed region of the encoder [example of region (1)], the Z0 signal synchronized with the detection timing of the sampling pulse LTS is defined as 2Z0. In addition, when the number of rotations is higher than a predetermined value (example of region (2)), when the series of Z0 signals detected by the sampling pulse LTS is equal to or less than the predetermined number of detections N, N + 1 sampling pulses. A signal having a signal length synchronized with LTS is defined as 1Z0. When a Z-phase signal is detected only in the gap between the sampling pulses LTS [example of region (3)], a signal having a signal length synchronized with N + 1 sampling pulses LTS from the nearest next sampling pulse LTS is set to 0Z0. It prescribes.
[0039]
The logical sum (OR) of the signals 2Z0, 1Z0 and 0Z0 thus defined is output as a Z-phase data signal Z1. Furthermore, as shown in FIG. 6, when a change in the rotational direction is detected by the rotational direction determination signal DIR even under the same operating conditions as in FIG. 5, the input condition is canceled at that time. Therefore, the signal Z1 disappears at the timing LTS of the next sampling pulse.
[0040]
A more specific configuration example of such a Z0 signal processing circuit is shown in FIG. In this example, it is constituted by a Z0 signal detection circuit 111, a detection circuit 112 or less N times, an inter-LTS detection circuit 113, an N + 1 synchronization circuit 114, an N + 1 synchronization circuit 115, a direction discrimination signal detection circuit 116, and an OR gate 117.
[0041]
The Z0 signal detection circuit 111 detects the input Z0 signal in synchronization with the LTS signal and outputs a 2Z0 signal. The N times or less detection circuit 112 outputs a 1Z01 signal when the signal length of Z0 is N times or less at the timing of LTS, and outputs it as an N + 1 signal length 1Z0 by the N + 1 synchronizing circuit 114. The inter-LTS detection circuit 113 detects the Z0 signal in the gap of the timing of the LTS signal, outputs the 0Z01 signal, and outputs the signal with the N + 1 signal length 0Z0 by the N + 1 synchronizing circuit 115. When the direction discrimination signal detection circuit 116 detects a change in the direction discrimination signal DIR, it sends a CL signal, and clears and resets the detection circuit 112 and the inter-LTS detection circuit 113 N times or less. The OR gate 117 outputs a logical sum (OR) of the above 0Z0, 1Z0 and 2Z0.
[0042]
Further, as shown in FIG. 8, the data continuity signal SC from the data comparison circuit 16 is inputted, and the output of the logical sum (OR) gate 117 via the logical negation (NOT) gate 118 is logically ANDed. The output signal Z1 can also be input to the gate 119. By doing so, the origin signal Z1 is prohibited when the continuity of the data is lost, and the origin signal Z1 having a low reliability due to the loss of continuity can be prevented from being recognized by the receiving side device. .
[0043]
As described above, even if the rotation speed is increased and the apparent signal width of the Z-phase signal is shortened or affected by noise, it is ensured by ensuring a constant signal width (N + 1). Can be recognized, and malfunction due to oversight of the origin can be prevented. Further, since the detected signal width is large in the low-speed operation, there is no problem even if it is as it is, and the accuracy can be ensured.
[0044]
<Counter clear circuit>
The counter clear circuit 13 holds the logical product (AND) or the counter clear signal CLR when the counter clear signal CLR and the Z0 signal from the Z phase signal synchronizer 10 (signal replacing the Z phase signal) are input from the outside. When the Z0 signal signal is input, the data clear signal CLD which is the logical product of the signals is output, and the data of the up / down (U / D) counter 7 is cleared to zero. As a result, when the Z phase is detected after power-on or reset, the count data DI is reset to zero, and the subsequent position data from the origin always becomes a constant value, facilitating processing on the data receiving side. Become.
[0045]
The above-mentioned incremental encoder is an optical type, but the configuration of the code signal generation unit 21 is not limited to this, and a contact type, a magnetic type, and other rotational movements are performed with a predetermined phase difference signal and 1 Any signal can be used as long as the origin signal output once per rotation can be defined. Moreover, although the said incremental encoder described as what handles A phase, B phase, and Z phase, for example, a magnetic pole position (U, V, W) is detected like an AC servomotor, and the said A phase, B phase, and The present invention can also be applied to a rotation position together with a Z-phase pulse, or a type of encoder used as a normalizing means or an auxiliary means in the case of controlling this as a sine wave signal.
[0046]
【The invention's effect】
As described above, according to the present invention, it is possible to provide an incremental encoder that prevents counting errors due to noise and that has a high response processing speed.
[0047]
In addition, it is possible to provide an incremental encoder that can easily process data received by a device on the receiving side or process data when power is turned on.
[0048]
Further, it is possible to provide an incremental encoder capable of reliably detecting and recognizing the Z phase with respect to the receiving device.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a basic configuration of an incremental encoder of the present invention.
FIG. 2 is a timing chart showing the relationship between A-phase and B-phase pulses, a Z0 signal, and a DLSB signal.
FIG. 3 is a timing chart showing an operation of a count data normalization unit.
FIG. 4 is a timing chart showing the operation of the data continuity confirmation unit.
FIG. 5 is a timing chart showing the operation of the Z0 signal processing unit when the DIR signal does not change.
FIG. 6 is a timing chart showing the operation of the Z0 signal processing unit when the DIR signal changes.
FIG. 7 is a block diagram showing a more detailed configuration of a Z0 signal processing unit.
FIG. 8 is a block diagram showing a more detailed configuration of a Z0 signal processing unit, showing a configuration example when a continuity confirmation signal is input.
FIG. 9 is a block diagram showing a configuration of a conventional incremental encoder.
10 is a timing chart showing the operation of the incremental encoder of FIG. 9;
[Explanation of symbols]
1 Light emitting element
2 Code plate
3 detector elements
4 Waveform shaping circuit
5 Power supply voltage monitoring circuit
6 Direction discrimination circuit
7 Up / Down (U / D) counter
8 Timing processing circuit
9 Code conversion circuit
10 Z0 signal processing gate
11 Z0 signal processing circuit
12 Data latch circuit
13 Counter clear circuit
14 Data latch circuit
15 Data latch circuit
16 Data comparison circuit
17 Data latch circuit
18 Serial signal conversion circuit

Claims (9)

A code signal generating unit for providing a phase difference 2 signal and an origin signal according to at least rotation of the object to be measured; and a data counting unit for counting incremental data obtained from the phase difference 2 signal from the code signal generating unit. ,
The data counting unit discriminates the rotational direction based on the phase difference 2 signal and generates a count signal for the change point of one of the signals, and the counting unit counts the count signal from the direction discriminating means. Low-order data generation means for generating low-order 2-bit data from the phase difference 2 signal, and when the time from the change point of one of the phase difference 2 signals to the next change point is equal to or longer than a predetermined time TF Timing means for providing only the read timing, and giving the weight of 3 bits or more from the least significant bit to the data of the counting means so as to be integrated with the data of the lower 2 bits, and reading this data at the read timing from the timing means An incremental encoder comprising data holding means for counting data.   2. The incremental encoder according to claim 1, wherein the predetermined time TF of the timing means has a maximum value less than a quarter period of the A-phase and B-phase pulses which are two phase difference signals. A code signal generator for providing a phase difference 2 signal and an origin signal in accordance with at least the rotation of the object to be measured; a data count unit for counting incremental data obtained from the phase difference 2 signal from the code signal generator; It has a data continuity judgment unit that judges the continuity of data when transferring data,
The data continuity determination unit compares data holding means for holding previously transferred data and data to be transferred at the present time with data transferred at the previous time obtained from the data holding means and the data to be transferred at present. Incremental encoder having data comparison means for judging whether or not the value is equal to or less than a reference value K and outputting the result.   The incremental encoder according to claim 3, wherein the data count unit is the data count unit according to claim 1.   2. The incremental encoder according to claim 1, further comprising an origin signal normalization unit that transmits the origin signal as a prescribed signal width N + 1 when a signal width of the origin signal is less than a prescribed signal width N + 1.   The origin signal normalization unit inputs Z-phase signal synchronization means for synchronizing the Z-phase signal to one of four divided areas of A and B-phase signals, and a sampling signal for transferring count data as a serial signal. 6. A Z0 signal processing means for outputting as a signal length corresponding to the predetermined number N + 1 when the number of times the output from the Z-phase signal synchronizing means is recognized by the sampling signal is equal to or less than the predetermined number N. Incremental encoder.   7. An incremental encoder according to claim 6, wherein said Z0 signal processing means inputs rotational direction data obtained from A and B phase signals, and stops sending the origin signal when the rotational direction changes.   4. The data continuity determination unit according to claim 3, wherein the origin signal normalization unit stops sending the origin signal when the output from the data continuity determination unit recognizes that there is no continuity of the transfer data. The incremental encoder according to claim 7.   Count data that clears the data of the counting means to zero when the counter clear signal CLR and the Z phase / or a signal replacing it are input from the outside, or when the Z phase / or a signal replacing it is input after the counter clear signal CLR is input The incremental encoder according to claim 1, further comprising a matching unit 13.

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