JP3720036B2 - CMOS image sensor - Google Patents

Description

    The present invention relates to a CMOS image sensor in which active pixels are arranged in a matrix on a semiconductor substrate and are XY addressed.

    An active pixel of a CMOS image sensor includes a photodiode as a light receiving element formed on a semiconductor substrate and a plurality of MOS transistors that transmit and amplify signal charges generated by irradiating the photodiode with light. A combination of pixel unit cells is used as a pixel unit by arranging a plurality of pixel unit cells in a matrix on a semiconductor substrate. Basically, for the transmission of one phototransistor, a combination of a reset transistor, an amplifying transistor and a selection transistor for row address is required.

  There is also known a structure for improving the efficiency of signal processing by using this one combination in common for a plurality of photodiodes. Usually, a sensor in which a common amplification unit is disposed in a pair of photodiodes has been put to practical use in digital cameras, mobile devices, camera-equipped mobile phones, and the like. In this structure, in order to alternately extract signal charges from a pair of photodiodes, a signal transistor is attached to each diode to perform signal switching. In addition, there is a pixel in which a timing generation circuit, a vertical line scanning circuit, a noise canceling circuit, a horizontal line scanning circuit, and a reading unit having an output amplifier are arranged in the periphery of the pixel portion (see, for example, Patent Document 1).

    Hereinafter, a conventional example will be described with reference to FIGS. FIG. 10 is a matrix arrangement diagram, FIG. 11 is a circuit diagram of the main part, and FIG. 12 is a diagram showing a layout of the main part.

    In the figure, the pixel portion 1 of the CMOS image sensor is configured by arranging a plurality of unit cells Ce in a two-dimensional matrix arrangement in a substantially regular lattice, and the pixel of one unit cell Ce has two first and second pixels. Photodiodes 12a and 12b. As shown in FIG. 11, the circuit configuration is such that the two first and second photodiodes 12a and 12b are connected to the sources of the read transistors 13a and 13b provided corresponding to the first and second photodiodes 12a and 12b, respectively. Read lines 15a and 15b for supplying a read pulse are connected to the gates 14a and 14b of the read transistors 13a and 13b, respectively.

    The drains of the read transistors 13a and 13b are formed by a common floating diffusion region 16, and the floating diffusion region 16 is connected to the gate 18 of the amplification transistor 17 and the source 20 of the reset transistor 19 by a metal wiring. . The drain 21 of the amplification transistor 17 is common with the source of the selection transistor 22, the drain 23 of the selection transistor 22 is connected to the power supply line 24, and a selection pulse is supplied to the gate 25 of the selection transistor 22. A selection line 26 is connected. Further, the source of the amplification transistor 17 is formed by a source diffusion region 27, and a signal line 28 is connected to the source diffusion region 27.

    On the other hand, the drain of the reset transistor 19 is common to the drain 23 of the selection transistor 22 of the adjacent unit cell Ce and is connected to the power supply line 24 of the reset drain voltage source. Is connected to the reset line 30.

    In addition, as shown in FIG. 12, the layout is such that only the first photodiode 12a or the second photodiode 12b, both of which are square, are arranged in the horizontal direction at a predetermined interval, and the first photodiode 12a is arranged in the vertical direction. The photodiodes 12a and the second photodiodes 12b are alternately arranged at a predetermined interval. Then, between the first photodiode 12a and the second photodiode 12b adjacent to each other in the vertical direction of the same unit cell Ce, the read lines 15a and 15b are arranged in the middle of the pattern so as to sandwich the floating diffusion region 16 therebetween. It is provided in the part so that it may extend in the horizontal direction. The read line constitutes the gates 14a and 14b of the read transistors 13a and 13b and supplies a read pulse.

    Further, on the upper side in the vertical direction of the first photodiode 12a, a reset line 30 on which a gate 29 of a reset transistor 19 to which a reset pulse is supplied is formed so as to extend in the horizontal direction with a predetermined interval. Is provided. On the other hand, on the lower side in the vertical direction of the second photodiode 12b, the gate 25 of the selection transistor 22 to which a selection pulse is supplied is formed between the second photodiode 12b and the first photodiode 12a of the adjacent unit cell on the lower side. The selection lines 26 are provided so as to extend in the horizontal direction with a predetermined interval between the reset lines 30 of the same adjacent unit cells.

    Further, a source 20 is formed below the reset line 30 serving as the gate 29 of the reset transistor 19, and a drain common to the drain 23 of the selection transistor 22 of the adjacent unit cell is formed on the upper side. A gate 18 of the amplification transistor 17 is formed in the vicinity of the second photodiode 12b between the read line 15b and the selection line 26 with the second photodiode 12b interposed therebetween. A source diffusion region 27 of the amplifying transistor 17 is formed above the gate 18 in the vertical direction, and a drain 21 of the amplifying transistor 7 that is also the source of the selecting transistor 22 is formed between the gate 18 and the selection line 26.

    Further, corresponding to the source of the select transistor 22, a select transistor that is also a drain of the reset transistor 19 of the adjacent unit cell between the select line 26 and the reset line 30 of the adjacent unit cell on the lower side in the vertical direction. 22 drains 23 are formed.

    In each unit cell of the pattern configured as described above, an Al wiring is connected to the drain 23 of the selection transistor 22 which is also the drain of the reset transistor 19 of each unit cell arranged in the vertical direction. A power line 24 is wired. Similarly, to the source diffusion region 27 of the amplification transistor 17 of each unit cell Ce arranged in the vertical direction, a signal line 28 that outputs a signal read by a read pulse is connected to each other by an Al wiring. Are wired like so.

Further, for each unit cell Ce, for example, the floating diffusion region 16 and the gate 18 of the amplification transistor 17 are connected to the floating diffusion region 16, the gate 18 of the amplification transistor 17, and the source 20 of the reset transistor 19, respectively. A connection line 31 for connecting the floating diffusion region 16 and the connection line 32 for connecting the source 20 of the reset transistor 19 are wired by Al wiring. The gates 14a, 14b, 18, 25, and 29 of the transistors 13a, 13b, 17, 19, and 22 are made of polycrystalline silicon.
US Pat. No. 6,019,449

  However, in the above prior art, one unit cell Ce is composed of the first photodiode 12a and the second photodiode 12b, the read transistors 13a and 13b, the amplification transistor 17, the reset transistor 19, and the selection transistor 22. On the other hand, the readout lines 15a and 15b, the selection line 26, and the reset line 30 are formed so as to be laid out on the same plane, and the power supply line 24, the signal line 28, and the connection lines 31 and 32 must be provided by Al wiring. It was. For this reason, the area of the first photodiode 12a and the second photodiode 12b is only about 20% to 30% of the entire area of the unit cell Ce, and high integration is achieved in order to improve the resolution of the sensor. When trying to do so, it is difficult to realize it, and there is a limit in terms of resolution improvement. Further, the readout line 15 a and the connection line 32 intersect to form an intersection 40.

  On the other hand, the presence of the source portion 20 and the connection line 32 of the reset transistor in addition to the floating diffusion layer 16 leads to an increase in capacitance, and a change in signal output with respect to the amount of signal charge, that is, an amplifier gain is reduced. It became an obstacle to realization.

    The present invention has been made in view of the above situation, and its object is to efficiently arrange the elements and wirings constituting the unit cell, and to make the elements and wirings particularly small or thin. It is an object of the present invention to provide a CMOS image sensor that can be highly integrated without increasing the resolution and improve the resolution and the like.

A CMOS image sensor of one embodiment of the present invention includes:
In a CMOS image sensor in which a plurality of unit cells composed of a photodiode and a plurality of MOS transistors are arranged in a matrix on a semiconductor substrate,
The unit cell includes first and second photodiodes formed on a semiconductor substrate, a first readout transistor connected to the first photodiode for reading out the signal charge, and a signal charge connected to the second photodiode. A second read transistor for reading, a floating diffusion region connected to the first and second read transistors for transmitting signal charges, a reset transistor connected to the floating diffusion region for resetting the potential of the region, and the floating transistor An amplification transistor having a gate connected to the diffusion region and amplifying the signal charge, and a selection transistor for selectively addressing the amplification transistor,
Each of the unit cells is coupled to a read line of the first and second read transistors, a reset line of the reset transistor, and a select line of the select transistor, which are four gate lines extending in the horizontal direction of the matrix arrangement, respectively. And
The unit cells extend in the vertical direction of the matrix arrangement and are coupled to a power supply line connected to the reset transistor and the selection transistor and a signal line connected to the amplification transistor,
The gate line extends in a double wiring layer every two lines,
The first and second photodiodes are spaced apart from each other across a read line of the first and second read transistors;
The floating diffusion region has a substantially rectangular shape,
The first and second read transistors and the reset transistor are connected to each side of the floating diffusion region in a semiconductor substrate.

  As described above, a pair of readout transistor and reset transistor are directly coupled with a common rectangular floating diffusion region, and the gate line is formed as a double layer wiring, thereby expanding the photodiode area and improving the efficiency of the unit cell and the wiring. The arrangement can be measured.

A CMOS image sensor according to another aspect of the present invention includes a pair of photodiodes, a pair of readout transistors connected to the photodiodes for reading out signals of the photodiodes, an amplification transistor for amplifying the signals, and the signal In a CMOS image sensor, in which a plurality of unit cells each having a reset transistor for resetting and a selection transistor for selecting the amplification transistor are arranged in a matrix at a predetermined pitch two-dimensionally in the vertical and horizontal directions.
The two photodiodes of the unit cell are spaced apart from each other in the vertical direction of the matrix arrangement, and the paired readout transistors are arranged between the paired photodiodes and have a common floating diffusion region serving as a drain. And
The floating diffusion region is substantially rectangular;
The reset transistor is provided directly adjacent to the floating diffusion region;
Read lines constituting the respective gates of the read transistors corresponding to the photodiodes are arranged to face each other so as to sandwich the floating diffusion region from both sides in the vertical direction,
The amplification transistor, the reset transistor, and the selection transistor are formed in a region sandwiched between the readout lines of the paired readout transistors.

  The gates of the readout transistors corresponding to the photodiodes of the unit cell are arranged to face each other so as to sandwich a substantially square floating diffusion region provided between the photodiodes from both sides in the vertical direction. Alternatively, the gates of the read transistors corresponding to the photodiodes of the unit cell are provided so as to be orthogonal to each other along adjacent sides of a substantially square floating diffusion region provided in common to the photodiodes. A reset transistor is provided directly adjacent to the floating diffusion region without going through an intermediate wiring.

  As described above, the unit cell and the wiring can be efficiently arranged by directly coupling the pair of read transistor and reset transistor in the common rectangular floating diffusion region.

  According to the present invention, elements, wirings, and the like constituting the unit cell can be efficiently arranged, can be highly integrated, can improve the photodiode area by 30% or more, and have a charge-voltage conversion gain. As a result, the dynamic gain can be increased and a highly sensitive sensor can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the part of the same code | symbol in each figure shows the same part.

  A first embodiment will be described with reference to FIGS. FIG. 1 shows a matrix diagram in which a plurality of unit cells Ce1 are arranged on a semiconductor substrate, R1 and R2 show read transistor gate regions for reading out signal charges of photodiodes 52a and 52b when read pulses R1 and R2 are applied, The reset transistor gate portion RS, the amplification transistor, and the selection transistor portion AMP are connected to this.

  In the figure, Y Driver CKT (R1, R2), which is a peripheral circuit that generates read pulses R1, R2 on the left side in the horizontal direction of the matrix, and a peripheral circuit Y Driver CKT (RS, ADD), which generates reset pulses and address pulses, on the right side of the figure. ) Respectively. A peripheral circuit READ CKT for sequentially reading signal line information in the vertical direction of the matrix on the lower side of the figure is shown.

  In the horizontal direction X of the matrix, first and second read lines 54a and 54b to which a read pulse is applied, a reset line 69 to which a reset pulse is applied, and a selection line 65 to which an address pulse is applied extend. These lines are gate lines that control the gate of each transistor. Further, power supply lines 68 and signal lines 62 extend in the vertical direction Y of the matrix. The unit cell Ce1 is coupled to four gate lines 54a, 54b, 65, 69 extending in the horizontal direction and a power supply line 68 and signal line 62 extending in the vertical direction.

  In this embodiment, the RS portion exists between the read lines 54a and 54b, and there is no crossing portion between the read lines.

  In the figure, the pixel portion 101 of the CMOS image sensor is configured by arranging a plurality of unit cells Ce1 in a matrix in a horizontal and vertical two-dimensional substantially regular lattice on a semiconductor substrate. Is composed of two first and second photodiodes 52a and 52b.

  In the present embodiment, the first read line 54a of the first read transistor 53a and the reset line 69 of the reset transistor 59 are stacked as the double wiring layer 104 via the interlayer insulating layer 103 (FIG. 4). Further, the second read line 54b of the second read transistor 53b and the select line 65 of the select transistor 62 are stacked as a double wiring layer 105 via the interlayer insulating layer 103 (FIG. 4).

  As shown in FIG. 3, in the layout, these double wiring layers 104 and 105 extend in the horizontal direction of the matrix arrangement and are arranged in parallel. The photodiodes 52a and 52b are arranged outside these wiring layers, and are positioned so as to sandwich the first and second read transistors 53a and 53b and the double wiring layers 104 and 105 inside. In addition, the floating diffusion region 56, the reset transistor 59, the amplification transistor 57, and the selection transistor 62 connected to the drains of the first and second read transistors are disposed in the inner region of the double wiring layer.

  The floating diffusion region 56 has a rectangular shape, and the drains of the first and second read transistors 53a and 53b are respectively connected to two sides 56a and 56b facing each other among the four sides of this region. Further, the source of the reset transistor 59 is connected to one side sandwiched between the two sides 56a and 56b.

    More specifically, as shown in FIG. 2, the two first and second photodiodes 52a and 52b of each unit cell are provided with read transistors 53a and 53b, respectively, and their sources are connected. The The gates of the read transistors 53 a and 53 b also serve as read lines 54 a and 54 b for supplying a read pulse, respectively. The drains of the read transistors 53 a and 53 b are formed by a common floating diffusion region 56. An amplification transistor 57, a reset transistor 59, and a selection transistor 62 are provided in common for the two first and second photodiodes 52a and 52b.

    Further, as shown in FIG. 3, only the first photodiode 52a or the second photodiode 52b having a rectangular shape that is long in the horizontal direction in the unit cell is arranged in the horizontal direction at a predetermined interval. . In the vertical direction, a predetermined interval is provided between the first photodiode 52a and the second photodiode 52b of the same unit cell. Arranged so that the first photodiode 52a and the second photodiode 52b are alternately positioned so that the first photodiode 52a and the second photodiode 52b of the adjacent unit cells in the horizontal direction are adjacent to each other. May be.

    Between the first photodiode 52a and the second photodiode 52b, the first readout line 54a and the second readout line 54b extend in common to the unit cells Ce1 of each column arranged in the horizontal direction of the matrix arrangement. Yes. The first read line 54a is the gate line of the read transistor 53a on the first photodiode 52a side. The second read line 54b is a gate line of the read transistor 53b on the second photodiode 52b side. The read lines 54a and 54b are made of polycrystalline silicon, and read line ends 55a and 55b for supplying a read pulse are connected to the read lines 54a and 54b, respectively.

    Further, between the gate (first read line) 54a of the read transistor 53a and the gate (second read line) 54b of the read transistor 53b, a substantially rectangular floating diffusion region 56 in order in the horizontal direction, and an element isolation region F. A substantially square source diffusion region 67 of the amplification transistor 57 is arranged at a predetermined interval. A rectangular gate 58 of the amplifying transistor 57 is disposed adjacent to the source diffusion region 67, and a rectangular drain 61 of the amplifying transistor 57 is disposed adjacent to the gate 58. Further, a predetermined interval is provided between the drain 61 region as a source. Thus, a square drain 63 of the selection transistor 62 is disposed for each unit cell Ce1.

    On the other hand, the gate (first read line) 54a of the read transistor 53a and the gate (second read line) 54b of the read transistor 53b are used as lower layers, and the reset transistor 59 formed of polycrystalline silicon is formed on the upper layer of these layers. The reset line 69 connected to the gate 69a and the selection line 65 connected to the gate 65a of the selection transistor 62 extend in the horizontal direction by providing an interlayer insulating layer between the respective readout lines. . Further, the gate 69a of the reset transistor 59 is formed so as to protrude from the reset line 69, and between the drain 63 of the selection transistor 62 of the unit cell Ce1 adjacent to the floating diffusion region 56 in the horizontal direction or the drain 63 of the selection transistor 62. Arranged between floating diffusion regions 56 of unit cells Ce1 adjacent in the horizontal direction.

    The gate 65 a of the selection transistor 62 is formed so as to protrude from the selection line 65 and is disposed between the drain 61 of the amplification transistor 57 and the drain 63 of the selection transistor 62. The reset line 69 has a reset line terminal 70 for supplying a reset pulse connected to the end of the reset line, and the selection line 65 has a selection line terminal 65a for supplying a selection pulse. It is connected to the.

    Each unit cell Ce1 having the layout configured as described above is directly wired with a power supply line 64 of Al wiring in the vertical direction. The drain of the reset transistor 59 of the unit cell Ce1 and the drain 63 of the selection transistor 62 are common, and the power supply line 64 connects the unit cells to each other in column units. A signal line 68 for outputting a signal read by a read pulse is connected to the source diffusion region 67 of the amplification transistor 57 of each unit cell Ce1 arranged in a column in the vertical direction by an Al wiring. ing. Further, for each unit cell Ce1, a connection line 73 that connects the floating diffusion region 56 and the gate 58 of the amplification transistor 57 is wired by an Al wiring.

    In the above description, as shown in FIG. 4, the gate 58 of the amplification transistor 57 is in the same layer as the gates 54a and 54b of the read transistors 53a and 53b, or the gate 69a of the reset transistor 59 and the selection transistor 62. The gate 65a may be formed of the same polycrystalline silicon, or may be formed of different polycrystalline silicon layers or metal layers as different layers.

  As a modification of this embodiment, as shown in FIG. 6, the selection line 65 and the reset line 69 may be passed through the gaps between the photodiodes 52a and 52b of the unit cells adjacent vertically as the double layer wiring 106.

    Based on the drive pulse waveform shown in FIG. 5, the cross-sectional view taken along the line AA ′ of FIG. 3 shown in FIG. 4, and the potential well change diagram at each location shown in FIG. 4. explain.

  FIG. 5 shows respective read pulses R1, R2 applied to the gates (read lines) of the read transistors 53a, 53b, a reset pulse waveform RS (69) applied to the reset line 69 applied to the gate 69a of the reset transistor, The timing chart of the address pulse waveform ADD (65) applied to the selection line 65 applied to the gate 65a of the selection transistor is shown.

    In FIG. 4, a metal wiring 73 is drawn as a connection line from the photodiodes 52 a and 52 b and the floating diffusion region 56 provided by diffusion on the semiconductor substrate 100 to the gate 58 of the amplification transistor 57.

  In the figure, the change of the potential well is described corresponding to each part. The amount of change in potential well change corresponding to each of the high level H and low level L of the pulse waveform is indicated by arrows.

  As a driving method, first, the reset pulse (RS (69)) applied to the gate 69a of the reset transistor is set to high level, and the potential of the floating diffusion region 56 is reset to the drain potential (constant potential) of the reset transistor (T1). ). Next, the high level of the address pulse (ADD (65)) is applied to the gate 65a of the selection transistor, and the potential of the source diffusion region 67 before the transfer of the signal charge from the photodiode 52a is detected (T2).

  Next, the read pulse (R1 (54a)) applied to the gate 54a of the read transistor is set to the high level, and the signal charge is transferred from the photodiode 52a to the floating diffusion region 56 (T3). This potential change in the floating diffusion region 56 is transmitted to the gate 58 of the amplification transistor via the connection line 73, and when the address pulse applied to the gate 65a of the selection transistor becomes high level, the potential of the source diffusion region 67 changes ( T4). At this time, the noise component of the output circuit is suppressed by taking the difference from the state without the signal charge. Next, the high level of the reset pulse is applied again to the gate 69a of the reset transistor, and the potential of the floating diffusion region 56 is reset again to the drain potential (constant potential) of the reset transistor (T5).

  Similarly, the signal charge of the photodiode 52b is read by the read pulse (R2 (54b)).

  Further, the signal charges are also read out from the first and second photodiodes 52a and 52b of the unit cells Ce1 horizontally adjacent to each other in the third line and the fourth line of the pixel column. This is performed in the same manner as the first line and the second line with the diffusion region 56 in common. Further, by repeating the same operation for each subsequent line, reading is performed for all the first and second photodiodes 52a and 52b which are pixels of the pixel unit 101.

  The floating diffusion region 56 is further provided between the gates 54a and 54b of the read transistors 53a and 53b which are configured as described above and are arranged to face each other between the read transistors 53a and 53b, and adjacent to the floating diffusion region 56. Since the reset transistor 59 for resetting the signal to a predetermined potential after reading the signal is provided, the floating diffusion region 16 and the source 20 of the reset transistor 19 required in the conventional layout (FIGS. 10 to 12) are connected. The connection line 32 becomes unnecessary. As a result, the output circuit in the unit cell Ce1 can be highly integrated, the sensor as a whole can be highly integrated, and the resolution can be improved.

  On the other hand, according to the present embodiment, the source of the reset transistor and the connection line 32 (FIG. 12) for connecting the reset transistor in the conventional device are not necessary, so that the change in the signal output with respect to the signal charge amount, that is, the amplifier gain can be controlled. It offers the advantage of improving over. This increase in amplifier gain reaches approximately 30%.

  Further, the first photodiode 52a and the second photodiode 52b are formed in a long rectangular shape, arranged in the horizontal direction with a predetermined interval determined by the width of the element isolation region therebetween, and the first photodiode 52a and the second photodiode 52b in the vertical direction. Since a common output circuit is arranged for each unit cell Ce1 between the photodiode 52a and the second photodiode 52b, the width of the inter-photodiode element isolation region is substantially halved when viewed in units of each photodiode. As a result, the areas of the first photodiode 52a and the second photodiode 52b can be increased, and the space factor with respect to the entire area of the unit cell Ce1 can be increased.

    The horizontal width of the read floating diffusion region 56 is sufficiently small as shown in FIG. 3 with respect to the horizontal width of the photodiode 52a, and only the element isolation region exists in the gap between the photodiodes in the horizontal direction. Therefore, as shown in FIG. 6, the photodiodes 52a can be shifted from each other in the horizontal direction X with respect to the vertically adjacent photodiodes 52b. This facilitates a layout that improves the resolution by shifting the pixels in a checkered pattern.

  Next, a second embodiment will be described with reference to FIGS. FIG. 7 shows a matrix diagram, R1 and R2 indicate read transistor gate regions of the photodiode to which the read pulses R1 and R2 are applied, RS indicates a reset transistor gate portion, and AMP indicates an amplifying transistor and a select transistor portion.

  In the figure, the peripheral circuit Y DriverCKT (R1, R2) for generating the read pulses R1 and R2 is shown on the left side, and the peripheral circuit Y DriverCKT (RS, AMP) for generating the reset pulse and the address pulse is shown on the right side of the figure. A peripheral circuit READ CKT for sequentially reading signal line information is shown on the lower side of the figure.

  In the embodiment of FIG. 7, the RS section bypasses the readout line 54a, thereby eliminating the intersection.

  In FIG. 8, FIG. 9A, and FIG. 9B, the pixel unit 201 of the CMOS image sensor is configured by arranging a plurality of unit cells Ce2 in a two-dimensional matrix, and one unit cell Ce2 has two first and second pixels. 2 photodiodes 52a and 52b, which are the same as the circuit configuration shown in FIG.

  That is, the two first and second photodiodes 52a and 52b of each unit cell Ce2 are provided with corresponding read transistors 53a and 53b, and the gates 54a and 54b of the read transistors 53a and 53b Read line terminals 55a and 55b for supplying read pulses are connected. The drains of the read transistors 53 a and 53 b are formed by a common floating diffusion region 56. An amplification transistor 57, a reset transistor 59, and a selection transistor 62 are provided in common for the two first and second photodiodes 52a and 52b.

  Further, as shown in FIG. 9A, the layout is such that only the first photodiode 52a or the second photodiode 52b having a parallelogram shape is arranged in the horizontal direction at a predetermined interval, and in the vertical direction. The first photodiode 52a and the second photodiode 52b are arranged so as to be alternately positioned with a predetermined interval therebetween. Both the first photodiode 52a and the second photodiode 52b that are arranged have their long sides positioned in the horizontal direction. For example, in the first photodiode 52a, the lower long side is positioned to the left of the upper long side, and in the second photodiode 52b, the lower long side is to the right of the upper long side. The lower long side 521a of the first photodiode 52a and the upper long side 521b of the second photodiode 52b in the same unit cell Ce2 face each other at a predetermined interval in the vertical direction. are doing.

  Between the first photodiode 52a and the second photodiode 52b in the same unit cell Ce2, between the opposing long sides 521a and 521b of the photodiodes 52a and 52b, and between the adjacent unit cells Ce2 A first double layer gate line 202 extending in the horizontal direction is provided therebetween. The gate line 202 has a first V-shaped portion 74a that is bent at a substantially right angle and protrudes downward in the vertical direction. An interlayer insulating layer is provided between the gate 54a of the read transistor 53a formed of polycrystalline silicon in the lower layer of the double layer structure, and the gate 54b of the read transistor 53b also formed of polycrystalline silicon is formed on the upper layer. Each of the adjacent unit cells Ce2 extends in the horizontal direction so as to be provided in the same manner.

  On the other hand, a second double layer gate line 203 extending in the horizontal direction X is provided between the unit cells Ce2 adjacent in the vertical direction. The second double layer gate line is provided between the lower long side 521b of the second photodiode 52b and the upper long side 521a of the first photodiode 52a of the adjacent unit cell Ce2. The gate line 203 forms a horizontal portion along both long sides of the diode and a second V-shaped portion 74b that is bent at a substantially right angle and protrudes downward in the vertical direction between the adjacent unit cells Ce2. ing.

  A gate 69 of the reset transistor 59 formed of polycrystalline silicon is disposed in the lower layer of the double layer structure, and a gate 65 of the selection transistor 62 also formed of polycrystalline silicon is disposed in the upper layer via an interlayer insulating layer therebetween. The unit cells Ce2 extending in the horizontal direction extend in the same manner.

  Thereby, a first partition portion 75a where the floating diffusion region 56 is disposed and a second partition portion 75b where the amplification transistor 57 is disposed are formed. The first partition portion 75a includes a first V-shaped portion 74a, a second V-shaped portion 74b, a right short side of the first photodiode 52a, and a right short side of the second photodiode 52b. It is formed in a substantially square shape. Further, this portion is formed adjacent to the right side of the first photodiode 52a in the horizontal direction. The second partition portion 75b is formed on the right side in the horizontal direction of the second photodiode 52b with the first V-shaped portion 74a interposed therebetween.

  Furthermore, the gate 54a of the read transistor 53a is perpendicular to the right short side of the first photodiode 52a from the opening end of the first V-shaped portion 74a toward the inside of the first partition portion 75a. The protruding portion 76 extends at the same depth as the gate 54a. As for the gate 69 of the reset transistor 59, a protruding portion 77 is formed from the horizontal portion toward the inside of the first partition portion 75a so that the root portion is at a right angle and the tip portion is orthogonal to the protruding portion 76 of the gate 54a. And the same depth as the gate 69. Note that the protruding portion 76 of the gate 54a and the protruding portion 77 of the gate 69 are formed at different depths by providing an interlayer insulating layer therebetween.

  Corresponding read line terminals 55a and 55b for supplying a read pulse are connected to the gates 54a and 54b of the read transistors 53a and 53b. A reset line 69 for supplying a reset pulse is connected to the gate 77 of the reset transistor 59, and the gate of the selection transistor 62 is formed by a selection line 65 for supplying a selection pulse.

  Further, a rectangular floating diffusion region 56 and a drain 63 of a trapezoidal selection transistor 62 are arranged in the first partition portion 75a so as to sandwich a protruding portion 77 that forms the gate of the reset transistor 59.

  As shown in an enlarged view in FIG. 9B, in the rectangular floating diffusion region, the first to fourth sides 56c, 56d, 56e, and 56f are arranged in a direction of approximately 45 ° with respect to the horizontal direction X of the matrix arrangement. The Furthermore, the gates 76 and 54b of the first and second read transistors are arranged along the adjacent first side 56c and second side 56d and so as to be orthogonal to each other. A protruding portion 77 of the gate 69 of the reset transistor 62 is disposed opposite to the fourth side 56f. An amplification transistor 57 is arranged in the direction of the third side 56e, and a metal wiring 73 is drawn from the floating diffusion region 56 to the gate 58 of the amplification transistor.

  Further, in the second partition portion 75b, the rectangular source diffusion region 67 and the rectangular shape are formed so as to sandwich the gate 58 of the rectangular amplification transistor 57 parallel to the left short side of the second photodiode 52b. A drain 61 of the amplification transistor 57 is disposed.

  Then, each unit cell Ce2 of the layout configured as described above is mutually connected to the drain 63 of the selection transistor 62 that is also the drain of the reset transistor 59 of each unit cell Ce2 arranged in the vertical direction Y. A power supply line 64 made of Al wiring is directly wired so as to be connected. Similarly, to the source diffusion region 67 of the amplification transistor 57 of each unit cell Ce2 arranged in the vertical direction, a signal line 68 for outputting a signal read by a read pulse is connected by an Al wiring. Are wired like so. Further, for each unit cell Ce2, a connection line 73 that connects the floating diffusion region 56 and the gate 58 of the amplification transistor 57 is wired by an Al wiring.

  As described above, the gate 54a of the read transistor 53a and the gate 54b of the read transistor 53b are formed in the double layer wiring 202 in two upper and lower layers and extended in the horizontal direction X, and the gate 69 of the reset transistor 59 and the gate of the selection transistor 62 are formed. Similarly, the upper and lower double-layer wirings 203 are extended in the horizontal direction X. Further, the gate lines 54a and 54b and the gate lines 65 and 69 stacked in two upper and lower layers are alternately arranged in the vertical direction Y. Further, only the first photodiode 52a or the second photodiode 52b having a parallelogram shape is arranged in the horizontal direction while being alternately arranged in the unit cell. By alternately arranging in the vertical direction, the area of the first photodiode 52a and the second photodiode 52b can be increased, and the space factor with respect to the entire area of the unit cell Ce2 can be increased.

  In addition, the first and second V-shaped portions 74a, which are bent at substantially right angles for each unit cell Ce2, are provided to the gates 54a, 54b, 69, 65 of the read transistor 53a, 53b, the reset transistor 59, and the selection transistor 62, respectively. 74b is formed, and first and second partition portions 75a and 75b are provided, and the floating diffusion region 56 common to the two read transistors 53a and 53b and the gate 58 of the amplification transistor 57 are provided in the partition portions 75a and 75b. Etc. are arranged. At this time, since the rectangular floating diffusion region 56 is disposed in a state inclined by approximately 45 ° with respect to the horizontal direction, the width in the vertical direction is reduced by about 0.7 times.

  Thereby, the arrangement interval in the vertical direction between the first photodiode 52a and the second photodiode 52b is the width of the element isolation region in the adjacent unit cell Ce2, stacked read transistors 53a and 53b, reset transistor 59, It is determined only by the width of each gate 54a, 54b, 69, 65 of the selection transistor 62, and high integration in the vertical direction is possible.

  Further, a floating diffusion region 56 is provided in the first and second partition portions 75a and 75b, and a reset transistor 59 is provided adjacent to the floating diffusion region 56 to reset it to a predetermined potential after reading a signal. Therefore, the connection line connecting the floating diffusion region 56 and the source 60 of the reset transistor 59, which is necessary in the conventional layout, becomes unnecessary. With such a configuration, the output circuit in the unit cell Ce2 can be highly integrated, the sensor as a whole can be highly integrated, and the resolution can be improved.

When the embodiment of the present invention is compared with a conventional apparatus using a matrix diagram,
The characteristic feature of the conventional device shown in FIG. 10 is that the readout line 15a forms an intersection 40 between the floating diffusion region and the RS as shown by the dotted line in FIG. As indicated by 12, the source region 20 of the reset transistor and the connection line 32 are required.

  In the matrix diagram of the present embodiment shown in FIG. 7, the readout line can be bypassed, thereby eliminating the intersection.

1 is a schematic circuit diagram showing a matrix according to a first embodiment of the present invention. The circuit diagram of the unit cell of the 1st Embodiment of this invention. The top view which shows the layout of the principal part of the 1st Embodiment of this invention. FIG. 4 is a schematic cross-sectional view taken along the line A-A ′ of FIG. 3 for explaining the first embodiment and describing a potential well diagram. FIG. 6 is a pulse waveform diagram for explaining the operation of the first embodiment. The circuit diagram which shows the modification of 1st Embodiment. The circuit schematic which shows the matrix in the 2nd Embodiment of this invention. The circuit diagram of the unit cell of the 2nd Embodiment of this invention. The top view which shows the layout of the principal part of the 2nd Embodiment of this invention. The principal part enlarged plan view of FIG. 9A. The circuit schematic which shows the matrix of the conventional apparatus. The circuit diagram of the unit cell of a conventional apparatus. The top view which shows the layout of the principal part of a conventional apparatus.

Explanation of symbols

52a, 52b: Photodiode 53a, 53b: Read transistor 54a, 54b: Read transistor gate (read line)
56: floating diffusion region 57: amplification transistor 58: gate of amplification transistor 59: reset transistor 60: source of reset transistor 61: drain of amplification transistor, source of selection transistor 62: selection transistor 63: drain of selection transistor, reset transistor Drain 64: Power line 65: Selection line 65a: Gate of selection transistor 67: Source diffusion region 68: Signal line 69: Reset line 69a: Gate of reset transistor 73: Connection line 101, 201: Pixel portion
Ce1, Ce2: Unit cell

Claims (4)

In a CMOS image sensor in which a plurality of unit cells composed of a photodiode and a plurality of MOS transistors are arranged in a matrix on a semiconductor substrate,
The unit cell includes first and second photodiodes formed on a semiconductor substrate, a first readout transistor connected to the first photodiode for reading out the signal charge, and a signal charge connected to the second photodiode. A second read transistor for reading, a floating diffusion region connected to the first and second read transistors for transmitting signal charges, a reset transistor connected to the floating diffusion region for resetting the potential of the region, and the floating transistor An amplification transistor having a gate connected to the diffusion region and amplifying the signal charge, and a selection transistor for selectively addressing the amplification transistor,
The unit cells are four address lines respectively extending in the horizontal direction of the matrix arrangement, the read lines of the first and second read transistors, the reset lines of the reset transistors and the select lines of the selection transistors, A power supply line extending in a vertical direction of the matrix arrangement and connected to the reset transistor and the selection transistor and a signal line connected to the amplification transistor,
The address lines extend in a double layer every two lines,
The first and second photodiodes are spaced apart from each other across a read line of the first and second read transistors;
A CMOS image sensor in which the first and second read transistors and the reset transistor are connected to the floating diffusion region in a semiconductor substrate. The floating diffusion region has a substantially square shape, and the first to fourth sides are arranged in a direction of about 45 ° with respect to the horizontal direction of the matrix arrangement, along the adjacent first side and second side. The gates of the first and second read transistors are arranged so as to be orthogonal to each other, the gate of the reset transistor is arranged opposite to the third side, and the amplification transistor is arranged in the direction of the fourth side The CMOS image sensor according to claim 1, wherein a metal wiring is drawn from the floating diffusion region to a gate of the amplification transistor. A pair of two photodiodes, a pair of readout transistors individually connected to the photodiodes for reading out photodiode signals, an amplification transistor for amplifying the signals, a reset transistor for resetting the signals, and the amplification transistor are selected. A plurality of unit cells each including a selection transistor are arranged in a matrix in a substantially lattice pattern at a predetermined pitch two-dimensionally in a vertical direction and a horizontal direction, and the pair of read transistors, the reset transistors, and the selection transistors In the CMOS image sensor in which each gate is formed by a gate line extending in the horizontal direction of the matrix arrangement,
  At least two of the gate lines overlap in the layer direction to form a double wiring layer,
  The two photodiodes of the unit cell are spaced apart in the vertical direction of the matrix arrangement, and the paired readout transistors have a floating diffusion region in common as a drain and are arranged between the two photodiodes.
  A CMOS image sensor, wherein the reset transistor is provided directly adjacent to the floating diffusion region. A pair of two photodiodes, a pair of readout transistors individually connected to the photodiodes for reading out photodiode signals, an amplification transistor for amplifying the signals, a reset transistor for resetting the signals, and the amplification transistor are selected. In a CMOS image sensor in which a plurality of unit cells each including a selection transistor are arranged in a matrix in a substantially lattice shape at a predetermined pitch two-dimensionally in a vertical direction and a horizontal direction,
  The two photodiodes of the unit cell are spaced apart from each other in the vertical direction of the matrix arrangement, and the paired readout transistors are arranged between the two photodiodes, the source is connected to the photodiode, and becomes the drain Having a floating diffusion region in common,
  The reset transistor is provided directly adjacent to the floating diffusion region;
  The readout lines constituting the respective gates of the readout transistors corresponding to the respective photodiodes are arranged to face each other so as to sandwich the floating diffusion region from both sides in the vertical direction.
  A CMOS image sensor, wherein the amplification transistor, the reset transistor, and the selection transistor are formed in a region sandwiched between the readout lines of the paired readout transistors.

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