JP3713876B2 - 論理回路接続装置 - Google Patents

論理回路接続装置 Download PDF

Info

Publication number
JP3713876B2
JP3713876B2 JP07307297A JP7307297A JP3713876B2 JP 3713876 B2 JP3713876 B2 JP 3713876B2 JP 07307297 A JP07307297 A JP 07307297A JP 7307297 A JP7307297 A JP 7307297A JP 3713876 B2 JP3713876 B2 JP 3713876B2
Authority
JP
Japan
Prior art keywords
instruction
transfer
logic circuit
data
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP07307297A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10269190A (ja
JPH10269190A5 (enExample
Inventor
英也 明石
亨 庄内
俊夫 大河内
俊明 垂井
康行 岡田
宏一 岡澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP07307297A priority Critical patent/JP3713876B2/ja
Publication of JPH10269190A publication Critical patent/JPH10269190A/ja
Publication of JPH10269190A5 publication Critical patent/JPH10269190A5/ja
Application granted granted Critical
Publication of JP3713876B2 publication Critical patent/JP3713876B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Multi Processors (AREA)
  • Bus Control (AREA)
JP07307297A 1997-03-26 1997-03-26 論理回路接続装置 Expired - Fee Related JP3713876B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07307297A JP3713876B2 (ja) 1997-03-26 1997-03-26 論理回路接続装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07307297A JP3713876B2 (ja) 1997-03-26 1997-03-26 論理回路接続装置

Publications (3)

Publication Number Publication Date
JPH10269190A JPH10269190A (ja) 1998-10-09
JPH10269190A5 JPH10269190A5 (enExample) 2005-02-24
JP3713876B2 true JP3713876B2 (ja) 2005-11-09

Family

ID=13507770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07307297A Expired - Fee Related JP3713876B2 (ja) 1997-03-26 1997-03-26 論理回路接続装置

Country Status (1)

Country Link
JP (1) JP3713876B2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4679601B2 (ja) * 2008-04-16 2011-04-27 エヌイーシーコンピュータテクノ株式会社 パケット制御回路、パケット処理装置、および、パケット処理方法

Also Published As

Publication number Publication date
JPH10269190A (ja) 1998-10-09

Similar Documents

Publication Publication Date Title
CA2051222C (en) Consistent packet switched memory bus for shared memory multiprocessors
US7120755B2 (en) Transfer of cache lines on-chip between processing cores in a multi-core system
CA2051029C (en) Arbitration of packet switched busses, including busses for shared memory multiprocessors
US5265235A (en) Consistency protocols for shared memory multiprocessors
KR100360064B1 (ko) 고도로파이프라인된버스구조
JP3832833B2 (ja) 情報処理方法および装置
US5919254A (en) Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
CN105095254B (zh) 一种实现数据一致性的方法及装置
TW417047B (en) Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency
CA2068580A1 (en) Scientific visualization system
KR980010805A (ko) 범용 컴퓨터 구조용 프로세서 서브시스템
CA2051209C (en) Consistency protocols for shared memory multiprocessors
KR980010806A (ko) 각종 프로세서와 버스 프로토콜에 적응 가능한 범용 구조를 제공하는 컴퓨터 시스템
WO1998032063A2 (en) Method and apparatus for zero latency bus transactions
EP3644190B1 (en) I/o coherent request node for data processing network with improved handling of write operations
US6892283B2 (en) High speed memory cloner with extended cache coherency protocols and responses
US20040111576A1 (en) High speed memory cloning facility via a source/destination switching mechanism
US20040111575A1 (en) Dynamic data routing mechanism for a high speed memory cloner
EP1367499A1 (en) Compute node to mesh interface for highly scalable parallel processing system
US8359419B2 (en) System LSI having plural buses
KR980010804A (ko) 프로세서와 고성능 시스템 버스간의 신호처리 프로토콜 변환 장치
US7043612B2 (en) Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data
US5586274A (en) Atomic operation control scheme
JP3713876B2 (ja) 論理回路接続装置
US7502917B2 (en) High speed memory cloning facility via a lockless multiprocessor mechanism

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040322

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040322

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20040322

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050106

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050308

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050509

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050802

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050815

LAPS Cancellation because of no payment of annual fees