JP3706656B2 - Image processing method and apparatus - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an image processing method and apparatus for rendering a rotated bitmap image of 90 ° × n (n = 1, 2, 3) with respect to an image in an arbitrary region of a given bitmap by a processor software. It is about.
[0002]
[Prior art]
Conventionally, a bitmap rotation method for drawing a rotated bitmap image of 90 ° × n (n = 1, 2, 3) with respect to an image in an arbitrary region of a given bitmap by processor software is as follows. There was a system like this. Hereinafter, the rotation angle represents the rotation angle in the counterclockwise direction, and the bit 7 side is the left pixel unless otherwise specified.
[0003]
FIG. 5 is an excerpt of the main part of the conventional 90 ° rotation.
[0004]
The rotation process uses 8 bytes of 1 byte × 8 lines (8 × 8 pixels) as a unit of processing. In the figure, p_from / p_to are input / output pointers of the respective blocks to be processed, and indicate addresses biased by n bytes by the index [n]. For example, p_from [2] indicates an address advanced by 2 bytes from p_from [0]. row_from / row_to is the number of bytes per line of the image before and after rotation, and work is a work variable for rotation processing.
[0005]
Step S51 is initialization, in which variables such as a pointer indicating the block to be rotated and a pointer indicating the rotated block are initialized.
[0006]
Step S52 is the main body of the rotation process. In order to generate one block (8 bytes) of the rotated process, the 8-byte data of the original block is accessed each time and transferred to the variable work pixel by pixel. Generate rotated data in variable work and write to pointer p_to's buffer.
[0007]
In step S52, each column of the pre-processing block (8 rows × 8 columns) is changed to each row of the post-processing block. In step S52-1, the pixel in the rightmost column of the pre-processing block is moved to the uppermost row of the post-processing block. Note that words such as left and right and up and down indicate corresponding positions when a block of 8 pixels × 8 pixels is visually considered. The movement at this time is performed by moving the uppermost pixel in the rightmost column of the pre-processing block to the left end of the uppermost row of the post-processing block, and sequentially processing the pixel below the pixel processed immediately before in the pre-processing block. This is performed so as to be arranged on the right side of the pixel processed immediately before in the subsequent block. Similarly, in step S52-2, the second column from the right side of the pre-processing block is moved to the second row of the post-processing block. In this way, 90 ° rotation is performed for one block.
[0008]
When step S52 ends, the process returns to step S51 to process the next block.
[0009]
FIG. 6 shows a conventional example of 180 degree rotation. FIG. 6A shows a case where a 256-byte lookup table (LUT) is used, and FIG. 6B shows a case where copy / paste is repeated in units of one pixel as in the conventional example rotated 90 degrees. . In the example using the LUT, the block before processing is converted by the LUT “table” in units of rows, that is, in units of 1 byte, and is used as the converted block. The LUT “table” has a value obtained by rotating the offset value in byte units from the head by 180 ° as a binary number. For example, the 0x05th byte of “table” is a value 0xA0 obtained by rotating it by 180 degrees. Therefore, in step S602, a value obtained by rotating the byte indicated by the pointer p_from by 180 degrees is given to the post-processing block indicated by the pointer p_to. If one line is processed, the pointer p_from is advanced by one line, the pointer p_to is moved back by one line, and processing is performed for eight lines, thereby completing one block rotation.
[0010]
In FIG. 6B, in step S612, one row (1 byte) of the pre-processing block is horizontally reversed, that is, rotated by 180 degrees. If this is sequentially performed from the upper stage for each row of the pre-rotation block, and it is incorporated from the lower stage of the post-rotation block, a block rotated 180 degrees is obtained.
[0011]
Incidentally, it is also conceivable to process using the LUT even in the case of 90-degree rotation.
[0012]
[Problems to be solved by the invention]
However, the conventional method is slow because processing is performed in units of one bit, and in order to perform processing in units of bits, it is necessary to access data in units of processing including the target bit, for example, in units of bytes. For this reason, since the rotated data is generated 1 byte, the data access of 8 bytes is performed every time, so that the speed is further reduced. This is even more noticeable in systems that do not have a data cache. Although the 16-bit processor can perform 16-bit computation and the 32-bit processor can perform 32-bit computation, the portion actually used for computation is only the 8-bit (1 BYTE) portion, which is wasteful.
[0013]
When the LUT is used, the number of data accesses increases, so that a data cache is desirable for high-speed processing. Also, if the table size is increased in order to further increase the speed by using the LUT and the number of LUT accesses is reduced so that conversion is performed in units of 2 bytes instead of conversion in units of 1 byte, for example, Compared to the increase in the table size that is 512 times, the number of LUT accesses is only ½, which is extremely inefficient. Conversely, in a system having a data cache, the cache hit rate may decrease and become slower.
[0014]
The present invention has been made in view of the above conventional example,
・ By storing and processing the data of the divided blocks spanning multiple bytes in a variable of multi-byte length, it is possible to process multiple pixels in one operation, reducing the total number of operations Image processing method and apparatus thereof, or
An image processing method and apparatus capable of reducing the number of operations by performing pixel recombination step by step from a small portion, or
An image processing method and apparatus capable of increasing the cache hit rate with respect to the capacity of the data cache and improving the speed by performing the processing order of the blocks in the order in which the addresses of the original images to be rotated are consecutive. The purpose is to provide.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the image processing method of the present invention has the following configuration. That is, 8 Bit x 8 An image processing device for rotating line image data by 90 degrees, 8 Store continuous image data of the upper half of the line in the first memory; 8 First processing means for storing continuous image data in the lower half of the line in a second memory; and image data stored in the first memory. N bits within 7 bits Shift, 1st 8 bit interval Image data masked except for the bit of interest and image data stored in the second memory N is 4 bits of difference M bits Shift, A second position shifted by MN bits with respect to the first bit of interest. Second processing means for storing, in a third memory, image data obtained by ORing image data other than the bit of interest masked; In order to process the image data not masked by the second processing means into 1 byte, A third processing means for obtaining a logical sum of the image data stored in the third memory and the image data obtained by shifting the image data stored in the third memory by a predetermined amount; and a shift by the second processing means. amount N and M one by one And the processing by the third processing means 8 And means for executing the number of times.
[0017]
[First embodiment]
FIG. 14 is a configuration diagram of a system for realizing image rotation processing according to the embodiment of the present invention. In FIG. 14, the CPU 1 executes a program stored in a memory to control the entire system and perform processing such as image rotation processing. The ROM 2 stores a control program (including a program related to a flowchart described later) and data of the CPU 1. The RAM 3 stores the work data of the CPU 1 and the rotated image and the rotated image. The scanner 4 inputs an image. The display 5 displays an image. The storage device 6 is composed of a magnetic disk device or the like, and stores images, programs, and other data. The printer 7 prints out images and the like. An input / output interface (I / F) 8 is connected to an external device for input / output. Among these blocks, there are the followings for performing image rotation described later.
[0018]
<Printer>
First, page description language data input from the input / output interface 8 or the like is stored in the RAM 3. The CPU 1 interprets it and draws it on the RAM 3, and sends the drawn bitmap data to the printer 7 for printing on the paper. In the printer 7, image rotation processing is performed when the bitmap data is rotated, the bitmap font is rotated, or when A4 is output by the A3 printer.
[0019]
<Filing device>
In FIG. 14, the storage device 6 corresponds to a filing device. In the case of an intelligent filing device that stores an original image read by the scanner 4 and performs character recognition, it is necessary to rotate the original image when the orientation of the original is not correct.
[0020]
<CPU>
The image read from the scanner 4 or the storage device 6 is stored in the RAM 3, rotated and displayed on the display 5.
[0021]
In this way, image rotation processing is performed as necessary. This rotation process is realized by the following procedure.
[0022]
<Rotation procedure>
FIG. 1 is a diagram that best represents image rotation processing according to the present invention.
[0023]
In the processing in this embodiment, a block of 1 byte × 8 lines (8 × 8 pixels) is used as a processing unit. Variables p_from / p_to are input / output pointers of blocks to be processed. The variables row_from / row_to are the number of bytes per line of the image before and after rotation, respectively. For example, if p_from points to the top row of a block, the next row of the block is an address obtained by adding the size row_from for one line of the image to the address of the row above the block. Variables work / tmp1 / tmp2 are work variables for rotation processing. Here, uint32 is a 4-byte long integer and is defined in advance.
[0024]
In the figure, step S11 is initialization, in which variables such as pointers to read and write blocks to be processed are initialized. That is, the address of the block before rotation is stored in the variable p_from, and the address of the block after rotation is stored in the variable p_to.
[0025]
Step S12 is a packing process in which all data of the block to be processed is read and stored in a variable larger than 1 byte length. As shown in FIG. 2 (a), the byte data of each line of 1 byte × 8 lines is divided into four lines, the upper four lines, and sequentially stored in variables of tmp1 and tmp2, respectively.
[0026]
Step S13 is a process of sequentially generating and writing the rotated data from the variables tmp1 and tmp2.
[0027]
FIG. 3 shows an outline of the processing of the bitcombine () macro, which is the main part of step S13.
[0028]
In step S12, pixel data of 1 byte × 8 lines (7th to 0th lines) is packed and stored in variables tmp1 and tmp2 by 4 bytes. In step S13, pixel data of each LSB (least significant digit) of the byte data on the seventh line is extracted from the seventh line, and 1-byte data that has been rotated is extracted. In the state rotated 90 degrees, the LSBs are arranged in order of numbers to form one row. For convenience of explanation, a value matching the line number is written in the LSB of each byte. A question mark indicates that the value does not matter.
[0029]
First, operation 1 is a logical operation in which each pixel data of LSB7 to LSB0 is extracted from variables tmp1 and tmp2 shown in state 1 and stored in variable work. In this operation, the contents of tmp1 are shifted left by 4 bits, and the logical product of the value and hexadecimal mask data mask2 = 0x10101010 is obtained. As a result, the value stored in the variable tmp1 is shifted left by 4 bits, and is 0 except for the original 4-bit LSBs 7, 6, 5, and 4. Further, the logical product of the contents of the variable tmep2 and the hexadecimal mask data mask1 = 0x01010101 is calculated. For this reason, the contents of tmp2 are all 0 except for the LSB. The value shown in the state 2 is obtained by calculating the logical sum of the tmp1 thus shifted and masked and the masked tmp2 to obtain the variable work. In this operation, the positional relationship between bit 7 and bit 3, the positional relationship between 6 and 2, the positional relationship between 5 and 1, and the positional relationship between 4 and 0 are arranged in the same manner as the positional relationship after rotation. .
[0030]
Next, by operation 2, the logical sum of the value of the variable work indicated as the state 2 and the value right-shifted by 7 bits is calculated. As a result, the variable work is rearranged as in state 3, and the positional relationship between LSB7, 6, 3 and 2 and the positional relationship between LSB5, 4 and 1 and 0 are arranged according to the positional relationship after rotation. Is done.
[0031]
Finally, the operation 3 calculates the logical sum of the value of the variable work indicated as the state 3 and the value obtained by shifting it to the right by 14 bits. As a result, the variable work is rearranged as in state 4, and the pixel data of the first row after rotation is obtained in the least significant 8 bits of the variable work.
[0032]
With the above operation, the rightmost column of the block before rotation can be replaced with the uppermost row of the block after rotation. To perform one block, the same operation is performed while shifting the LSB in the above description to the upper digit one pixel at a time. In order to move the pixel, the shift amount for the variables tmp1 and tmp2 in the operation 1 described above is decreased, and the shift operation is performed so that the target digit becomes the bits 0 to 7 in the state 2. The lower 1 byte of state 4 obtained in this way is a row rotated 90 degrees.
[0033]
FIGS. 15 and 16 show the flowchart of FIG. 1 in a more explanatory manner. In FIG. 15, step S151 corresponds to step S11, and the process of FIG. Steps S152 to S155 are processes corresponding to step S13. In step S13, it is described that a logical operation is performed on each column, but in FIG. 15, since the column number is generalized to n, a loop process is added. FIG. 16 explains step S153 in detail. The processing in the macro bitcombine () referred to in FIG. 1, that is, the procedure described in FIG. 3 is described with reference to FIG.
[0034]
In FIG. 16, the packed 32-bit tmp1 is first (4-n) Bits are shifted to the left, leaving all the 4th, 12th, 20th, and 28th bits set to 0. Here, n indicates a column (digit) to be rotated. When n-4 becomes negative, the shift direction is reversed. Next, in step S162, tmp2 is shifted n bits to the right, leaving 0th, 8, 16, and 24 bits as 0. In step S163, the logical sum of the results obtained in steps S161 and S162 is calculated. This is the operation 1 in FIG.
[0035]
Steps S164 to S166 are the contents as described in operations 2 and 3, respectively.
[0036]
In this way, each line of the block is not handled line by line, but is replaced with continuous data, and then the logical operation is performed, so that the pixel rearrangement is performed in parallel at a plurality of places instead of one place at a time. It is faster because it is processed.
[0037]
More specifically, for example, even if 4 bytes are packed and stored in variables tmp1 and tmp2, respectively, even if a necessary pixel is masked and extracted from data of 1 byte × 8 lines, one logical operation (AND operation) Can extract a plurality of pixels (4 pixels in the example). In addition, since the packing method of the data of the variables tmp1 and tmp2 is also aligned with the rotated bits, the pixel can be rearranged stepwise as shown in operations 2 and 3.
[0038]
The variables tmp1 and tmp2 can be reused not only when the bit is 0 as shown in FIG. 3 but also when extracting the rotation data of each digit. The remaining 7 bytes (line) of rotation data can be generated without access. For this reason, even if it is executed on a system without a data cache, if tmp1 and tmp2 are assigned to register variables, rotation data can be generated without memory access, which is very fast. In addition, packing a plurality of image data can reduce the number of variables, and also has an effect that assignment to register variables is easy. Even if allocation to register variables is not possible, the number of times of data access becomes 1/4 (8 times becomes 2 times because 1-byte access becomes 4-byte access), so it is still fast. is there.
[0039]
When calculated in detail, one block of 1 byte × 8 lines is rotated, so each byte data for packing is read once, an operation to generate 1 byte data after rotation from the packed data The number of times is 8 or 9 times, and the generated rotation data is written once. Incidentally, in the example of FIG. 3, operation 1 has 4 operations, and operations 2 and 3 each have 2 operations. That is, the number of access times of the image data is minimized, and the rotation process requires only one operation per pixel.
[0040]
When step S13 ends, the process returns to step S11 to process the next block, but the next block is considered to be the left or right block adjacent to the processed previous block or the upper and lower blocks. As shown in FIG. 4A, 25 blocks from 1 byte × 8 lines block a to y are processed in the order of 1 to 25, and blocks a to y are changed from 1 to 25 in the order as shown in FIG. Consider the case of processing in this order. When using a data cache, as a property of the data cache, if the data bus is a 32-bit processor even if it is a 1-byte read, at least 4 bytes on the 32-bit data bus including the 1 byte are stored in the cache memory. take in. Therefore, for example, when one byte in the block m is read, the data of the block l and the block n are taken into the cache memory. Since the data cache effect of block a appears when processing block b, when blocks are processed in the order of blocks a, f, k, p, u, b... As shown in FIG. The contents of the data cache are updated when the blocks f, k, p, and u are processed, and the probability of a miss hit is increased when the block b is processed. For this reason, the data cache hit rate is higher when processing is performed in the order as shown in FIG. In other words, it is effective even with a small-capacity data cache. Therefore, if the block configuration is the line configuration shown in the upper left block 41 as shown in FIG. 4C, after processing the shaded block, either the left or right block (the direction of the circle) is processed. It is desirable to do. The processing order of the blocks is performed in the order in which the addresses of the original images to be rotated are consecutive.
[0041]
FIG. 1 shows the case where all the data of one block of 1 byte × 8 lines is prepared. However, when the data is not prepared like the end of the image, the following may be performed.
[0042]
First, when the data of 8 lines are not prepared, the portion corresponding to the lack of the variables tmp1 and tmp2 is processed with a blank in step S12 (or step S151). If eight pixels in one byte are insufficient, control may be performed so that the bitcombine () macro corresponding to the missing portion is not executed in step S13, although there are eight bitcombine () macros. This corresponds to not executing the process for the missing n in step S153.
[Variation of the above embodiment]
Even if the macro bitcobine () of the above embodiment, that is, the processing procedure shown in FIG. 16 is changed as follows, the same result can be obtained.
[0043]
Bits other than the 4th, 12th, 20th, and 28th bits after shifting the 32-bit variable tmp1 in step S161 are set to 0, but are set to 1 instead of 0. Similarly, bits other than the 0th, 8th, 16th, and 24th bits are set to 0 in step S162, but this is also set to 1. Further, in step S163, a logical sum is calculated, but a logical product is calculated. As a result of this operation, the blank digit in state 2 of FIG. 3 is filled with 1 instead of 0. The subsequent steps are the same as in FIG.
[0044]
This can be expressed in the same way as bitcombine () in the upper part of FIG.
mask1 = 0xfefefefe;
mask2 = 0xefefefef;
#definebitcombine (pat1, pat2) \
work = ((pat1) | mask2) & ((pat2) | mask1); \
work & = work >>14; \
work & = work >>7;
In this example, when the number of lines in one block is not eight, the missing pixel is one. This means that the meaning of the black pixel may be 0 or 1. Therefore, when it is desired to make the margin portion white or black, it is preferable to use this example separately from the example of FIG.
[0045]
[Second embodiment]
[Rotate 180 degrees]
FIG. 7 shows an example in which the image processing apparatus according to the present invention is applied to 180 degree rotation of an image.
[0046]
The variable p_from / p_to is an input / output pointer of the block to be processed. The variable row_from / row_to is the number of horizontal bytes before and after rotation, and work is a work variable for rotation processing. The variable rem1 is a value for edge processing and stores the shift amount when the edge of the image does not fall on the 1-byte boundary. rem2 is a fixed value of (32−rem1).
[0047]
Step S71 is initialization, in which variables such as pointers for reading and writing of blocks to be processed are initialized. Processing is in units of 4 bytes × 1 line.
[0048]
Step S72 is a packing process in which all data of the block to be processed is read and stored in a variable larger than 1 byte length. The packed data is stored in the variable work. If the variable rem1 is not 0, the process of “work = (work >> rem1) | ((unit32) p_from [0] <<rem2);" in step S72 is performed to match the ends. The meaning of this expression is that the value of the variable work is shifted right by the number of digits rem1 to be aligned, and the value pointed to by the pointer p_from [0] is 32 bits and shifted left by rem2 digits. It is to calculate the logical sum. Incidentally, the same processing is necessary for the processing of the conventional example, but is omitted for the sake of simplicity. Note that the right shift operation to be performed here is a logical shift operation, and is a shift operation in which 0 is filled in the vacant digits after the shift.
[0049]
Step S73 is a process of sequentially generating and writing the rotated data from the variables. When step S73 ends, the process returns to step S71 to process the next block.
[0050]
FIG. 8 is a diagram for explaining the bitcombine () macro in step S73 of FIG. In order to simplify the explanation, explanation will be made with bit rotation of 1-byte data. First, bit data from 7 to 0 is arranged in the variable work as in state 1. By the operation 1, the pixel data of the variables work 7 and 6, 5 and 4, 3 and 2, 1 and 0 are exchanged, and the variable work becomes the state 2. Next, the contents of the variable work are rearranged by the operation 2, among which the pixel data 6-7, 4-5, 2-3, and 0-1 are exchanged, and the variable work becomes the state 3. Finally, the contents of the variable work are rearranged by the operation 3, among which the pixel data 4-7 and 0-3 are exchanged, the variable work becomes the state 4 and the rotation process ends. In other words, pixel recombination is processed in a stepwise manner because a plurality of locations are processed by a single operation. Incidentally, the result is the same regardless of the order of operations 1 to 3. The variable work to be rotated is a 4-byte variable, and the upper half or the lower half of the block is packed into the variable work in step S72. Therefore, in the process of step S73, the operation shown in FIG. Is applied simultaneously to the 4 bytes in the variable work.
[0051]
If this processing time is calculated in detail, operations 1 to 3 each have 5 operations and 15 operations. In FIG. 6B of the conventional example, since there are 21 operations, this alone is high speed. However, since the variable work is stored for 4 bytes and can be processed at the same time, the speed is further increased. The number of operations per bit is 15/32, which is about 0.5 operations. In addition, since this algorithm does not access extra data like the LUT, even if it is executed in a system without a data cache, the speed reduction is small. As can be seen from FIG. 8, the 180 ° rotation does not necessarily require packing because pixel rearrangement can be performed step by step without packing a plurality of bytes of data.
[0052]
FIG. 7 shows the case where all the data of one block of 4 bytes × 1 line is prepared. However, when the data is not prepared like the end of the image, the following may be performed. First, when the 4-byte data is not complete, the portion corresponding to the lack of the variable work is processed with a blank in step S72. In step S73, the same processing is performed in the bitcombine () macro, and control is performed so that only the valid portion of the data is written.
[0053]
FIG. 17 illustrates the processing of FIG. 7 in a more explanatory manner, and FIG. 18 illustrates the macro bitcombine in FIG.
[0054]
In FIG. 17, first, the upper half 4 bytes of the block to be rotated are packed into the variable work (S171). If this is an odd block, the odd portion is filled with blanks (S173). Next, the upper digit and the lower digit are reversed in the n-th line in the block (S175). This is what is shown in FIG. 18 and is the process itself of FIG. The process of step S175 is performed for the four lines packed in the variable work, and the process is repeated from step S171 in the same manner for the four lines that have finished the upper four lines (S179). finish.
[0055]
In FIG. 18, first, the odd and even digits adjacent to each other among the 4 bytes packed in step S181 are exchanged (operation 1), and then the two bits exchanged in step S182 are paired and further adjacent. The odd-numbered group and the even-numbered group are switched (operation 2). Similarly, in step S183, 4 bits each having 2 bits replaced in step S182 are set as a set, and the odd-numbered set and the even-numbered set adjacent to each other are switched (operation 3). This completes the exchange of the upper and lower digits for the packed 4 bytes. If the nth line in the pre-rotation block is stored as the (7-n) line in the post-rotation block, the rotation of one line is completed.
[0056]
[Third embodiment]
[90 degree rotation when bit 0 is left]
In the first embodiment, the 90 ° rotation is shown when bit 7 is the left pixel, but FIG. 9 shows an example where bit 0 is the left. The operation is almost the same as that in the first embodiment. However, in the processing in step S92, the data packing method is reversed as shown in FIG. 2B, and in step S13 in FIG. 1, the bitcombine () macro is used. Only the order of the lines converted from column to row is reversed. That is, in the process of FIG. 1, since the LSB is the rightmost digit, it is rotated so that it is the first line. However, in FIG. 9, the leftmost digit is the LSB, so that it is the first line. Contrary to FIG. 3, a line is first formed from the leftmost digit to form a first line.
[0057]
By doing in this way, even if bit 0 is the left end, 90 degree rotation processing can be performed similarly.
[0058]
[Fourth embodiment]
[270 degree rotation]
The case where bit 7 is the left pixel is the same as in FIG. 9, and the case where bit 0 is the left pixel is the same as in FIG. The only difference from the 90-degree rotation is the order of blocks to be processed by the pointer initialization in step S11 or step S91. This is clear from the fact that the processing in FIG. 1 and the processing in FIG. 9 are rotating in opposite directions when only the bit arrangement is considered.
[0059]
[Example of speeding up with 64-bit calculation]
FIG. 10 shows an example in which a 32-bit operation is used in the first embodiment, but a processor capable of 64-bit operation is used. Here, uint64 is an 8-byte long integer and is defined in advance.
[0060]
This process is essentially the same as the process described with reference to FIG. 3, FIG. 15, or FIG. 16. However, since 64 digits can be processed in parallel, tmp1 and tmp2 in FIG. 3 are combined into one variable work. It is a point that can be used. That is, in the state 1 of FIG. 3, the upper 4 bytes of the block are divided into two 4-byte variables and packed. In step S102 of FIG. 10, 8 bytes for one block are packed together. That is, in FIG. 10, tmp1 and tmp2 correspond to the continuous variable work, and therefore, a value obtained by shifting the variable work to the right by 32 digits (4 bytes) corresponds to the variable tmp1. Therefore, the operation 1 in FIG. 3 corresponds to shifting the upper 32 bits of the variable work by 4 digits and taking the logical sum with the lower 32 bits (including a masking process for non-target digits).
[0061]
As described above, in the first embodiment, the number of operations in the bitcombine () macro is 8 or 9, but in FIG. 10 of this embodiment, the processing of the operation 1 in FIG. 3 can calculate the shift and the logical sum. Therefore, the number of operations is further reduced to 7 or 8.
[0062]
In this way, the conventional algorithm performs processing in units of 8 bits regardless of the number of digits processed in parallel by the processor, so there is no room for speeding up even if the processor evolves. If so, the speed can be further increased.
[0063]
In this embodiment, there is an advantage that the variables tmp1, tmp2, mask1, and mask2 of the first embodiment are reduced to the variables tmp and mask. By the way, in the bitcombine () macro of FIG. 10, the part of ““ work | = work >>28; work | = 14; work | = work >>7; ”is in reverse order to FIG. Be the same. That is, the processing in “” corresponds to the operations 1 to 3 in which the digits described with reference to FIG. 3 are shifted and overlapped, but these operations can be obtained in the reverse order, and the same result can be obtained. That's what it means.
[0064]
[Fifth embodiment]
[Multi-valued image rotation]
FIG. 11 shows a 90-degree rotation processing method in the case of 2 bits per pixel. One byte × 4 lines are processed as one block, and this is a process in which the rotation processing shown as the first embodiment is performed with 2 bits as one unit. That is, in step 112, 4 lines and 32 bytes are packed into one variable tmp. FIG. 19 is a schematic diagram of the rotation process of one line forming the first line after rotation in step S113 of FIG. In step S112, the variable tmp is packed as in state 1 in FIG. Thereafter, the data is shifted to the right by 6 digits, and the other than the 2 rightmost digits of each byte are masked with 0 (operation 1). Here, the 6-digit shift is performed because the upper 2 bits are the object of processing. If the lowest 2 bits, it is not necessary to shift. If it is a bit, it is sufficient to shift four digits to the right. In this way, data in state 2 is obtained. This state is the same regardless of the number of lines.
[0065]
Next, the state 2 data is shifted to the right by 6 digits, and the logical sum with the state 2 data is calculated (operation 2) to obtain the state 3 data. . Further, the state 3 data is shifted to the right by 12 digits, and the logical sum with the state 3 data is calculated (operation 3) to obtain the state 4 data. This least significant byte is one line after rotation.
[0066]
If the above operation is performed for all four lines and the obtained lines are stored as lines corresponding to the digits before processing, image data rotated by 90 degrees can be obtained. In FIG. 19, the rotation is performed so that the upper digit is the upper line and the lower digit is the lower line. As described above, the procedure is basically the same as that of the first embodiment, except that the number of digits to be searched is 2 bits instead of 1 bit.
[0067]
As described above, the present invention can also be applied to multi-value images.
[0068]
[Sixth embodiment]
[Multi-line processing]
FIG. 12 shows a 90 ° rotation processing method in the case of 2 bits per pixel. Using the same variables tmp1 and tmp2 as in FIG. 1, in step S122, the same operation is prevented from being repeated in step S123 by the process of “tmp1 | = tmp1 <<14; tmp2 | = tmp2 <<14;”. As a result, in the bitcombine () macro, two lines of rotated data are generated for the variable work.
[0069]
FIG. 20 is a diagram showing this state. First, in step SS122, as in state 1, the first line (indicated by symbol a) and the second line (symbol b) of the pre-rotation block are set in the variable tmp2. That is, the second line and the first line are sequentially stored in the lower 16 bytes of tmp1 (the other digits are set to 0), and the logical sum of the value and the value obtained by shifting it to the left by 14 bits is stored in the variable tmp2. Store. Similarly, the variable tmp1 stores the third line and the fourth line.
[0070]
For these state 1 variables, first, the value of tmp2 is shifted 4 digits to the right to set the values other than the lower 2 bits of each byte to 0, and the values of tmp1 are set to 0 for the 3rd and 4th bits from the top of each byte. (Operation 1). It is desirable to keep the values of variables tmp1 and tmp2 unchanged for subsequent processing.
[0071]
For the value of state 2 obtained in this way, the logical OR of both is calculated (operation 2) to obtain the value of state 4, and the logical sum of the value of state 3 and the value obtained by shifting the value to the right by 6 digits (Operation 3), the value of state 4 is obtained.
[0072]
In state 4, two lines are obtained after the pre-rotation block is rotated 90 degrees by 2 bits. That is, the first line is obtained as the second byte, and the second line is obtained as the fourth byte.
[0073]
The above operation is also performed on the third and fourth lines after rotation. For that purpose, the two values given as state 2 are shifted to the left by 4 digits from FIG. 20, respectively, and instead of bits 7 and 6 or bits 5 and 4, as shown in FIG. Bits 1 and 0 may be replaced respectively. As a result, the third and fourth lines after rotation are obtained in operations 2 and 3.
[0074]
[Seventh embodiment]
[Multiple block processing]
FIG. 13 shows a 90-degree rotation processing method in the case of 4 bits per pixel. According to the first embodiment, when 1 pixel is 4 bits, 1 byte × 2 lines become a block, but if this is left as it is, when packing into a 32-bit variable, 2 bytes are blank and 1/2 of the operation is wasted. . Therefore, processing is performed by packing 2 bytes × 2 lines for 2 blocks into a variable tmp. This packing is performed in step S132. Here, packing is performed in a 4-byte variable tmp in the order of the first line of the second block, the second line of the second block, the first line of the first block, and the second line of the first block.
[0075]
FIG. 21 shows this state. First, for the two blocks A and B each having 4 bits and 1 pixel, the pixels a1 to a4 and b1 to b4 are considered as shown in FIG. This is packed as in state 1 in step S132. This is stored in the 32-bit variable tmp by operation 1 pixel by pixel (4 bits) from the lower order. Similarly, the pixels that are not stored in tmp are stored in work by shifting them four places to the right. This results in state 2. The logical sum of the value of tmp thus obtained and the value obtained by shifting the value to the right by 4 digits is calculated and stored in the variable tmp (operation 3). Do the same for the variable work. If both variables of state 3 obtained in this way are stored as the two blocks after rotation, the second byte of work, the second byte of temp, the fourth byte of work, and the fourth byte of tmp, Images obtained by rotating 90 ° together with B can be obtained.
[0076]
As a result, the total number of calculations and the number of loops are reduced, so that processing can be performed at high speed. If a plurality of variables for packing are prepared, the number of loops can be further reduced.
[0077]
Furthermore, if a processor capable of 64-bit operation is used, the number of blocks that can be processed by itself is doubled. For example, not only in the case of 4 bits per pixel but also in the case of 2 bits per pixel as shown in FIG. 11, it is easy to change to process two blocks simultaneously.
[0078]
The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Needless to say, the present invention can also be applied to a case where the present invention is achieved by supplying a program to a system or apparatus.
[0079]
【The invention's effect】
As described above, according to the image processing method and apparatus according to the present invention,
-By storing the data on a bitmap that spans multiple bytes in a variable of multiple bytes, multiple bytes can be processed simultaneously, and the number of operations can be reduced. Therefore, since a plurality of pixels can be processed at the same time, the number of operations per pixel is reduced, and the processing time can be shortened.
[0080]
In the conventional example, even if the processor to be executed is changed from 32 bits to 64 bits, the speed does not increase unless there is a change in operating frequency, cache contents, internal architecture, or the like. However, in the present invention, only the bit width of the operation is increased, and the speed is increased by actively using it. Therefore, the difference from the conventional example can be further increased.
[0081]
-Since the number of data accesses is small, the decrease in speed is small in a system with few data caches. For the same reason, the speed reduction is small even in a system without a data cache.
[0082]
By performing the processing order of blocks in the order in which the addresses of the original images to be rotated are consecutive, the cache hit rate is increased with respect to the capacity of the data cache, and the speed is improved.
[0083]
・ By storing image data that spans multiple bytes together in a variable of multi-byte length, it is possible to reduce the amount of variable rather than storing separately, which makes it easier for the compiler to assign the variable to a register variable. There is an effect.
[0084]
[Brief description of the drawings]
FIG. 1 is a diagram showing a procedure of 90-degree rotation processing according to a first embodiment of the present invention.
FIG. 2 is a diagram of data packing according to the first embodiment.
FIG. 3 is a diagram illustrating a procedure of a 90-degree rotation process according to the first embodiment.
FIG. 4 is a diagram illustrating an order of block processing according to the first embodiment.
FIG. 5 is a diagram showing a procedure of a conventional example of 90-degree rotation of a block.
FIG. 6 is a diagram showing a procedure of a conventional example of 180 degree rotation of a block.
FIG. 7 is a diagram illustrating a procedure of 180 degree rotation of a block according to a second embodiment.
FIG. 8 is a diagram for explaining 180-degree rotation in the second embodiment.
FIG. 9 is a diagram showing a procedure of 270 degree rotation in the fourth embodiment.
FIG. 10 is a diagram showing a processing procedure when the processing of the first embodiment is performed by a 64-bit processor.
FIG. 11 is a diagram showing a processing procedure for rotating a block by 90 degrees when one pixel is 2 bits according to the fifth embodiment;
FIG. 12 is a diagram showing a processing procedure for simultaneously processing a plurality of lines according to the sixth embodiment.
FIG. 13 is a diagram showing a processing procedure when processing a plurality of blocks simultaneously according to the seventh embodiment;
FIG. 14 is a configuration diagram of a system that performs image processing according to an embodiment.
FIG. 15 is a diagram showing a procedure of 90-degree rotation processing according to the first embodiment of the present invention.
FIG. 16 is a diagram showing a procedure of 90-degree rotation processing according to the first embodiment of the present invention.
FIG. 17 is a diagram showing a procedure of 180 degree rotation processing according to the second embodiment of the present invention.
FIG. 18 is a diagram showing a procedure of 180 degree rotation processing according to the second embodiment of the present invention.
FIG. 19 is a diagram illustrating a state in which a block is rotated 90 degrees when one pixel is 2 bits according to the fifth embodiment.
FIG. 20 is a diagram illustrating another state in which a block is rotated 90 degrees when one pixel is 2 bits according to the fifth embodiment.
FIG. 21 is a diagram showing a block state when a plurality of blocks are processed simultaneously according to the seventh embodiment;

Claims (10)

An image processing apparatus that rotates image data of 8 bits × 8 lines by 90 degrees,
First processing means for storing continuous image data of the upper half of the eight lines in the first memory, and storing continuous image data of the lower half of the eight lines in the second memory;
The image data stored in the first memory is shifted by N bits within 7 bits, and the image data masked except for the first bit of interest at intervals of 8 bits and the image data stored in the second memory are N Is a M-bit shift of a difference of 4 bits, and image data obtained by ORing image data other than the second noticed bit at a position shifted by MN bits with respect to the first noticed bit is the third Second processing means for storing in a memory;
An image obtained by shifting the image data stored in the third memory and the image data stored in the third memory by a predetermined amount in order to process the image data not masked by the second processing means into 1 byte. Third processing means for performing a logical OR with data;
An image processing apparatus comprising: processing for sequentially changing the shift amounts N and M by one by the second processing means, and means for executing the processing by the third processing means eight times. The second processing means shifts the image data stored in the first memory to the left by N bits and masks the image data other than the target bit and the image data stored in the second memory to the right by M bits. The image data obtained by performing a logical sum with the image data that has been shifted and masked other than the bit of interest is stored in the third memory,
The third processing means calculates the logical sum of the image data stored in the third memory and the image data obtained by shifting the image data stored in the third memory to the right by 7 bits and stores the logical sum in the third memory. The logical sum of the image data stored in the third memory and the image data obtained by shifting the image data stored in the third memory to the right by 14 bits is stored in the third memory. The image processing apparatus according to claim 1. The processing by the third processing means takes a logical sum of the image data stored in the third memory and the image data obtained by shifting the image data stored in the third memory to the right by 7 bits, The image processing apparatus according to claim 1, further comprising a process of calculating a logical sum of the logical sum result and image data obtained by shifting the logical sum result to the right by 14 bits .   4. The image processing apparatus according to claim 1, further comprising output means for outputting an image based on the image data.   The image processing apparatus according to claim 4, wherein the output unit is a printing unit. An image processing method of rotating image data of 8 bits × 8 lines by 90 degrees,
A first processing step of storing continuous image data of the upper half of the eight lines in the first memory, and storing continuous image data of the lower half of the eight lines in the second memory;
The image data stored in the first memory is shifted by N bits within 7 bits, and the image data masked except for the first bit of interest at intervals of 8 bits and the image data stored in the second memory are N Is a M-bit shift of a difference of 4 bits, and image data obtained by ORing image data other than the second noticed bit at a position shifted by MN bits with respect to the first noticed bit is the third A second processing step stored in a memory;
An image obtained by shifting the image data stored in the third memory and the image data stored in the third memory by a predetermined amount in order to process the image data not masked in the second processing step into 1 byte. A third processing step for performing a logical OR with data;
An image processing method comprising: a process in which the shift amounts N and M in the second processing step are sequentially changed by 1; and a step in which the processing in the third processing step is executed eight times. In the second processing step, the image data stored in the first memory is shifted N bits to the left, and the image data masked except for the bit of interest and the image data stored in the second memory are shifted to the right by M bits. The image data obtained by performing a logical sum with the image data that has been shifted and masked other than the bit of interest is stored in the third memory,
In the third processing step, the logical sum of the image data stored in the third memory and the image data obtained by right shifting the image data stored in the third memory by 7 bits is stored in the third memory. The logical sum of the image data stored in the third memory and the image data obtained by shifting the image data stored in the third memory to the right by 14 bits is stored in the third memory. The image processing method according to claim 6 . In the processing by the third processing step, the logical sum of the image data stored in the third memory and the image data obtained by shifting the image data stored in the third memory to the right by 7 bits is taken. The image processing method according to claim 6 , further comprising: a logical sum of the logical sum result and image data obtained by shifting the logical sum result to the right by 14 bits . The image processing method according to claim 6, further comprising an output step of outputting an image based on the image data. The image processing method according to claim 9 , wherein the output step is a printing step.

Images