JP3704046B2 - データハザードを検出するために用いられるデータを融合するためのシステム及び方法 - Google Patents

データハザードを検出するために用いられるデータを融合するためのシステム及び方法 Download PDF

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JP3704046B2
JP3704046B2 JP2001019488A JP2001019488A JP3704046B2 JP 3704046 B2 JP3704046 B2 JP 3704046B2 JP 2001019488 A JP2001019488 A JP 2001019488A JP 2001019488 A JP2001019488 A JP 2001019488A JP 3704046 B2 JP3704046 B2 JP 3704046B2
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register
instruction
identifier
data
stage
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JP2001216159A5 (enExample
JP2001216159A (ja
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ロニー・リー・アーノルド
ドナルド・チャールズ・ソルティス・ジュニア
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP2001019488A 2000-01-28 2001-01-29 データハザードを検出するために用いられるデータを融合するためのシステム及び方法 Expired - Fee Related JP3704046B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/493504 2000-01-28
US09/493,504 US6490674B1 (en) 2000-01-28 2000-01-28 System and method for coalescing data utilized to detect data hazards

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JP2001216159A JP2001216159A (ja) 2001-08-10
JP2001216159A5 JP2001216159A5 (enExample) 2005-03-17
JP3704046B2 true JP3704046B2 (ja) 2005-10-05

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JP2001019488A Expired - Fee Related JP3704046B2 (ja) 2000-01-28 2001-01-29 データハザードを検出するために用いられるデータを融合するためのシステム及び方法

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US (2) US6490674B1 (enExample)
JP (1) JP3704046B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7730282B2 (en) * 2004-08-11 2010-06-01 International Business Machines Corporation Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector
US20060200654A1 (en) * 2005-03-04 2006-09-07 Dieffenderfer James N Stop waiting for source operand when conditional instruction will not execute
JP4368320B2 (ja) * 2005-03-16 2009-11-18 富士通株式会社 情報処理システム，パイプライン処理装置，ビジー判定プログラム及び同プログラムを記録したコンピュータ読取可能な記録媒体
WO2007069000A1 (en) * 2005-12-16 2007-06-21 Freescale Semiconductor, Inc. Device and method for processing instructions
GB2447907B (en) * 2007-03-26 2009-02-18 Imagination Tech Ltd Processing long-latency instructions in a pipelined processor
US20090055636A1 (en) * 2007-08-22 2009-02-26 Heisig Stephen J Method for generating and applying a model to predict hardware performance hazards in a machine instruction sequence
US8117578B2 (en) * 2007-12-28 2012-02-14 Nec Corporation Static hazard detection device, static hazard detection method, and recording medium
US9195466B2 (en) * 2012-05-16 2015-11-24 Qualcomm Incorporated Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media
US9697580B2 (en) * 2014-11-10 2017-07-04 Qualcomm Incorporated Dynamic pipeline for graphics processing
US10810064B2 (en) * 2018-04-27 2020-10-20 Nasdaq Technology Ab Publish-subscribe framework for application execution
EP3812892B1 (en) 2019-10-21 2022-12-07 ARM Limited Apparatus and method for handling memory load requests
GB2594732B (en) * 2020-05-06 2022-06-01 Advanced Risc Mach Ltd Adaptive load coalescing

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US860017A (en) 1907-02-08 1907-07-16 John Antonio Cuneo Check-valve.
US5155817A (en) * 1988-04-01 1992-10-13 Kabushiki Kaisha Toshiba Microprocessor
US5006980A (en) * 1988-07-20 1991-04-09 Digital Equipment Corporation Pipelined digital CPU with deadlock resolution
JP2695956B2 (ja) * 1990-02-28 1998-01-14 株式会社東芝 多重通信システム
US5933651A (en) * 1995-09-29 1999-08-03 Matsushita Electric Works, Ltd. Programmable controller
US5778248A (en) * 1996-06-17 1998-07-07 Sun Microsystems, Inc. Fast microprocessor stage bypass logic enable
US5860017A (en) 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5859999A (en) 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
US6195724B1 (en) * 1998-11-16 2001-02-27 Infineon Technologies Ag Methods and apparatus for prioritization of access to external devices
US6374323B1 (en) * 1998-11-16 2002-04-16 Infineon Technologies Ag Computer memory conflict avoidance using page registers
US6401195B1 (en) * 1998-12-30 2002-06-04 Intel Corporation Method and apparatus for replacing data in an operand latch of a pipeline stage in a processor during a stall
US6219781B1 (en) * 1998-12-30 2001-04-17 Intel Corporation Method and apparatus for performing register hazard detection
US6304955B1 (en) * 1998-12-30 2001-10-16 Intel Corporation Method and apparatus for performing latency based hazard detection
US6438681B1 (en) * 2000-01-24 2002-08-20 Hewlett-Packard Company Detection of data hazards between instructions by decoding register indentifiers in each stage of processing system pipeline and comparing asserted bits in the decoded register indentifiers

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Publication number Publication date
US20030051121A1 (en) 2003-03-13
US6728868B2 (en) 2004-04-27
JP2001216159A (ja) 2001-08-10
US6490674B1 (en) 2002-12-03

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