JP3698959B2 - Information processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus that connects one or more PCI buses directly under a host bus using one or more host-PCI bus bridges.
[0002]
[Prior art]
Conventionally, in an information processing apparatus that connects one or more PCI buses directly under the host bus using one or more host-PCI (peripheral component interconnect) bus bridges, an initialization program is used to set the bus device configuration. For the on-board PCI device connected to the PCI bus directly under the host-PCI bus bridge and the optional PCI device mounted in the PCI slot, the device number of the on-board PCI device of the PCI bus and all PCI slots After reading the Vender ID of function 0 and confirming the presence or absence of the PCI device, the header type is confirmed if it exists. If the header type is type 00h, the base address register and the expansion ROM base address To check the size After their register written ol F, it reads the configuration header (offset 00h-3Fh).
[0003]
When the header type is confirmed, if the PCI device is a multi-function device, the vendor ID is also read for all the function numbers (1-7) other than the function 0 to check the presence or absence of the existing function. In this case, the same processing as when the previous function 0 exists is performed. Further, the initialization program is executed sequentially with respect to the host-PCI bus bridge.
[0004]
[Problems to be solved by the invention]
However, the first problem of the conventional information processing apparatus that connects one or more PCI buses directly under the host bus using the one or more host-PCI bus bridges is an optional PCI device mounted in the PCI slot. With respect to the above, when the device is a multi-function device and the number of functions is small, the initialization program spends wasted time.
[0005]
The reason for this is that in the case of a multi-function device, even if the device has two functions, the initialization program is a vendor to check whether all functions (0-7) exist. This is because the ID must be read.
[0006]
The second problem with conventional information processing devices is that as the number of host-PCI bus bridges increases, the initialization program confirms the presence of devices and functions, and the amount of memory and I / O (input / output) resources. This means that the processing time spent for reading the type 00h configuration header including confirmation becomes enormous.
[0007]
The reason for this is that in a system with multiple host-PCI bus bridges, the initialization program checks the existence of devices and functions for the PCI buses directly under each host-PCI bus bridge, and the memory and I / O resources To confirm the amount, all F is written to all base address registers and expansion ROM base address, and the operation of reading the configuration header of type 00h to the PCI bus directly under each host-PCI bus bridge is only sequential. This is because it cannot be executed.
[0008]
The present invention has been made in view of the above points, and an object of the present invention is to provide an information processing apparatus that can prevent deterioration in initialization processing time even when a multifunction PCI device is used.
[0009]
Another object of the present invention is to provide an information processing apparatus capable of preventing deterioration in initialization processing time even in a system having many host-PCI bus bridges.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has one or more host-PCI bus bridges and a processor connected to each other via a host bus, one or more PCI slots, an on-board PCI device, and a PCI- Each ROM bus bridge is connected to the host-PCI bus bridge via one or more PCI buses, and an optional PCI device can be connected to the PCI slot, and an on-board PCI device, an optional PCI device, and a host-PCI bus. An information processing apparatus in which a first memory storing an initialization program for setting a configuration state for a bridge is connected to a PCI bus via a PCI-ROM bus bridge ,
The host-PCI bus bridge has a second memory storing valid device numbers corresponding to all on-board PCI devices and PCI slots connected to the PCI device, and a third memory storing configuration header information. The configuration header of function number 0 in the on-board PCI device and optional PCI device corresponding to all device numbers stored in the second memory in response to the start instruction for collecting the configuration header information of the initialization program and the initialization program Collect the information and store it in the third memory. If the configuration header information is multi-function, check the existence of all functions and check the configuration for the existing functions. Configuration data collection processing means for collecting configuration header information and storing it in a third memory ,
The initialization program stored in the first memory executes a different process once after the configuration header information collection operation start instruction by the configuration data collection processing means, and then executes the process of the configuration header information by the configuration data collection processing means. A busy check request for confirming completion of collection is issued to the host-PCI bus bridge, and a free response indicating that collection of configuration header information is completed in response to the busy check request is a configuration data collection processing means. If there is, the initialization program manages the resources of the on-board PCI device and the optional PCI device based on the configuration header information obtained by reading the configuration header information stored in the third memory. And performing fine setting.
[0011]
In the present invention, when the PCI device connected to the PCI bus directly underneath the host-PCI bus bridge is a multi-function device, the presence / absence of all functions is independently confirmed, and the configuration related to the existing function is confirmed. Since the configuration header information is stored in the third memory in the host-PCI bus bridge, the initialization program can obtain information for the existing functions from the third memory. Further, while the initialization program is performing other processing such as memory configuration setting, configuration header information relating to existing functions can be stored in the third memory in the host-PCI bus bridge. .
[0012]
Here, the above initialization program is read and executed by the processor via the host bus, host-PCI bus bridge, PCI bus, and PCI-ROM bus bridge at power-on or hardware reset. It is characterized by that.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a configuration diagram of an embodiment of an information processing apparatus according to the present invention. As shown in the figure, in this information processing apparatus, a host-PCI bus bridge 1 and a processor 2 are connected to each other via a host bus 3, and PCI slots 5a, 5b, 5c and on-board PCI are connected. The device 7 and the PCI-ROM bus bridge 8 are connected to the host-PCI bus bridge 1 via the PCI bus 4.
[0021]
Furthermore, optional PCI devices 6a and 6b are connected to the PCI slots 5a and 5b, and a read-only memory (ROM) 9 is connected to the PCI-ROM bus bridge 8. The ROM 9 stores an initialization program 10.
[0022]
The host-PCI bus bridge 1 includes a host bus controller 11, a PCI bus controller 12, a valid device number nonvolatile memory 13, a configuration header information storage memory 14, a configuration data collection controller 15, and a configuration data collection processing host communication controller 16. It is made up of.
[0023]
FIG. 2 shows an exemplary format of a configuration header of a configuration register for each function of each PCI device. In the figure, a configuration header 20 includes a vendor ID (offset 00h-01h) 21, a header type (offset 0Eh) 22, a base address register (offset 10h-24h) 23, and an expansion ROM base address (offset 30h-33h) 24. Is included.
[0024]
However, the base address register (offset 10h-24h) 23 and the expansion ROM base address (offset 30h-33h) 24 are functions and names when the header type indicated by bits 0-6 of the header type (offset 0Eh) 22 is 00h. As for the operations of the base address register (offset 10h-24h) 23 and the expansion ROM base address (offset 30h-33h) 24 for devices other than the header type 00h, operations other than reading data are It is outside the scope of the present invention.
[0025]
Next, the operation of the present embodiment will be described. In FIG. 1, at power-on or hardware reset, the host-PCI bus bridge 1 and the PCI-ROM bus bridge 8 transfer the initialization program 10 stored in the ROM 9 from the host bus 3 to the host bus. Assume that the controller 11, the PCI bus controller 12, the PCI bus 4, and the PCI-ROM bus bridge 8 are reset to a readable state.
[0026]
The effective device number nonvolatile memory 13 has valid device numbers corresponding to all PCI slots 5a to 5c and on-board PCI devices 7 connected to the PCI bus 4 under the host-PCI bus bridge 1. It is assumed that it is registered in advance by a serial bus (not shown) at the time of factory shipment. The specific registering means in the effective device number nonvolatile memory 13 is not related to the gist of the present invention, and the description thereof will be omitted.
[0027]
When the power is turned on or the hardware is reset, the processor 2 loads the initialization program 10 stored in the ROM 9 from the host bus 3 to the host bus controller 11, the PCI bus controller 12, the PCI bus 4, and the PCI-ROM bus bridge 8. Read via.
[0028]
Subsequently, the initialization program 10 sends an option PCI device 6a, 6b to the host-PCI bus bridge 1 in which the host-PCI bus bridge 1 is connected to the PCI bus 4 via PCI slots 5a, 5b. Then, a configuration data collection start instruction indicating that collection of configuration header information of the on-board PCI device 7 is started is issued. This configuration data collection start instruction is passed to the configuration data collection processing host communication controller 16 via the host bus controller 11.
[0029]
Upon receiving the configuration data collection start instruction, the configuration data collection processing host communication controller 16 sends the above-mentioned start instruction to the configuration data collection controller 15 and also notifies the initialization program 10 that the collection process is busy. A busy response is made to the check request.
[0030]
Upon receiving the start instruction, the configuration data collection controller 15 reads the stored contents of the valid device number nonvolatile memory 13 and sets the function number 0 of the device number to be processed for all the registered device numbers. The vendor ID (offset 00h-01h) 21 located in the configuration header 20 shown in FIG. 2 is read, and when the vendor ID 21 is valid (other than FFFFh), the PCI bus controller 12 is controlled, and the configuration data shown below Have a collection process.
[0031]
The above “configuration data collection process” is to read the header type (offset 0Eh) 22 located in the configuration header 20 of the PCI device, and when bits 0-6 of the header type 22 are other than type 00h, the configuration is performed as it is. Configuration header (offset 00h-3Fh), and in the case of type 00h, in order to simultaneously obtain the size of the I / O space and memory space of the PCI device, After all Fh data is written to all base address registers (offset 10h-27h) 23 and expansion ROM base address (offset 30h-33h) 24, the configuration header (offset 00h-3Fh) 20 is read. This information (the size of the base address register 23 and the expansion ROM base address 24 can be determined by how many 0 are returned to the lower bits) is stored in the configuration header information storage memory 14 together with the corresponding device number and function number. This means a series of processing. When the vendor ID 21 is invalid, no further reading of the configuration header 20 and storage in the configuration header information storage memory 14 are performed.
[0032]
Further, when the header type 22 of the function number 0 is multi-function (when the bit 7 of the header type 22 is 1), all the function numbers (1-7) other than 0 of the device number are all The above configuration data collection process is performed.
[0033]
Through these processes, when all device numbers registered in the non-volatile memory for valid device number 13 and the corresponding devices are multi-function devices, information on the configuration header 20 of the devices valid for all function numbers (header type) When the bits 0-6 of 00h are 00h, the sizes of the I / O space and memory space are also stored in the configuration header information storage memory 14 together with the device number and function number.
[0034]
When the configuration data collection controller 15 completes the collection processing for all devices registered in the valid device number nonvolatile memory 13, the configuration data collection controller 15 notifies the configuration data collection processing host communication controller 16 to that effect. When the configuration data collection processing host communication controller 16 receives the above completion notification from the configuration data collection controller 15, the configuration data collection processing host communication controller 16 itself sets the internal state in which the collection processing of the configuration data collection processing host communication controller 16 is busy to a free state. Thereafter, a free response is made to the busy check request from the initialization program 10.
[0035]
After there are a plurality of other bridges (not shown) having the same function as the host-PCI bus bridge 1 after the initialization program 10 instructs the host-PCI bus bridge 1 to start configuration data collection, The configuration data collection start command is sent to the bridge.
[0036]
It should be noted that a plurality of other bridges (not shown) having the same functions as the host-PCI bus bridge 1 described above have the host-PCI bus bridge 1 and the ROM 9 is inserted into the PCI bus 4 at power-on or hardware reset. It is assumed that there is no function that is reset to a readable state via the PCI-ROM bus bridge 8, and the PCI bus directly under these other bridges includes a bridge and ROM 9 equivalent to the PCI-ROM bus bridge 8. There is no equivalent device. In addition, these other bridges register the PCI slots connected to the respective PCI buses and the device numbers corresponding to the on-board PCI devices in the nonvolatile memory for each effective device number. .
[0037]
Next, after issuing the above configuration data collection start instruction, the initialization program 10 temporarily performs processing different from the configuration header information collection operation of the PCI device such as memory initialization. Thereafter, the initialization program 10 issues a busy check request to the host-PCI bus bridge 1. The check is continued until the busy check request shifts from the busy state to the free state. In this case, if a configuration data collection start instruction has been given to a plurality of other bridges (not shown) having the same function as the host-PCI bus bridge 1, the busy check is also performed for those bridges. Issue a request and confirm the transition to each free state.
[0038]
When the initialization program 10 confirms the free state of the host-PCI bus bridge 1, the initialization program 10 instructs the configuration data collection processing host communication controller 16 to read the configuration header information via the host bus controller 11. .
[0039]
Upon receiving this configuration header information read instruction, the configuration data collection processing host communication controller 16 reads the information of all the configuration headers 20 and the corresponding device number and function number information stored in the configuration header information storage memory 14. To the initialization program 10.
[0040]
The initialization program 10 uses the information of all the configuration headers 20 and the corresponding device number and function number information obtained by the above-described configuration header information read instruction, and uses the on-board PCI device 7 and the optional PCI device 6a, Resource management related to 6b is performed, and the PCI devices 7, 6a and 6b are set (configured). At this time, if the data corresponding to the base address register 23 and the expansion ROM base address 24 is confirmed for a device whose bits 0-6 of the header type 22 of the configuration header 20 are 00h, the size of those resources should be confirmed. Can do.
[0041]
However, for PCI-PCI bridges in which the header type 22 bits 0-6 of the configuration header 20 are 01h, resource information about PCI devices under the PCI-PCI bridge is controlled by the initialization program 10 itself. It is necessary to obtain it.
[0042]
If there are a plurality of other bridges (not shown) having the same function as the host-PCI bus bridge 1, the configuration data collection start instruction and the free state confirmation are performed for these other bridges. Next, the configuration header information is instructed to be read for each bridge, the configuration header information and the corresponding device number and function number information are obtained, and the PCI device on the PCI bus connected to each other bridge Perform resource management and configuration (configuration).
[0043]
As described above, according to the present embodiment, the host-PCI bus bridge 1 uniquely moves to the PCI bus 4 directly below itself while the initialization program 10 performs other processing such as memory configuration. Check if there is a connected PCI device, and if it exists, if the PCI device is a multi-function device, check whether it exists for all functions, and type for existing functions Since the 00h configuration header information is stored in the memory 14 in the host-PCI bus bridge 1, the initialization program 10 only needs to obtain information for the existing functions from the memory 14. . Therefore, even when a multi-function PCI device is used, it is possible to prevent the initialization processing time from deteriorating.
[0044]
In the present embodiment, even in a system having a plurality of host-PCI bus bridges, each host-PCI bus bridge is connected while the initialization program 10 performs other processing such as memory configuration setting. Each of the functions of the PCI device connected to the PCI bus 4 directly below itself is checked for existence, and configuration header information of type 00h regarding the existing function is stored in the memory in the host-PCI bus bridge. Since each is stored, the operation until the configuration header information of the type 00h is collected can be performed in parallel, and the initialization program stores only the information for the existing functions in the memory 14. Can be obtained from
[0045]
【The invention's effect】
As described above, according to the present invention, even when a multi-function PCI device is used, deterioration of the initialization processing time can be prevented. The reason is that the PCI device connected to the PCI bus directly underneath by the host-PCI bus bridge is a multi-function device while the initialization program is performing other processing such as memory configuration. In this case, the presence or absence of all functions is independently confirmed, and the configuration header information related to the existing functions is stored in the memory in the host-PCI bus bridge. This is because it is only necessary to obtain information from the memory for the function that is currently being used.
[0046]
Further, according to the present invention, it is possible to prevent the initialization processing time from deteriorating even in a system having many host-PCI bus bridges. The reason is that each host-PCI bus bridge is connected to the PCI bus directly under the bridge while the initialization program is performing other processing such as memory configuration. All functions are checked for existence, and for existing functions, configuration header information of type 00h is stored in the internal memory of each bridge, and the operation until collecting the configuration header information is performed. This is because the initialization program can obtain information for the existing functions from its internal memory.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an embodiment of the present invention.
FIG. 2 is a diagram illustrating an exemplary format of a configuration header of a configuration register.
[Explanation of symbols]
1 Host-PCI bus bridge 2 Processor 3 Host bus 4 PCI bus 5a, 5b, 5c PCI slot 6a, 6b Optional PCI device 7 On-board PCI device 8 PCI-ROM bus bridge 9 Read-only memory (ROM)
10 Initialization program 11 Host bus controller 12 PCI bus controller 13 Non-volatile memory for valid device number 14 Configuration header information storage memory 15 Configuration data collection controller 16 Configuration data collection processing communication controller 20 Configuration header 21 Vendor ID
22 Header type 23 Base address register 24 Expansion ROM base address

Claims (3)

One or more host-PCI bus bridges and a processor are connected to each other via a host bus, and one or more PCI slots, an on-board PCI device and a PCI-ROM bus bridge each have one or more PCIs. The PCI slot is connected to the host-PCI bus bridge, and an optional PCI device can be connected to the PCI slot. The on-board PCI device, the optional PCI device, and the host-PCI bus bridge are configured. A first memory storing an initialization program to be set is an information processing apparatus connected to the PCI bus via the PCI-ROM bus bridge ;
The host-PCI bus bridge is
A second memory storing valid device numbers corresponding to all the on-board PCI devices and PCI slots connected to the PCI device;
A third memory for storing configuration header information;
Configuration header information of function number 0 in the on-board PCI device and optional PCI device corresponding to all device numbers stored in the second memory in response to an instruction to start configuration header information collection of the initialization program Is collected and stored in the third memory, and when the configuration header information is multi-function, the presence or absence of all functions is further confirmed, and the configuration header information related to the existing functions is collected. And a configuration data collection processing means for storing in the third memory ,
The initialization program stored in the first memory executes another process once after the configuration header information collection operation start instruction by the configuration data collection processing means, and then executes a configuration process by the configuration data collection processing means. A busy check request for confirming that the collection of configuration header information has been completed is issued to the host-PCI bus bridge, and a free check indicating that the collection of the configuration header information has been completed in response to the busy check request When there is a response from the configuration data collection processing means, the initialization program, based on the configuration header information obtained by reading the configuration header information stored in the third memory, The on-board PCI device The information processing apparatus and performs resource management and configuration of the chair and optional PCI device.   The initialization program is read and executed by the processor via the host bus, the host-PCI bus bridge, the PCI bus, and the PCI-ROM bus bridge at power-on or hardware reset. The information processing apparatus according to claim 1, wherein: The configuration data collection processing means receives a configuration header information collection operation start instruction of the initialization program, a read means for performing a read operation of the second memory, and the second data read by the read means Judgment for judging whether or not the configuration header information of the function number 0 is valid in the on-board PCI device and the optional PCI device corresponding to the device number from the memory, for all device numbers stored in the second memory If the PCI device corresponding to the configuration header information is a multi-function device when it is valid, the presence / absence of all functions is also confirmed, and the configuration for the existing function is checked. The information processing apparatus according to claim 1, characterized in that it comprises a storage means for storing the Deployment header information in the third memory.

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