JP3689264B2

JP3689264B2 - Anti-lock control device and recording medium recording anti-lock control program

Info

Publication number: JP3689264B2
Application number: JP15446799A
Authority: JP
Inventors: 照泰石川
Original assignee: Nidec Elesys Corp
Current assignee: Nidec Elesys Corp
Priority date: 1999-06-02
Filing date: 1999-06-02
Publication date: 2005-08-31
Anticipated expiration: 2019-06-02
Also published as: JP2000344090A

Description

【０００１】
【発明の属する技術分野】
本発明は、車両の各車輪に設けられ車輪の回転に応じて信号を出力する車輪速度センサと、センサからの信号を演算回路にパルスで出力する車輪速パルス出力回路と、車輪速パルス出力回路から送られるパルスから車輪速度を算出する機能を有する２つの演算回路を有し、２つの演算回路で算出した車輪速度を通信することでそれぞれの演算回路の動作に異常が無いかを判定可能とするアンチロック制御装置、及びアンチロック制御のプログラムを記録した記録媒体に関する。
【０００２】
【従来の技術】
図４にアンチロック制御装置の一輪分の全体構成図、図５に従来の制御ユニットの構成を示すブロック図をそれぞれ示す。
【０００３】
先ず、図４を参照してアンチロック制御装置の構成を説明する。アンチロック制御装置はブレーキを操作するブレーキペダル１と、ブレーキの操作に応じて油圧を出力するマスタシリンダ２と、ホイール毎に装着されたブレーキ装置３と、油圧をコントロールするための増圧ソレノイド４と減圧ソレノイド５と、減圧シレノイドを経由して油圧を抜くためのリザーバ７とポンプ６と、ポンプ６を駆動するためのモータ８と、ホイールの速度を検出するための各ホイール毎に設けられたパルサギア９とセンサ１０と、センサ１０からの信号からアンチロック制御をするための駆動信号の演算と出力を行う制御ユニット１１と、制御ユニットにてアンチロック制御装置に異常が検出された場合に乗員に異常の発生を知らせるワーニングランプ１２で構成される。
【０００４】
ここで、制御ユニット１１とブレーキペダル１は、マスタシリンダ２、ポンプ６、モータ８以外は基本的に各ホイール毎に設けられる。
【０００５】
次に、従来の制御ユニットの構成を図５を参照して説明する。従来の制御ユニット１３は、各車輪毎に設けられたパルサギア９とセンサ１０によって構成される車輪回転検出回路１４と、車輪回転検出回路１４からの信号を演算回路（１）１６と演算回路（２）１７にパルスで出力する車輪速パルス出力回路１５と、車輪速パルス出力回路１５から送られるパルスによって車輪速度を算出してアンチロック制御を行うか否かを判定する演算回路（１）１６と、演算回路（１）１６の動作が正常か否かを判定する演算回路（２）１７と、制御ユニット外部のソレノイド４、５やモータ８、ワーニングランプ１２を制御する制御回路１８と、制御回路１８によって動作するソレノイド４、５、モータ８、ワーニングランプ１２で構成される駆動回路１９から構成される。
【０００６】
ここで、演算回路（１）１６と演算回路（２）１７は、車輪速パルス出力回路１５からのパルスに従って車輪速度を演算する機能と、演算した車輪速度をどちらか一方または互いに通信するための通信機能と、演算結果に基づいて制御回路１８にアンチロック制御を行うための駆動信号を出力する機能を有する。
【０００７】
さらに、演算回路（２）１７には、演算回路（１）１６から送られた車輪速度と演算回路（２）１７で算出した車輪速度を比較して演算回路（１）１６の車輪速度演算が正常であるかを判定する機能と、演算回路（１）１６から所定のパルスが送られてくることで演算回路（１）１６の動作が正常であることを判定するウォッチドッグ機能と、演算回路の動作または車輪速演算が異常と判断した場合に制御回路１５にアンチロック制御を停止させるための駆動信号を出力する機能を有する。
【０００８】
このように従来のアンチロック制御装置は、車輪速パルス出力回路１５からのパルス信号をもとに演算回路（１）１６と演算回路（２）１７のそれぞれで車輪速度を算出し、その演算回路（１）１６で算出された車輪速度と、演算回路（２）１７で算出された車輪速度を、それそれの演算回路の通信機能とそれらをつなぐ通信ラインＬ１を使用して一方へ送信または互いに送受信し、それぞれの演算回路で算出した車輪速度を比較して演算回路（１）１６の車輪速度算出に異常が無いかを判定していた。
【０００９】
また、演算回路（１）１６と演算回路（２）１７間で車輪速度の通信が行われないときには、演算回路（１）から所定のパルスを演算回路（２）１７に出力することで演算回路（１）１６の動作に異常が無いかを演算回路（２）１７で判定していた。
【００１０】
【発明が解決しようとする課題】
しかしながら、このような従来のアンチロック制御装置では、演算回路の車輪速度の算出に異常がないかを確認するため、演算回路には車輪速度演算機能と通信機能、さらに車輪速度の通信が行われない場合の動作に異常がないかを判定するウォッチドッグ機能を持つ必要があり演算回路のコストが増加してしまうという欠点がある。
【００１１】
また、互いの算出した車輪速度を演算回路の通信機能を使用して通信する場合、演算回路間に高周波の通信ラインを設定する必要があり制御装置の基板設計の自由度を低下させたり、電界がかけられた状態で動作に不具合を発生させる等の欠点がある。
【００１２】
本発明は、上記の問題点に鑑みてなされたものであり、車輪速パルス出力回路２２から送られるパルスから車輪速を算出する機能を有する演算回路（１）１６および演算回路（２）１７を備え、演算回路（１）１６、演算回路（２）１７間においてそれぞれが算出した車輪速度を通信することで演算回路（１）１６と演算回路（２）１７のそれぞれの動作に異常が無いかを判定可能とすることを特徴としたアンチロック制御装置において、演算回路（１）１６と演算回路（２）１７に高周波で動作する特別な通信機能を要求せず、且つ、その通信方法にウォッチドッグ機能を付加することにより演算回路に要求される機能を削減し、安価な演算回路が使用可能となり、その結果、安価にアンチロック制御装置、及びアンチロック制御のプログラムを記録した記録媒体を提供することを目的とする。
【００１３】
【課題を解決するための手段】
かかる目的を達成するために、本発明による請求項１記載の発明は、車輪の回転から車輪速度を算出する第１の車輪速度算出手段、及び第２の車輪速度算出手段を有するアンチロック制御装置において、第１の車輪速度算出手段が、算出した車輪速度に応じてパルス幅を所定の方式で変換したウォッチドッグ信号を出力し、第２の車輪速度算出手段が、第１の車輪速度算出手段から入力したウォッチドッグ信号に基づいて、第１の車輪速度算出手段の動作の正常性を判定するとともに、第１の車輪速度算出手段と第２の車輪速度算出手段とのいずれか一方の車輪速度算出機能の正常性を判定することを特徴とする。
【００１４】
請求項２記載の発明は、請求項１記載の発明において、第１の車輪速度算出手段と第２の車輪速度算出手段とのいずれか一方の車輪速度算出機能に異常があると判定されたとき、或いは、第１車輪速度算出手段の動作に異常があると判定されたとき、アンチロック制御を停止させることを特徴とする。
【００１５】
請求項３記載の発明は、車輪の回転に応じて車輪速度Ｖ１を算出する第１の車輪速度算出手段と、車輪の回転に応じて車輪速度Ｖ２を算出する第２の車輪速度算出手段と、ウォッチドッグ信号のパルス幅を所定の方式で変換して与えた車輪速度Ｖ１のデータを出力するウォッチドッグ信号出力手段と、車輪速度Ｖ１のデータの入力により得た車輪速度Ｖ１と、第２の車輪速度算出手段にて算出された車輪速度Ｖ２とを比較する車輪速度比較手段と、車輪速度比較手段による比較の結果に基づいて第１の車輪速度算出手段と第２の車輪速度算出手段とのいずれか一方の車輪速度算出機能の正常性を判定する第１の判定手段と、所定の周期時間内におけるウォッチドッグ信号出力手段からの出力パルスの有無に応じて第１の車輪速度算出手段の動作の正常性を判定する第２の判定手段とを有することを特徴とする。
【００１６】
請求項４記載の発明は、請求項３記載の発明において、第２の判定手段は、所定の周期時間内におけるウォッチドッグ信号出力手段からの出力パルスがなかったとき、第１の車輪速度算出手段の動作に異常があると判定することを特徴とする。
【００１７】
請求項５記載の発明は、車輪の回転に応じてパルス信号で出力する車輪速パルス出力手段と、車輪速パルス出力回路から入力したパルス信号に基づいて車輪速度Ｖ１を算出する第１の車輪速度算出手段と、車輪速パルス出力回路から入力したパルス信号に基づいて車輪速度Ｖ２を算出する第２の車輪速度算出手段と、ウォッチドッグ信号のパルス幅を所定の方式で変換して与えた車輪速度Ｖ１のデータを出力するウォッチドッグ信号出力手段と、車輪速度Ｖ１のデータを入力し、入力した車輪速度Ｖ１のデータに所定の変換方式により車輪速度Ｖ１を導出する車輪速度導出手段と、車輪速度導出手段にて導出された車輪速度Ｖ１と、第２の車輪速度算出手段にて算出された車輪速度Ｖ２とを比較する車輪速度比較手段と、車輪速度比較手段による比較の結果に基づいて第１の車輪速度算出手段と第２の車輪速度算出手段とのいずれか一方の車輪速度算出機能の正常性を判定する第１の判定手段と、所定の周期時間内で、車輪速度導出手段にウォッチドッグ信号出力手段からパルスの入力があったか否かを判断する判断手段と、判断手段による判断結果に基づいて第１の車輪速度算出手段の動作の正常性を判定する第２の判定手段とを有することを特徴とする。
【００１８】
請求項６記載の発明は、請求項３又は５記載の発明において、第１の判定手段は、車輪速度Ｖ１と車輪速度Ｖ２との差が予め定めた値より大きな値であったとき、第１の車輪速度算出手段と第２の車輪速度算出手段とのいずれか一方の車輪速度算出機能に異常があると判定することを特徴とする。
【００１９】
請求項７記載の発明は、請求項５記載の発明において、第２の判定手段は、判断手段にてウォッチドッグ信号出力手段からパルスの入力がなかったと判定されたとき、第１の車輪速度算出手段の動作に異常があると判定することを特徴とする。
【００２０】
請求項８記載の発明は、請求項３又は５記載の発明において、第１の判断手段にて第１の車輪速度算出手段と第２の車輪速度算出手段とのいずれか一方の車輪速度算出機能に異常があると判定されたとき、或いは、第２の判断手段にて第１車輪速度算出手段の動作に異常があると判定されたとき、アンチロック制御の警報処理を行うための駆動信号を出力する駆動信号出力手段を有することを特徴とする。
【００２１】
請求項９記載の発明は、請求項３又は５記載の発明において、所定の方式とは、ウォッチドッグ信号出力手段に最低車輪速度を示すパルス幅及び最高車輪速度を示すパルス幅とを予め設定しておき、最低車輪速度を示すパルス幅或いは最高車輪速度を示すパルス幅を基にして車輪速度Ｖ１を示すパルス幅に変換することを特徴とする。
【００２２】
請求項１０記載の発明は、車輪の回転に応じて車輪速度Ｖ１を算出する第１の車輪速度算出手順と、車輪の回転に応じて車輪速度Ｖ２を算出する第２の車輪速度算出手順と、ウォッチドッグ信号のパルス幅を所定の方式で変換して与えた車輪速度Ｖ１のデータを出力するウォッチドッグ信号出力手順と、車輪速度Ｖ１のデータの入力により得た車輪速度Ｖ１と、第２の車輪速度算出手順にて算出された車輪速度Ｖ２とを比較する車輪速度比較手順と、車輪速度比較手順による比較の結果に基づいて第１の車輪速度算出手順と第２の車輪速度算出手順とのいずれか一方の車輪速度算出機能の正常性を判定する第１の判定手順と、所定の周期時間内におけるウォッチドッグ信号出力手順からの出力パルスの有無に応じて第１の車輪速度算出手順の動作の正常性を判定する第２の判定手順とを実行させるためのプログラムを記録している。
【００２３】
請求項１１記載の発明は、請求項１０記載の発明において、第２の判定手順は、所定の周期時間内におけるウォッチドッグ信号出力手順からの出力パルスがなかったとき、第１の車輪速度算出手順の動作に異常があると判定することを特徴とする。
【００２４】
請求項１２記載の発明は、車輪の回転に応じてパルス信号で出力する車輪速パルス出力手順と、車輪速パルス出力回路から入力したパルス信号に基づいて車輪速度Ｖ１を算出する第１の車輪速度算出手順と、車輪速パルス出力回路から入力したパルス信号に基づいて車輪速度Ｖ２を算出する第２の車輪速度算出手順と、ウォッチドッグ信号のパルス幅を所定の方式で変換して与えた車輪速度Ｖ１のデータを出力するウォッチドッグ信号出力手順と、車輪速度Ｖ１のデータを入力し、入力した車輪速度Ｖ１のデータに所定の変換方式により車輪速度Ｖ１を導出する車輪速度導出手順と、車輪速度導出手順にて導出された車輪速度Ｖ１と、第２の車輪速度算出手順にて算出された車輪速度Ｖ２とを比較する車輪速度比較手順と、車輪速度比較手順による比較の結果に基づいて第１の車輪速度算出手順と第２の車輪速度算出手順とのいずれか一方の車輪速度算出機能の正常性を判定する第１の判定手順と、所定の周期時間内で、車輪速度導出手順にウォッチドッグ信号出力手順からパルスの入力があったか否かを判断する判断手順と、判断手順による判断結果に基づいて第１の車輪速度算出手順の動作の正常性を判定する第２の判定手順とを実行させるためのプログラムを記録している。
【００２５】
請求項１３記載の発明は、請求項１０又は１２記載の発明において、第１の判定手順は、車輪速度Ｖ１と車輪速度Ｖ２との差が予め定めた値より大きな値であったとき、第１の車輪速度算出手順と第２の車輪速度算出手順とのいずれか一方の車輪速度算出機能に異常があると判定することを特徴とする。
【００２６】
請求項１４記載の発明は、請求項１２記載の発明において、第２の判定手順は、判断手順にてウォッチドッグ信号出力手順からパルスの入力がなかったと判定されたとき、第１の車輪速度算出手順の動作に異常があると判定することを特徴とする。
【００２７】
請求項１５記載の発明は、請求項１０又は１２記載の発明において、第１の判断手順にて第１の車輪速度算出手順と第２の車輪速度算出手順とのいずれか一方の車輪速度算出機能に異常があると判定されたとき、或いは、第２の判断手順にて第１車輪速度算出手順の動作に異常があると判定されたとき、アンチロック制御の警報処理を行うための駆動信号を出力する駆動信号出力手順を有することを特徴とする。
【００２８】
請求項１６記載の発明は、請求項１０又は１２記載の発明において、所定の方式とは、ウォッチドッグ信号出力手順に最低車輪速度を示すパルス幅及び最高車輪速度を示すパルス幅とを予め設定しておき、最低車輪速度を示すパルス幅或いは最高車輪速度を示すパルス幅を基にして車輪速度Ｖ１を示すパルス幅に変換することを特徴とする。
【００２９】
【発明の実施の形態】
以下、本発明の実施例を添付図面を参照しながら詳細に説明する。
【００３０】
図１に本実施例における制御ユニットの概略構成を示すブロック図、図２に本実施例による演算回路（１）から演算回路（２）へ出力される信号波形の一例、図３に本実施例における演算回路（１）、（２）での処理フローを示す。
【００３１】
図１に示される制御ユニットを図４に示されるアンチロック制御装置の全体構成図を参照しながら説明する。制御ユニット２０は、各車輪に設けられたパルサギア９とセンサ１０によって構成される車輪回転検出回路２１と、車輪回転検出回路２１からの信号を演算回路（１）２３と演算回路（２）２４にパルスで出力する車輪速パルス出力回路２２と、車輪速パルス出力回路２２から送られるパルスによって車輪速度を算出してアンチロック制御を行うか否かを判定する演算回路（１）２３と、演算回路（１）２３の動作が正常であるか否かを判定する演算回路（２）２４と、制御ユニット２０外部のソレノイド４、５やモータ８、ワーニングランプ１２を制御する制御回路２５と、制御回路２５の制御によって動作するソレノイド４，５、モータ８、ワーニングランプ１２で構成される駆動回路２６から構成される。
【００３２】
ここで、演算回路（１）２３と演算回路（２）２４は、車輪速パルス出力回路２２から出力されたパルスに従って車輪速度を演算する機能と、算出した車輪速度を予め決められた所定の信号に変換してそれを出力する機能と、演算結果に基づいて制御回路２５にアンチロック制御を行うための駆動信号を出力する機能を有する。
【００３３】
さらに、演算回路（２）２４には、演算回路（１）２３から送られた信号を車輪速度へ変換する機能と、演算回路（１）２３から送られた車輪速度と演算回路（２）２４で算出した車輪速度を比較して演算回路（１）２３の車輪速度演算が正常であるか否かを判定する機能と、演算回路（１）２３から送られた信号から演算回路（１）２３の動作が正常であることを判定するウォッチドッグ機能と、演算回路（１）の動作または車輪速演算が異常と判断した場合に制御回路２５にアンチロック制御を停止させるための駆動信号を出力する機能を有する。
【００３４】
次に、図２を参照しながら本実施例における演算回路（１）２３から演算回路（２）２４へ出力される信号波形サンプルを説明する。信号の周期Ｔ１は所定の決められた時間、例えば演算回路（１）２３の１サイクルの演算実行時間などを示し、Ｈｉ時間はそのときの演算回路（１）２３で算出した車輪速度を表す。
【００３５】
ここで、演算回路（１）２３は、算出した車輪速度を演算回路（２）２４へ送信する信号のＨｉ時間に変換するときは、波形Ｗ２に示される現在の車輪速度Ｈｉ時間Ｔ３のパルス幅は、互いに予め設定されている波形Ｗ１に示される最低車輪速度のＨｉ時間Ｔ２のパルス幅を最小、波形Ｗ３に示される最高車輪速度のＨｉ時間Ｔ４のパルス幅を最大のものとされ、このなかで、波形Ｗ１に示される最低車輪速度のＨｉ時間Ｔ２又は波形Ｗ３に示される最高車輪速度のＨｉ時間Ｔ４がもつパルス幅を基に与えられる。例えば、
Ｔ３＝Ｔ４／２，Ｔ４／３，・・・・
または、
Ｔ３＝Ｔ２×２，Ｔ２×３，・・・・
といった具合に与えられる。
【００３６】
図３に示されるフローチャートを参照しながら本実施例における動作例を説明する。各車輪毎に設けられたパルサギア９とセンサ１０によって構成される車輪回転検出回路２１からの信号は、車輪速パルス出力回路２２によって矩形波の信号に変換されて演算回路（１）２３と演算回路（２）２４に出力される。
【００３７】
それぞれの演算回路（１）２３、演算回路（２）２４は、車輪速パルス出力回路２２から車輪速パルスを受信すると（ステップＳ１、ステップＳ６）、受信した車輪速パルスに基づき車輪速度Ｖ１、Ｖ２を算出する（ステップＳ２、ステップＳ７）。
【００３８】
次に、演算回路（１）２３では、ステップＳ２にて算出した車輪速度を演算回路（２）２４へ送信する信号のＨｉ時間に変換する。このとき、演算回路（１）２３では、図２に示すように予め決めておいた最低車輪速度のＨｉ時間Ｔ２と最高車輪速度のＨｉ時間Ｔ４から現在の車輪速のＨｉ時間Ｔ３が決定される一方で（ステップＳ３）、自らの演算時間が１サイクルの演算実行時間を経過したか否かが判定され（ステップＳ４）、ここで１サイクルの演算実行時間が経過していないと判定されると（ステップＳ４／ＮＯ）、演算時間が１サイクルの演算実行時間を経過するまで処理を続行する。
【００３９】
ステップＳ４の処理において、演算回路（１）２３が自らの演算時間が１サイクルの演算実行時間を経過したと判定されると（ステップＳ４／ＹＥＳ）、所定の予め決められた信号の周期Ｔ１、ここでは演算回路（１）２３の１サイクルの演算実行時間毎に、演算回路（１）２３はステップＳ３にて決められた現在の車輪速のＨｉ時間Ｔ３パルスを演算回路（２）２４へ出力し（ステップＳ５）、再びステップＳ１の処理へ戻る。
【００４０】
演算回路（２）２４では演算回路（１）２３から出力された現在の車輪速のＨｉ時間Ｔ３パルスの入力を待つ。このとき演算回路（２）２４では、演算回路（１）２３から現在の車輪速のＨｉ時間Ｔ３パルスの入力があったか否かの判定が行われるが（ステップＳ８）、この判断において演算回路（１）２３からのパルスの入力がないと判定されると（ステップＳ８／ＮＯ）、その演算回路（１）２３からのパルス入力の待ち時間が上記の演算回路（１）１２の１サイクルの演算実行時間をオーバーしたか否かの判定が行われ（ステップＳ９）、その待ち時間が１サイクルの演算実行時間をオーバーしたと判定された場合は（ステップＳ９／ＹＥＳ）、アンチロック制御装置の警報処理が実行される（ステップＳ１０）。
【００４１】
ここで、アンチロック制御装置の警報処理とは、演算回路（２）２４が制御回路２５を介して駆動回路２６へソレノイド４，５、モータ８の停止、ワーニングランプ１２点灯等の動作の駆動信号を出力することである。
【００４２】
また、ステップＳ９の判定にて、その待ち時間が１サイクルの演算実行時間がオーバーしていないと判定された場合は（ステップＳ９／ＮＯ）、ステップＳ８の処理に戻り、再び演算回路（１）２３から演算回路（２）２４へのパルスの入力があったか否かを判定する。
【００４３】
演算回路（１）２３におけるステップＳ３の処理では、演算回路（１）２３は、車輪速パルス出力回路２２から入力した車輪速パルス信号から車輪速度を算出し、最低車輪速度Ｗ１のＨｉ時間Ｔ２或いは最高車輪速度Ｗ３のＨｉ時間Ｔ４から設定された現在の車輪速度Ｗ２のＨｉ時間Ｔ３を与え、このＨｉ時間Ｔ３をもつパルス信号を演算回路（２）２４へ出力していたが、演算回路（１）２３からのパルス信号が１サイクルの演算実行時間をオーバーせず、演算回路（２）２４へ入力されたと判定されたときは（ステップＳ８／ＹＥＳ）、演算回路（２）２４においては逆に、入力したパルス信号のＨｉ時間Ｔ３と、演算回路（１）２３と同様に予め設定されている最低車輪速度のＨｉ時間Ｔ２と最高車輪速度のＨｉ時間Ｔ４から、演算回路（１）２３が算出した車輪速度を導出する。
【００４４】
次に、演算回路（２）２４においては、演算回路（２）２４が車輪速パルス出力回路２２から入力した車輪速パルス信号に基づいて算出した車輪速度Ｖ２と、演算回路（２）２４が演算回路（１）２３から入力した波形Ｗ２のパルス信号を基に導出した車輪速度Ｖ１を比較し、その差が予め定められたＶ３以下であるか否かを判定する（ステップＳ１２）。この判断において車輪速度Ｖ２と車輪速度Ｖ１の差がＶ３以下であると判定されたとき（ステップＳ１２／ＹＥＳ）、演算回路（２）２４は、それぞれの演算回路は正常に動作していると判断し、ステップＳ６の処理へ戻り繰り返し実行される。
【００４５】
ステップＳ１２の処理において、演算回路（１）２３で算出した車輪速度Ｖ１と演算回路（２）２４で算出した車輪速度Ｖ２の差がＶ３より大きいと判定されたときは（ステップＳ１２／ＮＯ）、演算回路（２）２４は、演算回路のいずれか一方の車輪速度の算出機能に異常があると判断し、ステップＳ１０のアンチロック制御装置の警報処理が実行される。
【００４６】
尚、これら図２に示される車輪速度のデータをウォッチドッグ信号のパルス幅に変換して行う動作は、アンチロック制御を行うためのその他の演算の一部としてか又はアンチロック制御を行うためのその他の演算と並列して行われる。
【００４７】
以上、本発明の実施例を記述したが、本発明は上記の実施例に限定されるものではなく、特許請求の範囲の記載を逸脱することなく種々の設計変更を行うことが可能である。
【００４８】
【発明の効果】
以上の説明より明らかなように、本発明によれば、一方の演算回路から他方の演算回路へ送る車輪速度のデータをウォッチドッグ信号のパルス幅に変換して行うことで安価な演算回路を使用することができるアンチロック制御装置、及びアンチロック制御のプログラムを記録した記録媒体を提供することが可能となる。
【図面の簡単な説明】
【図１】本発明の一実施例による制御ユニットの概略構成を示すブロック図である。
【図２】本発明の一実施例による演算回路（１）から演算回路（２）へ出力される信号波形を示す図である。
【図３】本発明の一実施例による演算回路（１）、（２）における処理動作の流れを示すフローチャートである。
【図４】本発明の一実施例におけるアンチロック制御装置の一輪分の全体構成図である。
【図５】従来技術におけるアンチロック制御装置の制御ユニットの構成例を示すブロック図である。
【符号の説明】
２０制御ユニット
２１車輪回転検出回路
２２車輪速パルス出力回路
２３演算回路（１）
２４演算回路（２）
２５制御回路
２６駆動回路[0001]
BACKGROUND OF THE INVENTION
The present invention includes a wheel speed sensor that is provided at each wheel of a vehicle and outputs a signal according to the rotation of the wheel, a wheel speed pulse output circuit that outputs a signal from the sensor to a calculation circuit as a pulse, and a wheel speed pulse output circuit It is possible to determine whether there is any abnormality in the operation of each arithmetic circuit by communicating the wheel speed calculated by the two arithmetic circuits, having two arithmetic circuits that have the function of calculating the wheel speed from the pulses sent from The present invention relates to an anti-lock control device and a recording medium on which an anti-lock control program is recorded.
[0002]
[Prior art]
FIG. 4 is an overall configuration diagram for one wheel of the antilock control device, and FIG. 5 is a block diagram showing the configuration of a conventional control unit.
[0003]
First, the configuration of the antilock control device will be described with reference to FIG. The anti-lock control device includes a brake pedal 1 that operates a brake, a master cylinder 2 that outputs hydraulic pressure in response to the operation of the brake, a brake device 3 that is mounted for each wheel, and a pressure-increasing solenoid 4 that controls the hydraulic pressure. And a decompression solenoid 5, a reservoir 7 and a pump 6 for releasing hydraulic pressure via a decompression silenoid, a motor 8 for driving the pump 6, and a wheel for detecting the speed of the wheel. The pulsar gear 9, the sensor 10, the control unit 11 that calculates and outputs a drive signal for performing antilock control from the signal from the sensor 10, and an occupant when an abnormality is detected in the antilock control device by the control unit It comprises a warning lamp 12 for informing the occurrence of an abnormality.
[0004]
Here, the control unit 11 and the brake pedal 1 are basically provided for each wheel except for the master cylinder 2, the pump 6, and the motor 8.
[0005]
Next, the configuration of the conventional control unit will be described with reference to FIG. The conventional control unit 13 includes a wheel rotation detection circuit 14 composed of a pulsar gear 9 and a sensor 10 provided for each wheel, a signal from the wheel rotation detection circuit 14 and an arithmetic circuit (1) 16 and an arithmetic circuit (2 ) A wheel speed pulse output circuit 15 that outputs a pulse to 17; an arithmetic circuit (1) 16 that determines whether or not to perform antilock control by calculating a wheel speed based on a pulse sent from the wheel speed pulse output circuit 15; An arithmetic circuit (2) 17 for determining whether or not the operation of the arithmetic circuit (1) 16 is normal, a control circuit 18 for controlling the solenoids 4 and 5 outside the control unit, the motor 8 and the warning lamp 12, and a control circuit The drive circuit 19 includes solenoids 4 and 5 that are operated by a motor 18, a motor 8, and a warning lamp 12.
[0006]
Here, the arithmetic circuit (1) 16 and the arithmetic circuit (2) 17 are used to communicate the wheel speed according to the pulse from the wheel speed pulse output circuit 15 and the calculated wheel speed or to communicate with each other. It has a communication function and a function of outputting a drive signal for performing antilock control to the control circuit 18 based on the calculation result.
[0007]
Further, the arithmetic circuit (2) 17 compares the wheel speed sent from the arithmetic circuit (1) 16 with the wheel speed calculated by the arithmetic circuit (2) 17 to calculate the wheel speed of the arithmetic circuit (1) 16. A function for determining whether it is normal, a watchdog function for determining whether the operation of the arithmetic circuit (1) 16 is normal when a predetermined pulse is sent from the arithmetic circuit (1) 16, and an arithmetic circuit The control circuit 15 has a function of outputting a drive signal for stopping the antilock control when it is determined that the operation or wheel speed calculation is abnormal.
[0008]
Thus, the conventional anti-lock control device calculates the wheel speed by each of the arithmetic circuit (1) 16 and the arithmetic circuit (2) 17 based on the pulse signal from the wheel speed pulse output circuit 15, and the arithmetic circuit. (1) The wheel speed calculated in 16 and the wheel speed calculated in the arithmetic circuit (2) 17 are transmitted to one or the other using the communication function of the arithmetic circuit and the communication line L1 connecting them. Transmission / reception was performed, and the wheel speeds calculated by the respective arithmetic circuits were compared to determine whether the calculation of the wheel speed by the arithmetic circuit (1) 16 was normal.
[0009]
When the wheel speed is not communicated between the arithmetic circuit (1) 16 and the arithmetic circuit (2) 17, the arithmetic circuit (1) outputs a predetermined pulse to the arithmetic circuit (2) 17, thereby calculating the arithmetic circuit. (1) The arithmetic circuit (2) 17 determines whether the operation of 16 is normal.
[0010]
[Problems to be solved by the invention]
However, in such a conventional anti-lock control device, in order to check whether there is any abnormality in the calculation of the wheel speed of the arithmetic circuit, the arithmetic circuit is communicated with the wheel speed arithmetic function and the communication function, and further the wheel speed is communicated. There is a disadvantage that it is necessary to have a watchdog function for judging whether there is an abnormality in the operation when there is no operation, and the cost of the arithmetic circuit increases.
[0011]
In addition, when communicating the calculated wheel speeds using the communication function of the arithmetic circuit, it is necessary to set a high-frequency communication line between the arithmetic circuits, reducing the degree of freedom in the design of the control device board, There are disadvantages such as causing malfunctions in the state where the operation is applied.
[0012]
The present invention has been made in view of the above problems, and includes an arithmetic circuit (1) 16 and an arithmetic circuit (2) 17 having a function of calculating a wheel speed from a pulse sent from the wheel speed pulse output circuit 22. Whether the operation of each of the arithmetic circuit (1) 16 and the arithmetic circuit (2) 17 is normal by communicating the calculated wheel speed between the arithmetic circuit (1) 16 and the arithmetic circuit (2) 17 In the anti-lock control device characterized in that the arithmetic circuit (1) 16 and the arithmetic circuit (2) 17 do not require a special communication function that operates at a high frequency, and the communication method is a watch. By adding the dog function, the functions required for the arithmetic circuit are reduced, and an inexpensive arithmetic circuit can be used. As a result, the anti-lock control device and the anti-lock control program can be inexpensively used And to provide a recording medium which records a beam.
[0013]
[Means for Solving the Problems]
In order to achieve this object, the invention according to claim 1 of the present invention includes a first wheel speed calculating means for calculating a wheel speed from rotation of a wheel, and an antilock control device having a second wheel speed calculating means. The first wheel speed calculating means outputs a watchdog signal in which the pulse width is converted by a predetermined method in accordance with the calculated wheel speed, and the second wheel speed calculating means is the first wheel speed calculating means. The normality of the operation of the first wheel speed calculation means is determined based on the watchdog signal input from the wheel speed of either one of the first wheel speed calculation means and the second wheel speed calculation means. The normality of the calculation function is determined.
[0014]
The invention according to claim 2 is the invention according to claim 1, wherein it is determined that there is an abnormality in the wheel speed calculation function of either the first wheel speed calculation means or the second wheel speed calculation means. Alternatively, when it is determined that there is an abnormality in the operation of the first wheel speed calculation means, the antilock control is stopped.
[0015]
The invention according to claim 3 is a first wheel speed calculating means for calculating the wheel speed V1 according to the rotation of the wheel, a second wheel speed calculating means for calculating the wheel speed V2 according to the rotation of the wheel, The watchdog signal output means for outputting the wheel speed V1 data obtained by converting the pulse width of the watchdog signal by a predetermined method, the wheel speed V1 obtained by inputting the wheel speed V1 data, and the second wheel Which of the wheel speed comparison means for comparing the wheel speed V2 calculated by the speed calculation means, and the first wheel speed calculation means and the second wheel speed calculation means based on the comparison result by the wheel speed comparison means? The first determination means for determining the normality of one of the wheel speed calculation functions and the operation of the first wheel speed calculation means in accordance with the presence or absence of an output pulse from the watchdog signal output means within a predetermined cycle time. And having a second judging means for judging the normality of the.
[0016]
Invention of claim 4, wherein, in the third aspect of the present invention, the second determining means, when the output pulse from the watchdog signal output means in a predetermined cycle time has Tsu Naka, first wheel speed calculation It is characterized by determining that the operation of the means is abnormal.
[0017]
The invention according to claim 5 is the first wheel speed for calculating the wheel speed V1 based on the wheel speed pulse output means for outputting a pulse signal according to the rotation of the wheel and the pulse signal input from the wheel speed pulse output circuit. A calculation means; a second wheel speed calculation means for calculating the wheel speed V2 based on a pulse signal input from the wheel speed pulse output circuit; and a wheel speed obtained by converting the pulse width of the watchdog signal by a predetermined method. A watchdog signal output means for outputting V1 data, wheel speed derivation means for inputting wheel speed V1 data, and deriving the wheel speed V1 from the inputted wheel speed V1 data by a predetermined conversion method; and wheel speed derivation A wheel speed comparing means for comparing the wheel speed V1 derived by the means with the wheel speed V2 calculated by the second wheel speed calculating means, and a wheel speed comparing means. First determination means for determining the normality of the wheel speed calculation function of one of the first wheel speed calculation means and the second wheel speed calculation means based on the result of the comparison, and within a predetermined cycle time And determining whether the wheel speed deriving means has received a pulse from the watchdog signal output means, and determining the normality of the operation of the first wheel speed calculating means based on the determination result by the determining means. And a second determination unit.
[0018]
According to a sixth aspect of the present invention, in the third or fifth aspect of the invention, the first determination means is configured such that when the difference between the wheel speed V1 and the wheel speed V2 is greater than a predetermined value, It is determined that there is an abnormality in one of the wheel speed calculation functions of the wheel speed calculation means and the second wheel speed calculation means.
[0019]
Invention of claim 7, wherein, in the invention of claim 5, wherein the second determining means, when the input of the pulse is determined to Tsu cry from the watchdog signal output means at decision means, first wheel speed It is determined that there is an abnormality in the operation of the calculation means.
[0020]
The invention according to claim 8 is the invention according to claim 3 or 5, wherein the first determination means uses one of the first wheel speed calculation means and the second wheel speed calculation means. When it is determined that there is an abnormality, or when it is determined by the second determination means that there is an abnormality in the operation of the first wheel speed calculation means, a drive signal for performing an anti-lock control alarm process is provided. It has a drive signal output means for outputting.
[0021]
The invention according to claim 9 is the invention according to claim 3 or 5, wherein the predetermined method is that a pulse width indicating the minimum wheel speed and a pulse width indicating the maximum wheel speed are preset in the watchdog signal output means. In addition, the pulse width indicating the minimum wheel speed or the pulse width indicating the maximum wheel speed is converted into a pulse width indicating the wheel speed V1.
[0022]
The invention according to claim 10 is a first wheel speed calculation procedure for calculating the wheel speed V1 according to the rotation of the wheel, a second wheel speed calculation procedure for calculating the wheel speed V2 according to the rotation of the wheel, A watchdog signal output procedure for outputting the wheel speed V1 data obtained by converting the pulse width of the watchdog signal by a predetermined method, the wheel speed V1 obtained by inputting the wheel speed V1 data, and the second wheel Which of the wheel speed comparison procedure for comparing the wheel speed V2 calculated in the speed calculation procedure and the first wheel speed calculation procedure and the second wheel speed calculation procedure based on the result of comparison by the wheel speed comparison procedure A first determination procedure for determining the normality of one of the wheel speed calculation functions, and a first wheel speed calculation procedure according to the presence or absence of an output pulse from the watchdog signal output procedure within a predetermined cycle time. It records a program for executing a second determination procedure for determining the normality of the work.
[0023]
Invention of claim 11, wherein, in the invention of claim 10, the second determination step, when the output pulse from the watchdog signal output procedure in the predetermined cycle time has Tsu Naka, first wheel speed calculation It is determined that there is an abnormality in the operation of the procedure.
[0024]
The invention according to claim 12 is the first wheel speed for calculating the wheel speed V1 based on the wheel speed pulse output procedure for outputting the pulse signal according to the rotation of the wheel and the pulse signal input from the wheel speed pulse output circuit. A calculation procedure, a second wheel speed calculation procedure for calculating the wheel speed V2 based on the pulse signal input from the wheel speed pulse output circuit, and a wheel speed obtained by converting the pulse width of the watchdog signal by a predetermined method A watchdog signal output procedure for outputting V1 data, a wheel speed derivation procedure for inputting wheel speed V1 data, and deriving the wheel speed V1 from the inputted wheel speed V1 data by a predetermined conversion method, and wheel speed derivation A wheel speed comparison procedure for comparing the wheel speed V1 derived in the procedure with the wheel speed V2 calculated in the second wheel speed calculation procedure, and a wheel speed comparison procedure A first determination procedure for determining the normality of one of the wheel speed calculation functions of the first wheel speed calculation procedure and the second wheel speed calculation procedure based on the result of the comparison, and within a predetermined cycle time Thus, a determination procedure for determining whether or not a pulse is input from the watch dog signal output procedure in the wheel speed derivation procedure, and the normality of the operation of the first wheel speed calculation procedure is determined based on the determination result of the determination procedure. A program for executing the second determination procedure is recorded.
[0025]
According to a thirteenth aspect of the present invention, in the tenth or twelfth aspect of the present invention, the first determination procedure is performed when the difference between the wheel speed V1 and the wheel speed V2 is larger than a predetermined value. It is determined that there is an abnormality in one of the wheel speed calculation functions of the wheel speed calculation procedure and the second wheel speed calculation procedure.
[0026]
Invention of claim 14, wherein, in the invention of claim 12 wherein, the second determination step, when the input pulse from the watchdog signal output procedure is determined to have Tsu Naka at decision procedure, the first wheel speed It is determined that there is an abnormality in the operation of the calculation procedure.
[0027]
The invention according to claim 15 is the wheel speed calculation function according to any one of the first wheel speed calculation procedure and the second wheel speed calculation procedure in the first determination procedure in the invention according to claim 10 or 12. When it is determined that there is an abnormality in the vehicle, or when it is determined in the second determination procedure that there is an abnormality in the operation of the first wheel speed calculation procedure, a drive signal for performing an anti-lock control alarm process is provided. It has a drive signal output procedure for outputting.
[0028]
In the invention described in claim 16, in the invention described in claim 10 or 12, the predetermined method is that a pulse width indicating the minimum wheel speed and a pulse width indicating the maximum wheel speed are preset in the watch dog signal output procedure. In addition, the pulse width indicating the minimum wheel speed or the pulse width indicating the maximum wheel speed is converted into a pulse width indicating the wheel speed V1.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0030]
FIG. 1 is a block diagram showing a schematic configuration of a control unit in the present embodiment, FIG. 2 shows an example of a signal waveform output from the arithmetic circuit (1) according to the present embodiment to the arithmetic circuit (2), and FIG. 3 shows the present embodiment. The processing flow in the arithmetic circuits (1) and (2) in FIG.
[0031]
The control unit shown in FIG. 1 will be described with reference to the overall configuration diagram of the antilock control device shown in FIG. The control unit 20 includes a wheel rotation detection circuit 21 constituted by a pulsar gear 9 and a sensor 10 provided on each wheel, and signals from the wheel rotation detection circuit 21 to an arithmetic circuit (1) 23 and an arithmetic circuit (2) 24. A wheel speed pulse output circuit 22 that outputs in pulses, an arithmetic circuit (1) 23 that determines whether or not to perform antilock control by calculating a wheel speed based on pulses sent from the wheel speed pulse output circuit 22, and an arithmetic circuit (1) An arithmetic circuit (2) 24 for determining whether or not the operation of 23 is normal, a control circuit 25 for controlling the solenoids 4, 5 and motor 8, and the warning lamp 12 outside the control unit 20, and a control circuit The drive circuit 26 includes solenoids 4, 5, a motor 8, and a warning lamp 12 that are operated under control of 25.
[0032]
Here, the arithmetic circuit (1) 23 and the arithmetic circuit (2) 24 have a function of calculating the wheel speed in accordance with the pulse output from the wheel speed pulse output circuit 22, and a predetermined signal for calculating the calculated wheel speed. And a function of outputting a drive signal for performing antilock control to the control circuit 25 based on the calculation result.
[0033]
Further, the arithmetic circuit (2) 24 has a function of converting the signal sent from the arithmetic circuit (1) 23 into a wheel speed, the wheel speed sent from the arithmetic circuit (1) 23, and the arithmetic circuit (2) 24. A function for determining whether or not the wheel speed calculation of the arithmetic circuit (1) 23 is normal by comparing the wheel speeds calculated in the above, and the arithmetic circuit (1) 23 from the signal sent from the arithmetic circuit (1) 23 A watchdog function for determining that the operation of the vehicle is normal, and a drive signal for stopping the antilock control is output to the control circuit 25 when it is determined that the operation of the arithmetic circuit (1) or the wheel speed calculation is abnormal. It has a function.
[0034]
Next, signal waveform samples output from the arithmetic circuit (1) 23 to the arithmetic circuit (2) 24 in this embodiment will be described with reference to FIG. The period T1 of the signal indicates a predetermined time, for example, the calculation execution time of one cycle of the arithmetic circuit (1) 23, and the Hi time indicates the wheel speed calculated by the arithmetic circuit (1) 23 at that time.
[0035]
Here, when the arithmetic circuit (1) 23 converts the calculated wheel speed into the Hi time of the signal transmitted to the arithmetic circuit (2) 24, the pulse width of the current wheel speed Hi time T3 indicated by the waveform W2. The pulse width of Hi time T2 of the lowest wheel speed shown in the waveform W1 set in advance mutually is the minimum, and the pulse width of Hi time T4 of the highest wheel speed shown in the waveform W3 is made maximum, Thus, it is given based on the pulse width of the Hi time T2 of the lowest wheel speed shown in the waveform W1 or the Hi time T4 of the highest wheel speed shown in the waveform W3. For example,
T3 = T4 / 2, T4 / 3, ...
Or
T3 = T2 × 2, T2 × 3, ...
And so on.
[0036]
An example of operation in the present embodiment will be described with reference to the flowchart shown in FIG. A signal from a wheel rotation detection circuit 21 constituted by a pulsar gear 9 and a sensor 10 provided for each wheel is converted into a rectangular wave signal by a wheel speed pulse output circuit 22, and the arithmetic circuit (1) 23 and the arithmetic circuit. (2) Output to 24.
[0037]
When the arithmetic circuit (1) 23 and the arithmetic circuit (2) 24 receive the wheel speed pulse from the wheel speed pulse output circuit 22 (step S1, step S6), the wheel speeds V1, V2 are based on the received wheel speed pulse. Is calculated (step S2, step S7).
[0038]
Next, the arithmetic circuit (1) 23 converts the wheel speed calculated in step S2 into the Hi time of a signal to be transmitted to the arithmetic circuit (2) 24. At this time, the arithmetic circuit (1) 23 determines the Hi time T3 of the current wheel speed from the Hi time T2 of the lowest wheel speed and the Hi time T4 of the highest wheel speed, as shown in FIG. On the other hand (step S3), it is determined whether or not its calculation time has passed one cycle of calculation execution time (step S4). If it is determined that one cycle of calculation execution time has not elapsed, (Step S4 / NO), the processing is continued until the calculation time has passed one cycle of calculation execution time.
[0039]
In the processing of step S4, when it is determined that the arithmetic circuit (1) 23 has passed its one arithmetic operation time of one cycle (step S4 / YES), a predetermined predetermined signal cycle T1, Here, every calculation operation time of one cycle of the arithmetic circuit (1) 23, the arithmetic circuit (1) 23 outputs the current wheel speed Hi time T3 pulse determined in step S3 to the arithmetic circuit (2) 24. (Step S5), the process returns to Step S1 again.
[0040]
The arithmetic circuit (2) 24 waits for the input of the current wheel speed Hi time T3 pulse output from the arithmetic circuit (1) 23. At this time, the arithmetic circuit (2) 24 determines whether or not the current wheel speed Hi time T3 pulse has been input from the arithmetic circuit (1) 23 (step S8). ) When it is determined that no pulse is input from 23 (step S8 / NO), the waiting time of the pulse input from the arithmetic circuit (1) 23 is one cycle of execution of the arithmetic circuit (1) 12. It is determined whether or not the time has been exceeded (step S9), and if it is determined that the waiting time has exceeded the calculation execution time of one cycle (step S9 / YES), the alarm processing of the antilock control device Is executed (step S10).
[0041]
Here, the alarm processing of the anti-lock control device means that the arithmetic circuit (2) 24 sends a drive signal to the drive circuit 26 via the control circuit 25 for operations such as stopping the solenoids 4, 5 and the motor 8, and turning on the warning lamp 12. Is output.
[0042]
If it is determined in step S9 that the waiting time does not exceed the calculation execution time of one cycle (step S9 / NO), the process returns to step S8, and the calculation circuit (1) is again processed. 23, it is determined whether or not a pulse is input to the arithmetic circuit (2) 24.
[0043]
In the process of step S3 in the arithmetic circuit (1) 23, the arithmetic circuit (1) 23 calculates the wheel speed from the wheel speed pulse signal input from the wheel speed pulse output circuit 22, and the Hi time T2 of the minimum wheel speed W1 or The Hi time T3 of the current wheel speed W2 set from the Hi time T4 of the maximum wheel speed W3 is given, and a pulse signal having this Hi time T3 is output to the arithmetic circuit (2) 24. ) When it is determined that the pulse signal from 23 does not exceed the calculation execution time of one cycle and is input to the arithmetic circuit (2) 24 (step S8 / YES), the arithmetic circuit (2) 24 reverses From the Hi time T3 of the input pulse signal, and the Hi time T2 of the lowest wheel speed and the Hi time T4 of the highest wheel speed set in advance as in the calculation circuit (1) 23, the calculation time (1) 23 to derive a wheel speed calculated.
[0044]
Next, in the arithmetic circuit (2) 24, the arithmetic circuit (2) 24 calculates the wheel speed V2 calculated based on the wheel speed pulse signal inputted from the wheel speed pulse output circuit 22, and the arithmetic circuit (2) 24 calculates. The wheel speed V1 derived based on the pulse signal of the waveform W2 input from the circuit (1) 23 is compared, and it is determined whether or not the difference is equal to or less than a predetermined V3 (step S12). When it is determined in this determination that the difference between the wheel speed V2 and the wheel speed V1 is equal to or less than V3 (step S12 / YES), the arithmetic circuit (2) 24 determines that the respective arithmetic circuits are operating normally. Then, the process returns to step S6 and is repeatedly executed.
[0045]
In the process of step S12, when it is determined that the difference between the wheel speed V1 calculated by the arithmetic circuit (1) 23 and the wheel speed V2 calculated by the arithmetic circuit (2) 24 is larger than V3 (step S12 / NO), The arithmetic circuit (2) 24 determines that there is an abnormality in the function for calculating the wheel speed of any one of the arithmetic circuits, and the alarm processing of the antilock control device in step S10 is executed.
[0046]
Note that the operation performed by converting the wheel speed data shown in FIG. 2 into the pulse width of the watchdog signal may be performed as part of other calculations for performing antilock control or for performing antilock control. Performed in parallel with other operations.
[0047]
As mentioned above, although the Example of this invention was described, this invention is not limited to said Example, A various design change is possible without deviating from description of a claim.
[0048]
【The invention's effect】
As is clear from the above description, according to the present invention, an inexpensive arithmetic circuit is used by converting the wheel speed data sent from one arithmetic circuit to the other arithmetic circuit into the pulse width of the watchdog signal. It is possible to provide an anti-lock control device that can perform the recording and a recording medium on which an anti-lock control program is recorded.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of a control unit according to an embodiment of the present invention.
FIG. 2 is a diagram showing signal waveforms output from the arithmetic circuit (1) to the arithmetic circuit (2) according to one embodiment of the present invention.
FIG. 3 is a flowchart showing the flow of processing operations in arithmetic circuits (1) and (2) according to an embodiment of the present invention.
FIG. 4 is an overall configuration diagram of one wheel of an antilock control device according to an embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration example of a control unit of an antilock control device in the prior art.
[Explanation of symbols]
20 control unit 21 wheel rotation detection circuit 22 wheel speed pulse output circuit 23 arithmetic circuit (1)
24 arithmetic circuit (2)
25 Control circuit 26 Drive circuit

Claims

In the anti-lock control device having the first wheel speed calculating means for calculating the wheel speed from the rotation of the wheel and the second wheel speed calculating means,
The first wheel speed calculating means outputs a watchdog signal obtained by converting the pulse width in a predetermined manner according to the calculated wheel speed, and the second wheel speed calculating means is configured to calculate the first wheel speed. Based on the watchdog signal input from the means, the normality of the operation of the first wheel speed calculating means is determined, and any of the first wheel speed calculating means and the second wheel speed calculating means is determined. An anti-lock control device characterized by determining the normality of one of the wheel speed calculation functions.

When it is determined that there is an abnormality in the wheel speed calculation function of one of the first wheel speed calculation means and the second wheel speed calculation means, or the operation of the first wheel speed calculation means is abnormal. The antilock control device according to claim 1, wherein when it is determined that there is an antilock, the antilock control is stopped.

First wheel speed calculating means for calculating a wheel speed V1 according to the rotation of the wheel;
Second wheel speed calculating means for calculating a wheel speed V2 according to the rotation of the wheel;
Watchdog signal output means for outputting the wheel speed V1 data obtained by converting the pulse width of the watchdog signal by a predetermined method;
Wheel speed comparing means for comparing the wheel speed V1 obtained by inputting the data of the wheel speed V1 and the wheel speed V2 calculated by the second wheel speed calculating means;
First determination means for determining normality of one of the wheel speed calculation functions of the first wheel speed calculation means and the second wheel speed calculation means based on a result of comparison by the wheel speed comparison means When,
And second determination means for determining normality of operation of the first wheel speed calculation means in accordance with the presence or absence of an output pulse from the watchdog signal output means within a predetermined cycle time. Anti-lock control device.

The second determination means, when the output pulse from the watchdog signal output means within said predetermined period of time has Tsu Naka, determining that there is abnormality in the operation of the first wheel speed calculation means 4. The antilock control device according to claim 3, wherein

Wheel speed pulse output means for outputting a pulse signal according to the rotation of the wheel;
First wheel speed calculating means for calculating a wheel speed V1 based on a pulse signal input from the wheel speed pulse output circuit;
Second wheel speed calculation means for calculating a wheel speed V2 based on a pulse signal input from the wheel speed pulse output circuit;
Watchdog signal output means for outputting the wheel speed V1 data obtained by converting the pulse width of the watchdog signal by a predetermined method;
Wheel speed deriving means for inputting the wheel speed V1 data and deriving the wheel speed V1 by a predetermined conversion method to the input wheel speed V1 data;
Wheel speed comparing means for comparing the wheel speed V1 derived by the wheel speed deriving means with the wheel speed V2 calculated by the second wheel speed calculating means;
First determination means for determining normality of one of the wheel speed calculation functions of the first wheel speed calculation means and the second wheel speed calculation means based on a result of comparison by the wheel speed comparison means When,
A judging means for judging whether or not a pulse is inputted from the watchdog signal output means to the wheel speed deriving means within a predetermined cycle time;
An antilock control device comprising: a second determination unit that determines normality of operation of the first wheel speed calculation unit based on a determination result by the determination unit.

When the difference between the wheel speed V1 and the wheel speed V2 is larger than a predetermined value, the first determination means is the first wheel speed calculation means and the second wheel speed calculation means. The antilock control device according to claim 3, wherein it is determined that there is an abnormality in any one of the wheel speed calculation functions.

The second determination means, when the input of the pulse is determined to Tsu cry from the watchdog signal output means by said determining means, determining that there is an abnormality in the operation of the first wheel speed calculation means The antilock control device according to claim 5.

When it is determined by the first determination means that there is an abnormality in the wheel speed calculation function of one of the first wheel speed calculation means and the second wheel speed calculation means, or the second And a drive signal output means for outputting a drive signal for performing an anti-lock control alarm process when it is determined by the determining means that the operation of the first wheel speed calculating means is abnormal. The antilock control device according to claim 3 or 5.

The predetermined method means that the pulse width indicating the minimum wheel speed and the pulse width indicating the maximum wheel speed are preset in the watch dog signal output means, and the pulse width indicating the minimum wheel speed or the maximum wheel speed is set. 6. The anti-lock control device according to claim 3, wherein the anti-lock control device is converted into a pulse width indicating the wheel speed V1 based on a pulse width indicating.

A first wheel speed calculation procedure for calculating the wheel speed V1 according to the rotation of the wheel;
A second wheel speed calculation procedure for calculating a wheel speed V2 according to the rotation of the wheel;
A watchdog signal output procedure for outputting the wheel speed V1 data obtained by converting the pulse width of the watchdog signal by a predetermined method;
A wheel speed comparison procedure for comparing the wheel speed V1 obtained by inputting the data of the wheel speed V1 and the wheel speed V2 calculated in the second wheel speed calculation procedure;
First determination procedure for determining normality of one of the wheel speed calculation functions of the first wheel speed calculation procedure and the second wheel speed calculation procedure based on the result of comparison by the wheel speed comparison procedure When,
A program for executing a second determination procedure for determining the normality of the operation of the first wheel speed calculation procedure in accordance with the presence or absence of an output pulse from the watchdog signal output procedure within a predetermined cycle time Recorded recording medium.

The second determination step, when the output pulse from the watchdog signal output instructions within said predetermined period of time has Tsu Naka, determining that there is abnormality in the operation of the first wheel speed calculation procedure A recording medium on which the program according to claim 10 is recorded.

Wheel speed pulse output procedure to output with a pulse signal according to the rotation of the wheel,
A first wheel speed calculation procedure for calculating a wheel speed V1 based on a pulse signal input from the wheel speed pulse output circuit;
A second wheel speed calculation procedure for calculating a wheel speed V2 based on a pulse signal input from the wheel speed pulse output circuit;
A watchdog signal output procedure for outputting the wheel speed V1 data obtained by converting the pulse width of the watchdog signal by a predetermined method;
A wheel speed derivation procedure for inputting the wheel speed V1 data and deriving the wheel speed V1 by a predetermined conversion method to the input wheel speed V1 data;
A wheel speed comparison procedure for comparing the wheel speed V1 derived in the wheel speed derivation procedure with the wheel speed V2 calculated in the second wheel speed calculation procedure;
First determination procedure for determining normality of one of the wheel speed calculation functions of the first wheel speed calculation procedure and the second wheel speed calculation procedure based on the result of comparison by the wheel speed comparison procedure When,
A determination procedure for determining whether a pulse is input from the watchdog signal output procedure in the wheel speed derivation procedure within a predetermined cycle time;
A recording medium recording a program for executing a second determination procedure for determining normality of the operation of the first wheel speed calculation procedure based on a determination result by the determination procedure.

In the first determination procedure, when the difference between the wheel speed V1 and the wheel speed V2 is larger than a predetermined value, the first wheel speed calculation procedure and the second wheel speed calculation procedure are performed. The recording medium according to claim 10 or 12, wherein it is determined that there is an abnormality in any one of the wheel speed calculation functions.

The second determination step, when the input pulse from the watchdog signal output procedure in the determination procedure is determined to Tsu Naka, determining that there is an abnormality in the operation of the first wheel speed calculation procedure A recording medium on which the program according to claim 12 is recorded.

When it is determined in the first determination procedure that there is an abnormality in one of the wheel speed calculation functions of the first wheel speed calculation procedure and the second wheel speed calculation procedure, or the second A drive signal output procedure for outputting a drive signal for performing anti-lock control alarm processing when it is determined in the determination procedure that there is an abnormality in the operation of the first wheel speed calculation procedure. A recording medium on which the program according to claim 10 or 12 is recorded.

The predetermined method is that the pulse width indicating the minimum wheel speed and the pulse width indicating the maximum wheel speed are set in advance in the watch dog signal output procedure, and the pulse width indicating the minimum wheel speed or the maximum wheel speed is set. The recording medium according to claim 10 or 12, wherein the recording medium is converted into a pulse width indicating the wheel speed V1 on the basis of a pulse width indicating.