JP3685750B2 - OFDM demodulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an OFDM demodulator for demodulating a signal modulated by the OFDM method used in terrestrial digital broadcasting and the like .
[0002]
[Prior art]
In recent years, an OFDM (Orthogonal Frequency Division Multiplexing) system has been proposed as a system excellent in high-quality transmission and frequency utilization efficiency in a system that transmits video signals or audio signals.
[0003]
The OFDM method is a modulation method in which a large number of subcarriers are set in one channel band. For example, after converting an analog TV signal into a digital signal, data compression is performed by MPEG (Moving Picture Experts Group). Byte interleaving and bit interleaving are performed on this data signal in order to disperse the cause of errors such as noise in the transmission path, and mapping according to modulation schemes such as QPSK (Quadrature Phase Shift Keying) and 16QAM (Quadrature Amplitude Modulation) I do.
[0004]
The mapped data is subjected to time interleaving and frequency interleaving to disperse the cause of errors in the transmission path such as fading, then IFFT (inverse Fourier transform), and after orthogonal modulation, frequency converted to RF frequency. And transmitted.
[0005]
FIG. 1 shows the configuration of a digital television receiver.
[0006]
In the digital television receiver, the TV signal is demodulated by performing the operation completely opposite to that on the transmission side.
[0007]
The RF input input from the antenna is input to the mixer 21. A signal corresponding to the channel selection is also input to the mixer 21 from the local signal generator 22, and a signal whose frequency is converted so that the desired frequency falls within the band of the BPF (band pass filter) 23 is output. The BPF 23 extracts only the desired frequency component.
[0008]
The output of the BPF 23 is input to the mixers 24 and 25, respectively. A cosine signal and a sine signal are input to the mixers 24 and 25 from a 90-degree phase shifter 27 that receives a signal from the local signal generator 26. The mixers 24 and 25 down-convert the output of the BPF 23 having the IF frequency and convert it into a Low IF signal composed of a real axis (I axis) component and an imaginary axis (Q axis) component, and the analog / digital converter 7, 8 is output.
[0009]
The analog / digital converters 7 and 8 convert analog signals (I-axis component and Q-axis component) into digital signals and output them to the FFT circuit 9. The FFT circuit 9 performs fast Fourier transform on the input signal, converts the time axis data into frequency data, and outputs the frequency data to the frequency deinterleave circuit 12.
[0010]
The frequency deinterleave circuit 12 restores the frequency interleave performed to compensate for the loss of the specific frequency signal due to the reflection of radio waves. The output of the frequency deinterleave circuit 12 is sent to the time deinterleave circuit 13. The time deinterleave circuit 13 restores the time interleave performed for anti-fading and the like.
[0011]
The I-axis and Q-axis signals subjected to time deinterleaving are sent to the demapping circuit 14 and converted into 2 bits (QPSK), 4 bits (16QAM), or 6 bits (64QAM). The demapped signal is sent to the bit deinterleave circuit 15. The bit deinterleaving circuit 15 cancels bit interleaving performed for the purpose of increasing error resilience. The output of the bit deinterleave circuit 15 is sent to the Viterbi decoding circuit 16. The Viterbi decoding circuit 16 performs error correction using the convolutional code performed on the transmission side.
[0012]
The signal subjected to Viterbi decoding is sent to the byte deinterleave circuit 17. The byte deinterleaving circuit 17 cancels byte interleaving performed for the purpose of increasing error resilience in the same way as bit interleaving. The output of the byte deinterleave circuit 17 is sent to the RS decoding circuit 18. The RS decoding circuit 18 performs error correction by performing RS (Reed Solomon) decoding. The error-corrected signal is sent to the MPEG decoding circuit 19. The MPEG decoding circuit 19 decompresses the error-corrected signal (compressed signal) and outputs it to the digital / analog conversion 20. The digital / analog converter 20 converts the signal sent from the MPEG decode circuit 19 into an analog video and analog audio signal and outputs the analog video and analog audio signal.
[0013]
In the Japanese terrestrial digital broadcasting system, a segmented signal format is adopted, and in the case of television broadcasting, 13 segments are grouped and transmitted within a 6 MHz band. Further, partial reception in which data broadcasting or the like can be performed with only one segment is possible in one central segment of the 13 segments. In contrast to 13-segment reception, the band is only 1/13 in partial reception, and reception is possible with substantially the same configuration.
[0014]
As the reception method, in the above description, the so-called superheterodyne method in which the IF frequency is once converted and then converted to the Low IF has been described. In a single carrier transmission system such as QPSK modulation, a direct conversion system that directly converts an RF signal into a baseband signal is also used as another reception system. In the direct conversion method, the band-pass filter 23 or the like that is usually realized by a SAW filter is not necessary, and the number of parts can be deleted.
[0015]
FIG. 2 shows the configuration of a direct conversion digital television receiver developed by the present applicant. This direct conversion type digital television receiver differs from the conventional direct conversion type digital television receiver in that an unnecessary component removing circuit is provided, and is not known at the time of filing of the present application.
[0016]
Differences from the superheterodyne digital television receiver of FIG. 1 are as follows.
[0017]
(1) A circuit (mixer 21, local signal generator 22, BPF 23, local signal generator 26, mixers 24, 25, and 90 degree phase shifter 27) for converting an RF signal into an IF signal and further into a low IF signal ) Has been deleted.
[0018]
(2) The addition of a down converter (local signal generator 1, mixer 2, 3, 90-degree phase shifter 4) and LPFs 5, 6 for down-converting the RF signal.
[0019]
(3) The unnecessary component removal circuits 10 and 11 are added.
[0020]
[Problems to be solved by the invention]
In OFDM reception, in addition to directly converting an RF signal into a Low IF signal, a method of frequency-converting the RF signal so that the center frequency of the occupation frequency of the partial reception target segment becomes zero (DC component) is also possible. In this case, since a direct current component (frequency zero component) is also an effective signal component, a signal without a DC offset is required. However, it is not easy to generate a signal having no DC offset due to the DC offset of the down converter or the AD converter.
[0021]
This invention aims to provide an OFDM demodulator that enables highly accurate DC offset correction in a easy single configuration.
[0022]
[Means for Solving the Problems]
O FDM demodulator that by this invention, the down converter for down-converting an analog RF signal modulated by the OFDM method, with respect to the signal obtained by the AD conversion means and the AD converting means for analog / digital conversion of the down-converted signal In the OFDM demodulator including FFT means for performing fast Fourier transform to convert the time axis into the frequency axis, DC offset detection means for detecting a DC offset amount from a DC component after FFT by the FFT means, and DC offset DC offset correcting means for correcting the DC offset based on the DC offset amount detected by the detecting means is provided. The DC offset detecting means has a plurality of reference values and a DC component after FFT by the FFT means. Difference means for calculating and outputting a difference value from each reference value, And a means for selecting and outputting the minimum value among the difference values calculated by the difference means, and an integration means for integrating the difference value output by the comparison means for a certain period and outputting the obtained integral value as an offset amount. It is characterized by having.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, with reference to FIG. 3 to FIG. 7, an embodiment when the present invention is applied to a direct conversion receiver will be described.
[0026]
FIG. 3 shows a configuration of a direct conversion digital television receiver. FIG. 4 shows the spectrum of each part of FIG.
[0027]
In FIG. 3, the same components as those in FIG. Differences between the receiver of FIG. 3 and the conventional example of FIG. 1 are as follows.
[0028]
(1) A circuit (mixer 21, local signal generator 22, BPF 23, local signal generator 26, mixers 24, 25, and 90 degree phase shifter 27) for converting an RF signal into an IF signal and further into a low IF signal ) Has been deleted.
(2) Downconverter (local signal generator 1, mixer 2, 3, 90-degree phase shifter 4) that converts the frequency of the RF signal so that the center frequency of the occupied frequency of the partial reception target segment becomes zero (DC component) ) And LPF5, 6 were added.
(3) The unnecessary component removal circuits 10 and 11 are added.
(4) The DC offset correction circuits 101 to 102 and the DC offset detection circuit 103 are added.
[0029]
In terrestrial digital broadcasting, the signal is transmitted with a spectrum as shown in FIG. In FIG. 4A, the spectrum for UHF channels 14 to 16 is shown. One channel is 6 HMz, and one channel is composed of 13 segments. Of these, the central segment is a signal for partial reception. The case where the UHF 15 is partially received will be described.
[0030]
FIG. 4B is an enlarged view of the UHF 15, in which the partial reception target segment is S15-0, and the preceding and succeeding segments are S15-1 to S15-12, of which S15-0 to S15-6 are illustrated.
[0031]
The RF signal of the UHF 15 is frequency-converted by the down converter (local signal generator 1, 90 degree phase shifter 4 and mixers 2, 3) shown in FIG. The local signal generator 1 outputs a signal having a frequency for frequency conversion of the RF signal so that the center frequency of the occupied frequency of the partial reception target segment S15-0 becomes zero. Further, the 90-degree phase shifter 4 outputs a cosine signal and a sine signal to the mixers 2 and 3 in order to output real axis and imaginary axis components.
[0032]
The spectrum after frequency conversion by the down converter is as shown in FIG. Since the down converter frequency-converts the RF signal so that the center frequency of the occupied frequency of the partial reception target segment S15-0 is zero (DC component), the half frequency of the occupied frequency of the partial reception target segment S15-0 is Folding occurs, and the folded signals are multiplexed.
[0033]
Harmonic components are removed from this signal by LPFs 5 and 6. The output spectrum after the harmonic component removal by the LPFs 5 and 6 is as shown in FIG. Since the LPFs 5 and 6 use analog filters having relatively gentle characteristics, the spectrum of the output signal after the harmonic component removal by the LPFs 5 and 6 is adjacent to the segment other than the partial reception target segment S15-0. Segments S15-1 and S15-2 also remain.
[0034]
For this signal, FFT 9 converts the time axis data into frequency axis data. The output spectrum of the FFT 9 is as shown in FIG.
[0035]
The unnecessary component removal circuits 10 and 11 remove the output of the FFT 9 from the segments S15-1 and S15-2 which are unnecessary components other than the partial reception target segment S15-0, and output them to the frequency deinterleave circuit 12. Therefore, the spectrum of the output signals of the unnecessary component removal circuits 10 and 11 is only the partial reception target segment S15-0 as shown in FIG. The signal processing after the frequency deinterleave circuit 12 is the same as that of the receiver of FIG.
[0036]
For reference, the principle by which the signal component of the partial reception target segment S15-0 can be separated by the FFT circuit 9 will be described.
[0037]
For simplicity, assuming that the center frequency of the segment S15-0, which is a partial receiver, is wc, and there is one carrier at a portion that is ± α away from wc vertically, the signal S0 of the segment S15-0 is It is represented by Formula (1).
[0038]
S0 = A * cos ((wc + α) t) + B * sin ((wc-α) t)) (1)
[0039]
Here, A to B are signal amplitudes.
[0040]
To convert the center of the RF signal of each of the real axis and imaginary axis to DC, this signal is multiplied by cos (wct) and sin (wct), and then the harmonic component is removed (coefficient is omitted in 1/2) ), The real axis component I is represented by the following formula (2), and the imaginary axis component Q is represented by the following formula (3).
[0041]
I = A * cos (αt) + B * sin (-αt) (2)
Q = A * sin (-αt) + B * cos (αt)… (3)
[0042]
In order to perform FFT on this signal, multiply this signal by cos (-αt) -jsin (-αt) and integrate for one period to obtain A, and also multiply cos (αt)-jsin (αt) for one period. Since B is obtained by integration, the positive frequency component and the negative frequency component can be completely separated.
[0043]
Incidentally, as in the spectrum shown in FIG. 4C, since the DC component (the component with zero frequency) is also a signal component, a signal having no DC offset is required. As causes of the DC offset, when the mixers 2 and 3 and the LPFs 5 and 6 are active filters, there are DC offsets of active elements, analog / digital conversion circuits 7 and 8, and the like.
[0044]
In the receiver of FIG. 3, the output after the FFT in the FFT circuit 9 is input to the DC offset detection circuit 103, and the output of the DC offset detection circuit 103 is input to the DC offset correction circuits 101 and 102. The DC offset correction circuits 101 and 102 correct the value at the time of DC output of the FFT circuit 9 according to the DC offset amount of the DC offset detection circuit 103.
[0045]
FIG. 5 shows the configuration of the DC offset detection circuit 103.
[0046]
Usually, data becomes a signal close to random data by transmission signal processing. For this reason, when the signal component is integrated for a certain period, it becomes a constant value. Using this property, the DC offset detection circuit 103 integrates the DC component of the output of the FFT circuit 9 for a certain period, and uses the integration result as the DC offset amount.
[0047]
The DC offset detection circuit 103 in FIG. 5 includes a first circuit (DC position detection circuit 201 and an integrator 202) for giving an offset amount to one DC offset correction circuit 101, and the other DC offset correction circuit 102. A second circuit (DC position detection circuit 301 and integrator 302) for providing an offset amount is provided.
[0048]
Since the operation of both circuits is the same, only the operation of the first circuit will be described. The DC position detection circuit 201 receives one signal output from the FFT circuit 9 and detects the level of the DC position. The integrator 202 integrates the level of the DC position detected by the DC position detection circuit 201 for a certain period, and outputs the integration result as an offset amount.
[0049]
FIG. 6 shows another configuration example of the DC offset detection circuit 103.
[0050]
When the signal component takes a value of +1 or -1, the output of the FFT circuit 9 becomes + 1 + α or -1 + α if the DC offset value is α.
[0051]
For example, when the output is + 1 + α, when this value is ± 1, 2 + α and α are obtained. The value close to 0, that is, α is the DC offset amount. Similarly, when the output is −1 + α, when this value is set to ± 1, α and −2 + α are obtained. The value close to 0, that is, α is the DC offset amount. In this way, the assumed signal value is subtracted from the output of the FFT circuit 9, and the value close to 0 is set as the DC offset amount.
[0052]
The DC offset detection circuit 103 in FIG. 6 is a first circuit (a DC position detection circuit 401, a first difference circuit 402, a second difference circuit 403, a comparison circuit) for giving an offset amount to one DC offset correction circuit 101. 404 and integrator 405) and a second circuit (DC position detection circuit 501, first difference circuit 502, second difference circuit 503, comparison circuit 504, and the like) for providing an offset amount to the other DC offset correction circuit 102. Integrator 505).
[0053]
Since the operation of both circuits is the same, only the operation of the first circuit will be described. The DC position detection circuit 401 receives one signal output from the FFT circuit 9 and detects the level of the DC position. The output X of the DC position detection circuit 401 is + 1 + α or −1 + α.
[0054]
The first difference circuit 402 subtracts −1 (adds +1) from the output X of the DC position detection circuit 401. The output value of the first difference circuit 402 is X + 1. The second difference circuit 403 subtracts +1 from the output X of the DC position detection circuit 401. The output value of the second difference circuit 403 is X-1.
[0055]
The comparison circuit 404 compares the output value (X + 1) of the first difference circuit 402 with the output value (X-1) of the second difference circuit 403, and selects and outputs the smaller output value α. The integrator 405 integrates the output of the comparison circuit 404 for a certain period and outputs the integration result as an offset amount.
[0056]
In the above embodiment, the DC offset correction circuits 101 and 102 are provided in the subsequent stage of the FFT circuit 9, but the DC offset correction circuits 101 and 102 are provided in the previous stage of the FFT circuit 9 as shown in FIG. Also good. In the case where the DC offset correction circuits 101 and 102 are provided in the previous stage of the FFT circuit 9, since the correction is performed before the FFT conversion, the dynamic range of the FFT can be fully utilized. There is a delay.
[0057]
【The invention's effect】
According to the present invention, accurate DC offset correction can be performed with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a conventional digital television receiver.
FIG. 2 is a block diagram showing a configuration of a direct conversion digital television receiver developed by the present applicant.
FIG. 3 is a block diagram showing a configuration of a digital television receiver according to the embodiment of the present invention.
4 is a schematic diagram showing a spectrum of each part in FIG. 3; FIG.
5 is a block diagram showing a configuration of a DC offset detection circuit 103. FIG.
6 is a block diagram showing another configuration of the DC offset detection circuit 103. FIG.
FIG. 7 is a block diagram showing another configuration of the digital television receiver.
[Explanation of symbols]
1 Local signal generator 2, 3 Mixer 4 90 degree phase shifter 5, 6 LPF
9 FFT circuit 10, 11 Unnecessary component removal circuit 101, 102 DC offset correction circuit 103 DC offset detection circuit

Claims (1)

A down converter for down-converting an analog RF signal modulated by the OFDM method, an AD conversion means for analog / digital conversion of the down-converted signal, and a signal obtained by the AD conversion means are subjected to fast Fourier transform to obtain a time axis In an OFDM demodulator comprising FFT means for converting the frequency into the frequency axis,
DC offset detection means for detecting the DC offset amount from the DC component after FFT by the FFT means, and DC offset correction means for correcting the DC offset based on the DC offset amount detected by the DC offset detection means,
The DC offset detecting means has a plurality of reference values and calculates and outputs a difference value between the DC component after FFT by the FFT means and each reference value, and among the difference values calculated by the difference means Means for selecting and outputting the minimum value of the signal, and an OFDM demodulator comprising an integration means for integrating the difference value output by the comparison means for a certain period and outputting the obtained integrated value as an offset amount Machine.

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