JP3678968B2 - Circuit board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit board used in a circuit configuration including a resonance circuit such as a voltage controlled oscillator and a power module.
[0002]
[Prior art]
In an electronic / communication device that operates at a high frequency such as a mobile phone, an oscillator or a filter using a resonance circuit is used. In such a circuit board, a conductor film having an inductance component such as a strip line, a microstrip line, or an inductance element is formed on a single-plate or laminated dielectric substrate. As a result, the circuit board is highly integrated.
[0003]
FIG. 4 is an exploded perspective view of a circuit board including a conventional resonance circuit. As the resonant circuit substrate, a laminated substrate 51 composed of three ceramic dielectric layers 51a, 51b and 51c is used. The multilayer substrate 51 is formed with various conductor patterns 54 and 58 and a wiring pattern 53 that constitute a part of the resonance circuit, and circuit elements such as transistors, resistors, and capacitors that constitute a predetermined circuit on the surface. 52 is arranged. Thus, an oscillation circuit or a filter circuit having a resonance circuit is configured.
[0004]
In the figure, conductor patterns 54 (54a, 54b), 58 constituting a part of the resonance circuit are connected via, for example, two via-hole conductors 56a, 56b extending in the thickness direction of the dielectric layer 51a. Specifically, one conductor pattern 54a (first conductor pattern) formed on the surface of the multilayer substrate 51 is connected to an upper connection portion that is one end on the upper side of the first via-hole conductor 56a. The lower connection portion, which is one lower end of one via-hole conductor 56a, is connected to one end portion of the third conductor pattern 58 disposed between the dielectric layers 51a and 51b (the lower surface side of the dielectric layer 1a). ing. Further, the other end of the third conductor pattern 58 is connected to a lower connection portion which is one end on the lower side of the second via hole conductor 56b, and an upper connection portion which is one end on the upper side of the second via hole conductor 56a is The conductor pattern 54 (second conductor pattern) is connected.
[0005]
Such a resonant circuit board 51 has through holes formed as via-hole conductors 56a and 56b in a large green sheet formed from a dielectric ceramic slurry, and each through hole is filled with a conductive paste, and a large-sized green sheet is formed. A conductor paste made of silver or the like is screen-printed on the green sheet to form conductor films to be the predetermined conductor patterns 54 and 58 and the wiring pattern 53, and then a large green sheet is laminated. Thereafter, the substrate is baked under predetermined conditions, and the obtained multi-chip mother board is divided into individual resonant circuit boards. The resonant circuit board thus obtained had various electronic component elements 52 mounted on the surface thereof.
[0006]
Such a substrate material may be not only ceramic but also a composite material substrate made of glass epoxy resin. A similar substrate can be obtained by pasting a copper foil on an epoxy prepreg sheet, laminating an etched electrode pattern, and thermocompression bonding.
[0007]
In such a resonant circuit board, the first conductor pattern 54a, the first via-hole conductor 56a, the third conductor pattern 58, the second via-hole conductor 56b, and the second conductor pattern 54b form a series and have a predetermined length. Conductor film (for example, a strip line) having a predetermined inductance component. Thus, desired electrical characteristics are obtained with a predetermined resonance circuit. The oscillation or filter circuit needs to be electrically resonated at a specific frequency, but the resonance frequency is determined by the electrical length L of the stripline, which is approximately equivalent to its physical length. By controlling the physical length of the stripline, the circuit can be operated at a desired resonance frequency.
[0008]
Forming the conductor film to be the stripline on the upper surface of the substrate usually leads to an increase in the size of the circuit board and is not a possible measure. For this reason, a part or all of the strip line is formed as an inner layer with the substrate structure being a laminated substrate. As a result, the resonance circuit board can be greatly reduced in size.
[0009]
[Problems to be solved by the invention]
However, in the circuit board having the above-described structure, the electrical characteristics are greatly influenced by the manufacturing process of the laminated board, particularly, the accuracy during lamination. That is, the connection point at the end of the first conductor pattern 54a and the connection point at one end of the third conductor pattern 58 are connected to the connection point at the other end of the third conductor pattern 58 and the second connection point. The connection point at the end of the conductor pattern 54b does not necessarily match, and the centers of the first and second via-hole conductors 56a and 56b for connection do not exactly match.
[0010]
As a result, even if the via-hole conductor and each conductor pattern are electrically connected due to the misalignment in the laminating process of the dielectric layer 51a and the dielectric layer 51b, the misalignment is caused by a physical misalignment amount ΔL. Suppose that At this time, a deviation amount ΔL occurs between the two via-hole conductors, and the electrical length increases or decreases by 2 × ΔL as a whole.
[0011]
Normally, when a large number of laminated substrates are taken from the mother substrate, the deviation amount ΔL usually takes various values depending on where the region to be the laminated substrate is located.
[0012]
In this way, variations in the overall electrical length of the conductor film having an inductance component occur due to stacking misalignment, conductor pattern printing misalignment, via hole position misalignment, shrinkage variation in the mother board, and the like, resulting in desired resonance characteristics. No resonance circuit can be obtained.
[0013]
As such a countermeasure, an electrode pattern for adjusting resonance characteristics is usually applied to a conductor pattern having an inductance component, and the electrode pattern is trimmed. That is, such a configuration leads to an increase in processing man-hours.
[0014]
The present invention has been devised in view of the problems of the art, and its purpose is that the resonance characteristics do not fluctuate even if misalignment occurs during manufacturing, and the size can be reduced. Is to provide a simple circuit board.
[0015]
The circuit board according to the present invention includes a first conductor pattern connected to the first via hole conductor and the second via hole conductor on an upper surface side of the dielectric layer on which the first via hole conductor and the second via hole conductor are formed. And a second conductor pattern to be connected to each other, and a third conductor pattern having both ends connected to the first and second via-hole conductors on the lower surface side of the dielectric layer. The third conductor pattern is formed in a strip shape so as to be connected only to the first and second via hole conductors on the lower surface side of the dielectric layer, and both ends of the third conductor pattern. The lead portions in the vicinity of the circular land provided in the lead are led out in parallel and opposite directions.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Below, the circuit board of this invention is demonstrated based on drawing.
FIG. 1 is a partially exploded perspective view of a circuit board provided with a resonance circuit of the present invention, and this will be described as a resonance circuit board hereinafter.
[0017]
In FIG. 1, 1 is a dielectric substrate, 2a to 2d are various electronic components, 3 is a wiring pattern, 4 (4a and 4b) is a conductor pattern on the upper surface side, 6a and 6b are via-hole conductors, and 8 is a conductor on the lower surface side. It is a pattern.
[0018]
The dielectric substrate 1 has, for example, a laminated structure of three dielectric layers 1a to 1c. A conductive film (microstrip, stripline, inductance conductive film) having an inductance component that constitutes a part of the resonance circuit is formed on the substrate. Various electronic components 2 a to 2 d are connected to the wiring pattern 3 on the surface of the substrate 1.
[0019]
The conductor film having a predetermined inductance component constituting a part of the resonance circuit is formed on the upper surface side and the lower surface side of the dielectric layer 1a constituting the dielectric substrate 1 (bonding surfaces of the dielectric layer 1a and the dielectric layer 1b). ). That is, the dielectric layer 1a includes the first conductor pattern film 4a, the second conductor pattern 4b, the third conductor pattern 8, and the via-hole conductors 6a and 6b connecting them. Note that the first conductor pattern and the second conductor patterns 4a and 4b have a short conductor length in this example, and therefore are completely separated from the lead portions in connection with both end portions of the via-hole conductors 6a and 6b. Since it cannot be used, it is also used as a symbol.
[0020]
Specifically, on the upper surface of the dielectric layer 1, the first conductor pattern 4a extends from the predetermined wiring pattern 3, and a circular land 5a is formed at one end. The second wiring pattern 4b also extends from the predetermined wiring pattern 3, and a circular land 5b is formed at one end.
[0021]
Further, on the lower surface side of the dielectric layer 1 (in the figure, the upper surface of the dielectric layer 1b), the third conductor pattern 8 formed so as to circulate is a strip-like shape connected only to the via-hole conductors 6a and 6b. The circular lands 7a and 7b are provided at both ends, and in the vicinity of the circular lands 7a and 7b, parallel and opposite directions, that is, parallel to each other and extending directions are provided. Lead portions 8a and 8b which are opposite to each other are provided.
[0022]
The dielectric layer 1a is formed with a first via hole conductor 6a and a second via hole conductor 6b extending in the thickness direction.
[0023]
When the dielectric layer 1a and the dielectric layer 1b are laminated, the first conductor pattern 4a on the dielectric layer 1a is connected to the upper end (upper side connection portion) of the first via-hole conductor 6a via the land 5a. Connected to. The lower end (lower connection portion) of the first via hole conductor 6 a is connected to the land 7 a at one end of the third conductor pattern 8. The land 7b at the other end of the third conductor pattern 8 is connected to the lower end (lower side connecting portion) of the second via-hole conductor 6b. Further, the (upper end) upper side connection portion of the second via hole 6b is connected to the land 5b at the end portion of the second conductor pattern 4b.
[0024]
That is, the first conductor pattern 4a, the first via hole conductor 6a, the third conductor pattern 8, the second via hole conductor 6b, the second conductor pattern 4b are connected to each other, and a conductor film having a predetermined inductance component, for example, It constitutes the stripline.
[0025]
Below, the concrete dimension of each conductor pattern 4a, 4b, 8 etc. is shown. The first conductor pattern 4a and the second conductor pattern 4b connected to the wiring pattern 3 formed on the surface of the dielectric substrate 1 have a conductor width of 0.3 to 0.5 mm, and the circular land 5a at the end thereof. 5b has a diameter of 0.7 mm.
[0026]
The third conductor pattern 8 formed on the lower surface side of the dielectric layer 1a has a conductor width of 0.3 to 0.5 mm, and the circular lands 7a and 7b at both ends thereof have a diameter of 0.9 mm. .
[0027]
The via hole conductors 6a and 6b connecting the lands 5a and 7a and 5b and 7b have a diameter of 0.3 mm.
[0028]
When there is no positional deviation (lamination deviation, printing deviation) between the dielectric layers 1a and 1b, the centers of the lands 5a, 5b, 7a, and 7b are positioned at the centers of the via-hole conductors 6a and 6b. . The lands 7a and 7b at both ends of the third conductor pattern 8 are formed to be 0.2 mm larger in diameter than the lands 5a of the first conductor pattern 4a and the lands 5b of the second conductor pattern 4b. This is because an alignment accuracy of 0.1 mm at the time of stacking is considered.
[0029]
The difference between the conductor film having the inductance component of the resonant circuit board shown in FIG. 1 and the conventional conductor film having the inductance component of the resonant circuit board shown in FIG. 4 is that both ends of the second conductor pattern 8 are different as described above. This is the direction in which the lead portions 8a and 8b are pulled out. That is, although the lead directions (extending directions) of both the lead portions 8a and 8b are parallel to each other, when viewed from the lower connection portions (lands 7a and 7b) of the via-hole conductors 6a and 6b, the lead portions 8a and 8b. The extending directions are opposite to each other. In short, the lead portion 8a from the land 7a and the lead portion 8b from the land 7b are 180 degrees out of the lead.
[0030]
When viewed from a total of four connecting portions of the two via-hole conductors 6a and 6b, the extending direction of the first conductor pattern 4a from the upper connecting portion of the first via-hole conductor 6a (the direction toward the upper right in FIG. 1) ), The extending direction of the lead portion 8a of the third conductor pattern 8 from the lower connecting portion of the first via-hole conductor 6a (the direction toward the upper right in FIG. 1), and the lower connecting portion of the second via-hole conductor 6b. Direction of the lead portion 8a of the third conductor pattern 8 (the direction toward the lower left in FIG. 1), the extension direction of the second conductor pattern 4b from the upper connection portion of the second via-hole conductor 6b (upper portion in FIG. 1, Each of the four extending directions is parallel to each other. The extension direction is one extension direction, that is, only the extension direction of the lead portion 8a of the third conductor pattern 8 from the lower connection portion of the second via-hole conductor 6b is different from the other extension directions. Is reversed.
[0031]
Like the third conductor pattern 8, by reversing the extending directions of the leads 8a and 8b at the ends, for example, when the dielectric layer 1a and the dielectric layer 1b are laminated, Further, when the third conductor pattern 8 is printed, it can be prevented from being affected by the deviation of the electrical length caused by the displacement.
[0032]
This situation can be explained using FIG.
[0033]
2A to 2C show the second via-hole conductor 6b side in FIG. 1, and the third conductor pattern 4b extends from the land 5b connected to the upper connection portion of the second via-hole conductor 6b to the back of the page. The end portion of the third conductor pattern 8 extends in front of the paper surface from the land 7b extending in the direction and connected to the lower connection portion of the via-hole conductor 6b.
[0034]
2D to 2F show the first via-hole conductor 6a side in FIG. 1, and the first conductor pattern 4a extends from the land 5a connected to the upper connection portion of the first via-hole conductor 6a to the back of the drawing. The end of the third conductor pattern 8 extends in front of the paper surface from the land 7a that extends in the direction and connects to the lower connection portion of the via-hole conductor 6a.
[0035]
FIGS. 2A and 2D show the case where they are stacked at a normal position. On the other hand, FIGS. 2B and 2E show a state in which the via-hole conductors 6a and 6b are displaced from the centers of the lands 7a and 7b in the depth direction of the drawing. 2C and 2F show a state in which the via-hole conductors 6a and 6b are displaced from the centers of the lands 7a and 7b toward the front side of the drawing.
[0036]
2B and 2E, on the second via hole conductor 6b side in FIG. 2B, the electrical length L of the conductor film of the inductance component is extended by ΔL according to the positional deviation amount ΔL. (+ ΔL). On the other hand, on the first via-hole conductor 6a side in FIG. 2E, the electrical length L of the conductor film of the inductance component is shortened by ΔL (−ΔL) according to the positional deviation amount ΔL.
[0037]
2C and 2F, on the second via-hole conductor 6b side in FIG. 2C, the electrical length L of the conductor film of the inductance component is shortened by ΔL according to the positional deviation amount ΔL. (−ΔL). On the other hand, on the first via-hole conductor 6a side in FIG. 2 (f), the electrical length L of the conductor film of the inductance component increases by ΔL according to the positional deviation amount ΔL (+ ΔL).
[0038]
In the present invention, the lead portions 8a and 8b at both ends of the third conductor pattern 8 are set so as to extend in opposite directions to each other. When the lead portions 8a and 8b are in the same direction, a combination of the state of FIG. 2 (b) and the state of FIG. 2 (e), or the state of FIG. 2 (c) and the state of FIG. 2 (f). One of the combinations.
[0039]
In such a combination, the deviation of the electrical length is a combination of ΔL and −ΔL, which cancel each other and the electrical length does not change.
[0040]
That is, it is not affected by the stacking error.
[0041]
2 (g) to 2 (i), taking the second via-hole conductor 6 b side as an example, consider the effect when the stacking misalignment or printing misalignment direction occurs in the lateral direction perpendicular to the above-described direction.
[0042]
FIG. 2 (g) shows a normal connection state. In the figure, the dotted line indicates the shortest distance of the signal path.
[0043]
If the second conductor pattern 4b is shifted to the left side as shown in FIG. 2 (h), or the second conductor pattern 4b is shifted to the right side as shown in FIG. The shortest distance of the path does not substantially change, and the electrical length is hardly affected.
[0044]
2 (h) and 2 (i) illustrate the second conductor pattern 4b connected to the upper connection portion of the via-hole conductor 6b as an example, but the lower connection portion of the via-hole conductor 6a is relatively described. The same applies to the shift in the left-right direction of the third conductor pattern 8 to be connected. The same applies to the first via-hole conductor 6a side.
[0045]
The actual deviation occurs in any direction. However, if the deviation is decomposed in the front-rear direction and the lateral direction, the electrical length is not affected by the electrical length in both the front-rear direction and the lateral direction. It can be seen that no fluctuation occurs.
[0046]
As described above, in the resonant circuit board of the present invention, in the conductor film having the inductance component having the two via-hole conductors 6a and 6b, the conductor patterns 4a, 4b, and 8 are extended from the two via-hole conductors 6a and 6b. Since the direction is controlled, even if the stacking deviation in the extending direction of the dielectric layers 1a and 1b and the positional deviation of the conductor patterns 4a, 4b, or 8 with respect to the via-hole conductors 6a and 6b occur, the electrical length is substantially reduced. Fluctuations are offset on the two via-hole conductors 6a and 6b sides, and a resonant circuit board having stable resonance characteristics without fluctuations in electrical length can be obtained.
[0047]
In addition, since the conductor film having an inductance component is formed separately on the upper surface side and the lower surface side of the dielectric layer 1a, the density of the conductor film can be increased, thereby enabling miniaturization.
[0048]
Further, the trimming pattern conventionally formed on the conductor film having the necessary inductance component is unnecessary or small.
[0049]
Further, it is possible to obtain an inexpensive substrate that can be easily managed when the substrates are stacked, does not require adjustment work, and does not require processing costs.
[0050]
FIG. 3 shows another embodiment of the present invention. It is a modification of the 3rd conductor pattern 8 shown in FIG. That is, the third conductor pattern 8 shown in FIG. 1 is patterned so as to surround the land 7a at one end, but in this embodiment, a pattern that crosses the two lands at both ends, for example, A substantially S-shaped conductor pattern 18 is formed.
[0051]
Accordingly, in the lower connection portion of the first via hole conductor 6a, the lead portion 18a extends to the upper side of the paper surface, and in the lower connection portion of the second via hole conductor 6b, the lead portion 18b extends to the lower side of the paper surface. Yes.
[0052]
In the upper connection portion of the first via hole conductor 6a, the first conductor pattern 4a extends to the upper side of the paper surface, and in the upper connection portion of the second via hole conductor 6b, the second conductor pattern 4b is formed on the paper surface. It extends upward.
[0054]
Also in FIG. 3, as described with reference to FIG. 2, in the two via-hole conductors 6a and 6b, fluctuations in the electrical length between the conductor patterns at one connection portion of the two via-hole conductors cancel each other. Become. Thereby, stable resonance characteristics can be maintained.
[0056]
In the above embodiment, only the strip line has been described as the conductor film having an inductance component. For example, a conductor film having a ground potential is formed between the dielectric layers 1b and 1c and used as a microstrip line. The resonance circuit may be configured in a distributed constant manner.
[0057]
Further, only one dielectric layer, that is, a dielectric substrate on a single plate, a first conductor pattern and a second conductor pattern are formed on the surface of the substrate, and a third conductor pattern is formed on the back surface of the substrate. It doesn't matter.
[0058]
【The invention's effect】
According to the present invention, even when the stacking position shift occurs during the formation of the circuit board, the variation in the electrical length caused by the shift can be canceled out on the first and second via hole conductor sides. Thereby, the electrical length L when viewed from the network side is not affected. When this circuit board is a resonant circuit board, variations in resonance characteristics such as a resonance frequency can be effectively suppressed.
[0059]
In addition, a trimming pattern is unnecessary or small, and a conductor film having an inductance component can be formed in the thickness direction, so that a small circuit board is obtained.
[0060]
Further, management at the time of substrate lamination is easy, adjustment work is removed or reduced, and an inexpensive substrate that does not require processing costs can be obtained.
[Brief description of the drawings]
FIG. 1 is a partially exploded perspective view showing an embodiment of a circuit board according to the present invention.
FIGS. 2A to 2I are schematic views showing a variation state of an electrical length when a positional deviation occurs.
FIG. 3 is a partially exploded perspective view showing another embodiment of the circuit board of the present invention.
FIG. 4 is a partially exploded perspective view showing a conventional circuit board.
[Explanation of symbols]
1 .. Dielectric substrate 1a, 1b, 1c .. Dielectric layer 2, 2a, 2b, 2c, 2d .. Electronic component 3 .. Wiring pattern 4a, 14a, 34a .. First conductor pattern 4b, 14b, 34b ... Second conductor pattern 5a, 5b ... Land 6a ... First via hole conductor 6b ... Second via hole conductor 7a, 7b ... Land 8, 18, 38 ... Third conductor pattern

Claims (1)

A first conductor pattern connected to the first via hole conductor and a second conductor connected to the second via hole conductor on the upper surface side of the dielectric layer on which the first via hole conductor and the second via hole conductor are formed. In the circuit board, in which each pattern is disposed, and a third conductor pattern having both ends connected to the first and second via-hole conductors is disposed on the lower surface side of the dielectric layer.
The third conductor pattern is formed in a strip shape so as to be connected only to the first and second via-hole conductors on the lower surface side of the dielectric layer, and at both ends of the third conductor pattern. A circuit board , wherein lead portions in the vicinity of provided circular lands are led out in parallel and opposite directions .

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