JP3677422B2 - Integrated circuit and design method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit and a design method thereof, and more particularly to a method of designing an integrated circuit using a scanning technique and an integrated circuit designed using the method.
[0002]
[Prior art]
In recent years, a desired circuit is realized by performing logic synthesis / automatic placement and routing using a standard cell (hereinafter referred to as SC). This is because an SC having a certain function is registered in advance in a library, a desired circuit whose specification is determined and its logic configuration is described in a function description language is synthesized by combining a plurality of SCs, and a netlist. And a circuit pattern is realized by performing automatic placement and routing using this list.
[0003]
Since this method can automatically generate a function described in a function description language up to a circuit pattern, it is effective in shortening the design period and improving the degree of design freedom. Therefore, the logic synthesis / automatic placement and routing technique using SC is not limited to ASIC (Application Specific IC), but is also partially applied to microprocessors that require high-performance custom design.
[0004]
In addition, this method can automatically generate test patterns at the time of product shipment using ATPG (Auto Test Pattern Generator) by applying a scan method for ease of testing, realizing a high failure detection rate. can do.
[0005]
Here, the scanning method is roughly divided into a sequential circuit composed of flip-flops (hereinafter referred to as F / F) and a combinational circuit composed of logic circuits not including F / F, and the F / Fs are connected in series. In this method, a desired value is input from the outside, propagated to a combinational circuit and operated, and operation results are sequentially extracted from the shift register and inspected. The logic circuit sandwiched between the scan F / Fs can be cut out as a circuit having a small scale as a circuit to be inspected. Therefore, it is possible to easily analyze combinations of inputs that can be detected using the ATPG.
[0006]
However, in a circuit having a specific fixed function, such as a memory or a high-speed arithmetic unit, it is not realized by a combination of SCs. A technique for achieving high-speed operation is used. Such circuits are often designed in advance as MB (Macro Block) or purchased from other companies as IP (Intellectual Property).
[0007]
Such MB or IP is not used alone as a device, but is used in a state in which a circuit according to the application is arranged and combined around it. However, what kind of circuit is arranged around the MB or IP is unknown at the time of design. In view of this, design for facilitating tests such as scan F / F and BIST (Build-In Self Test) is usually performed in the circuit so that failure detection is possible with MB or IP alone.
[0008]
Therefore, a circuit for which logic synthesis / automatic placement and routing is performed using SC can be easily tested by a scanning method, and testing can be facilitated for MB or IP alone because a testing method has been established. .
[0009]
[Problems to be solved by the invention]
However, the conventional apparatus combining the circuit synthesized by SC and MB or IP has the following problems.
[0010]
As shown in FIG. 6, an SC block SCB2 combining SCs and a custom block CB2 made of MB or IP are arranged. In the SC block SCB2, the F / F is scan-connected, and desired data input setting and test result output can be performed from a scan input terminal SIT provided outside the apparatus. The test in the custom block CB2 can be performed according to a technique established at the time of design.
[0011]
However, by combining with the custom block CB2, the SC block SCB2 includes an area AR2 where failure detection is possible by scan design and an area AR3 where this is not possible. This area AR3 corresponds to a boundary area between the custom block CB2 and the SC block SCB2, and it is impossible to detect a failure because it is impossible to trace input control and output observation by scanning.
[0012]
As shown in FIG. 6, a method of performing scan design using the F / F included in the custom block CB2 is also conceivable. However, when such a design is performed, the area of the custom block CB2 increases and the operating frequency tends to decrease. For this reason, the significance of using the custom block CB2 is lost.
[0013]
In view of the above circumstances, the present invention is an integrated circuit capable of facilitating a test of a boundary region between blocks when an SC block capable of using a scanning method and a custom block made of MB or IP are combined. It is an object of the present invention to provide an integrated circuit designed by using this design method and this method.
[0015]
[Means for Solving the Problems]
The integrated circuit design method of the present invention is an integrated circuit that receives an input operand and an input opcode in a normal operation mode, performs a predetermined process specified by the input opcode, and outputs at least one of the output operand and the output opcode. An integrated circuit design method that applies a scanning technique to a circuit,
When the scan mode is set, regardless of the predetermined process specified by the input opcode, a process that is fixed in advance and simpler than the predetermined process is performed on the input operand.
A result obtained by performing the processing is output as at least one of the output operand and the output opcode.
[0017]
The integrated circuit of the present invention is an integrated circuit that receives an input operand and an input opcode in a normal operation mode, performs a predetermined process specified by the input opcode, and outputs at least one of the output operand and the output opcode. An integrated circuit to which a scanning technique is applied,
In addition to the means for performing the predetermined processing, the integrated circuit includes:
Scan mode setting means for setting the scan mode;
Processing means for performing processing that is fixed in advance and simpler than the predetermined processing on the input operand regardless of the predetermined processing specified by the input opcode when the scan mode is set by the scan mode setting means; ,
And a means for outputting the result obtained by the processing by the processing means as at least one of the output operand and the output opcode.
[0018]
Here, the integrated circuit may be an arithmetic unit. In this case, the scan mode setting means is a scan mode setting signal input terminal to which a scan mode setting signal is input, and the processing means is the scan mode. When a setting signal is input, the fixed processing is performed on the input operand, and the output means outputs the result processed by the processing means as at least one of the output operand and the output opcode. You may do.
[0019]
Alternatively, the integrated circuit may be a writable and readable memory. In this case, in normal operation, the input operand is write data, and the input opcode is an address and a control for designating writing or reading. The output operand is read data, the scan mode setting means is a scan mode setting signal input terminal to which a scan mode setting signal is input, and the processing means is input with the scan mode setting signal. Then, based on the control signal, either the input operand or the input operand is selected and bypassed, and the output means outputs the output operand that has been bypassed by the processing means. It may be a thing.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0021]
The present embodiment is applied to a design method for facilitating a test in an integrated circuit combining an SC block for which scan design has been performed and a custom block made of IP or MB, and an integrated circuit designed by this method. FIG. 1 shows the configuration of an integrated circuit.
[0022]
As a design method, a scan mode setting signal input terminal for switching from the normal operation mode to the scan mode is newly provided in the custom block CB1. When a scan mode setting signal is input to this terminal, a bypass path is added to the custom block CB1 for outputting the signal input to the custom block CB1 by performing a logical operation simpler than the normal operation.
[0023]
Thus, the custom block CB1 is replaced with a functional block having a simple logical configuration in the scan mode. Therefore, when the test pattern is automatically generated for the SC block SCB1 using ATPG, the custom block CB1 and the SC block SCB1 can be performed together. As a result, it is possible to detect a failure in the boundary area between the blocks (area AR3 in FIG. 6), which conventionally cannot be detected by scanning, and to improve the failure detection rate of the entire circuit.
[0024]
Here, as an example of the configuration that operates in the scan mode, for example, as shown in FIG. 1, two input paths L11 and L12 from the SC block SCB1 to the custom block CB1 are exclusive OR (hereinafter referred to as EXOR). ) It is connected to the gate EX, and its output is input to the SC block SCB1 from the output path L13. In the scan mode, such a simple logical operation is performed on the signal input to the custom block CB1, and the output is returned to the SC block SCB1. Thereby, it is possible to take out and observe the output directly corresponding to the input data without being affected by the past history remaining in the custom block CB1. Therefore, the test pattern can be automatically generated by ATPG to facilitate the test.
[0025]
Next, a generalized concept of the scan mode added to the custom block CB1 will be described with reference to FIG.
[0026]
In normal operation, input operands IND1 to INDn are input n (n is an integer equal to or greater than 1) input data, and p (p is an integer equal to or greater than 1) input data specifying the type of operation is input. The operation codes INC1 to INCp are used. The operations specified by the input opcodes INC1 to INCp are performed on the input operands IND1 to INDn. As a result, m (m is an integer greater than or equal to 1) data is output as output operands OUTD1 to OUTDm (m is an integer greater than or equal to 1), and q (q is an integer greater than or equal to 1) indicating an operation flag or the like ) Output opcodes are output.
[0027]
In contrast to the normal operation, when the scan mode setting signal SMS is input, the type of calculation designated by the input opcodes INC1 to INCn is ignored, and the operation is switched to a fixed calculation dedicated to the scan mode. Although the content of this calculation can be set arbitrarily, it is desirable that the operation is a logical operation that is equivalent to or simpler than the normal operation, such as the EX-OR operation, and that allows a high failure detection rate.
[0028]
As a specific example of the custom block CB1, a design method for an arithmetic unit and its configuration will be described with reference to FIG. Two input operands INDA and INDB are input to the arithmetic unit ALU. The operation opcode OOC is input to specify the type of operation, the result of the operation is output as the output operand OUTD, and a flag indicating the operation result such as the occurrence of carry is output as the operation flag OF.
[0029]
A terminal for inputting a scan mode setting signal SMS for setting the scan mode to such a commonly used arithmetic unit ALU and the operation opcode OOC when the signal SMS is input are fixed and ignored. Means for performing an operation, means for outputting the result of the fixed operation as an output operand OUTD, and means for outputting an operation flag OF indicating the result of the operation are added.
[0030]
In normal operation, the operation specified by the operation opcode OOC includes, for example, a plurality of types of operations such as addition, subtraction, multiplication, and division of arithmetic operations and AND, OR, and EXOR of logical operations. On the other hand, when the scan mode is set, it is fixed to one type of operation such as logical operation EXOR. In general, since the arithmetic unit ALU includes an EXOR arithmetic means, it can be used without being newly added.
[0031]
Further, regarding the generation of the operation flag OF, in the scan mode, the operation flag OOF is output by reducing the number of bits of the output data using the compression circuit CC for the operation opcode OOC. For example, when the operation opcode OOC is composed of 3 bits, a 4-bit input is input to the compression circuit CC, an operation such as EXOR is performed, and a 1-bit operation flag OF is output.
[0032]
As described above, when EXOR is used as the fixed operation in the scan mode, it is possible to detect a failure in the path from the input of the two input operands INDA and INDB to the operation.
[0033]
On the other hand, it is conceivable to use an operation in which the input operand INDA is fixed to “1” regardless of the value of the input operand INDB and the input operand INDA is multiplied by “1”. In this case, the calculation content is simpler, but failure detection in the input path of the input operand INDB cannot be performed.
[0034]
As another specific example of the custom block CB1, a design method and a configuration of a writable and readable memory will be described with reference to FIG. The memory MCA receives an address AD as an input opcode, a read / write signal R / W designating reading or writing, an enable signal ENC for activating the operation, and an input operand IND as write data. When writing is specified, the write data is written to the address specified by the address AD, and when reading is specified, the data written to the address selected by the address AD is the output operand. Read as OUTD.
[0035]
A terminal for inputting a scan mode setting signal SMS for setting the scan mode to a normal memory having the above-described configuration, and means for ignoring the address AD and fixing the address to the address “0” when this signal SMS is input And means for bypassing the write data input as the input operand IND and outputting it as the output operand OUTD.
[0036]
Thus, when the scan mode setting signal SMS is input, the input operand IND is output as the output operand OUTD regardless of the address AD and regardless of the history of data written so far. Therefore, the input / output relationship is simplified without being affected by past data, and failure detection becomes possible.
[0037]
Further, not only the input operand IND but also the input address AD is output as the output operand OUTD, so that it is possible to detect a failure in the input path of the address AD. In this case, control means for switching and outputting either the input operand IND or the address AD is required. For example, the read / write signal R / W may be used for control.
[0038]
As described above, by adding the scan mode configuration to the memory according to the present embodiment, the logical relationship between the input and the output can be simplified and the test pattern can be automatically generated by the ATPG.
[0039]
The arithmetic unit ALU and the memory MCA have output operands. However, the custom block CB does not necessarily have an output operand but may only have an operation flag. A scan mode can be added to such a block according to the present embodiment.
[0040]
As an example of this case, a coincidence detector is shown in FIG. At least two input operands INDA and INDB are input to the coincidence detector DT, and coincidence or disagreement is determined by, for example, EXOR operation or the like. The calculation result is output as a calculation flag OF.
[0041]
According to the present embodiment, the coincidence detector DT is supplied with means for inputting the equivalent or scan mode setting signal SMS, means for performing simplified calculation when this signal is input, and outputting the calculation result. And a means to do. Thus, when a scan mode setting signal is input, a predetermined calculation is performed between the input operands INDA and INDB, and the calculation flag OF is output. As the calculation contents, an EXOR calculation may be performed as in the normal operation. Alternatively, the operation may be performed by using only one input operand INDA and fixing the other input operand INDB to a value of “1”, for example, regardless of its value.
[0042]
As described above, by combining the custom block CB1 designed to add the scan mode according to the present embodiment with the SC block SCB1, the logical relationship between the inputs and outputs of the custom block CB1 is simplified. Even in the boundary region, failure detection can be performed using the scanning method. Thereby, a test pattern can be automatically generated using ATPG without the designer recognizing detailed circuit specifications.
[0043]
In addition, when a scan mode is added according to the design method according to the present embodiment, a minimum function of performing output by a simple logical operation fixed using a control system normally provided in a custom block is added. Can be realized. Therefore, the addition of the scan mode is not brought about, and the influence such as an increase in circuit scale and a decrease in operation speed can be minimized.
[0044]
The above-described embodiment is an example and does not limit the present invention. For example, the configurations of the arithmetic unit ALU and the memory MCA shown in FIG. 3 and FIG. 4 as a custom block are merely examples, and the present invention is not limited to this, and various modifications are possible.
[0045]
【The invention's effect】
As described above, according to the integrated circuit design method of the present invention and the integrated circuit designed by this method, the input / output logic in the scan mode is simplified from the normal operation, so that the ATPG or the like is used. Test patterns can be automatically generated to facilitate testing.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an integrated circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a custom block included in the integrated circuit.
FIG. 3 is a block diagram showing the configuration of a computing unit as an example of the custom block.
FIG. 4 is a block diagram showing a configuration of a memory as an example of the custom block.
FIG. 5 is a block diagram showing a configuration of a coincidence detector as an example of the custom block.
FIG. 6 is a block diagram showing a configuration of a conventional integrated circuit.
[Explanation of symbols]
SCB1 Standard cell block CB1 Custom block F / F Scan flip-flop SIT External input / output terminal AR1 area (area where failure can be detected by scan design)
IND1 to INDn, INDA, INDB, IND Input operand OUTD1 to OUTDm, OUTD Output operand INC1 to INCp Input opcode OUTC1 to OUTq Output opcode SMS Scan mode setting signal OOC Operation opcode OF Operation flag CC Compression circuit AD Address R / W Read Write signal ENC Enable signal DT Match detector

Claims (4)

An integrated circuit that applies a scan technique to an integrated circuit that receives an input operand and an input opcode in a normal operation mode, performs a predetermined process specified by the input opcode, and outputs at least one of the output operand and the output opcode. A design method,
When the scan mode is set, regardless of the predetermined process specified by the input opcode, a process that is fixed in advance and simpler than the predetermined process is performed on the input operand.
A method for designing an integrated circuit, wherein the result obtained by performing the processing is output as at least one of the output operand and the output opcode. An integrated circuit in which a scanning technique is applied to an integrated circuit that receives an input operand and an input opcode in a normal operation mode, performs a predetermined process specified by the input opcode, and outputs at least one of the output operand and the output opcode Because
In addition to the means for performing the predetermined processing, the integrated circuit includes:
Scan mode setting means for setting the scan mode;
Processing means for performing processing that is fixed in advance and simpler than the predetermined processing on the input operand regardless of the predetermined processing specified by the input opcode when the scan mode is set by the scan mode setting means; ,
An integrated circuit, further comprising: means for outputting a result obtained by the processing by the processing means as at least one of the output operand and the output opcode. The integrated circuit is an arithmetic unit;
The scan mode setting means is a scan mode setting signal input terminal to which a scan mode setting signal is input,
The processing means performs the fixed processing on the input operand when the scan mode setting signal is input;
3. The integrated circuit according to claim 2, wherein the output means outputs the result processed by the processing means as at least one of the output operand and the output opcode. The integrated circuit is a writable and readable memory;
In normal operation, the input operand is write data, the input opcode includes an address and a control signal designating write or read, and the output operand is read data,
The scan mode setting means is a scan mode setting signal input terminal to which a scan mode setting signal is input,
When the scan mode setting signal is input, the processing means selects and bypasses either the input operand or the input operand based on the control signal,
3. The integrated circuit according to claim 2, wherein the output means outputs the output operand as bypassed by the processing means.

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