JP3673989B2 - Interleave circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interleave circuit used for BS digital broadcasting.
[0002]
[Prior art]
The interleaving method used in BS digital broadcasting is (a) block interleaving in units of superframes, (b) interleaving is 8 in the frame direction, and (c) processing is performed for each slot, depending on the frame configuration. There is a feature that does not.
[0003]
Next, a procedure for writing / reading data to / from the interleave memory in the interleave circuit will be described. FIG. 12 shows a writing procedure to the interleave memory. The first byte of slot # 1 in frame # 1 is written sequentially in the slot direction. Here, when the memory addresses are displayed in an array and (frame number, slot number, byte number), the top is (0, 0, 0). The final address of the first slot is (0, 0, 202), and the process proceeds to the beginning of slot # 2. Similarly, when the frame reaches the final value (0, 47, 202), it becomes the next frame and starts from (1, 0, 0). As described above, when all the 8 frames (superframes) are written, the writing memory is switched as described later, and the next superframe interleave writing is started again.
[0004]
When the address is displayed as an absolute address, it is as follows. Since one slot is 203 bytes, one frame is 48 slots, and one super frame is eight frames, “absolute address = frame number × 9744 + slot number × 203 + byte number”. Here, 9744 is the number of bytes for one frame, which is 203 bytes × 48 slots. Byte data input from address 0 is sequentially written.
[0005]
Next, the interleave reading procedure is shown in FIG. The reading procedure is different from the writing procedure, and reading is performed along the frame direction. The head is (0, 0, 0). Next is the first byte (1, 0, 0) of frame # 2, and after reading up to (7, 0, 0) of frame # 7, it moves to the second byte of frame # 1. Reading in the frame direction is repeated until reading of 203 bytes for one slot is completed. Up to this point, slot # 1 has been interleaved. Therefore, the multiplexed frame configuration after interleaving is not different from the configuration before interleaving.
[0006]
Next, the process proceeds to slot # 2 and similarly starts reading in the frame direction. The final address of the first slot is (2, 0, 25), and the final address of the first frame is (2, 47, 25). As shown in the figure, the second frame returns to the slot # 1 and starts from (3, 0, 25) next to the last address (2, 0, 25) of the first slot of the first frame.
[0007]
Thus, when performing interleaving using a memory, the address generator becomes important. FIG. 14 is a schematic block diagram showing the configuration of a conventional interleave circuit. Here, as an example of the transmission mode, 46 slots are transmitted with TC (trellis code) 8PSK, 1 slot is transmitted with QPSK, coding rate r = 1/2, and a dummy is 1 slot. Yes.
[0008]
Actually, since data is continuously input to the interleave memory, the memory for two superframes of the interleave memory 1 and the interleave memory 2 having a storage capacity for one superframe, the write address generator 3 and the read When writing to the interleave memory 1 using the address generator 4, the dummy slot is read from the interleave memory 2, and when writing to the interleave memory 2, the dummy slot is read from the interleave memory 1. It is controlled to read out. As a result, control is performed so that one interleave memory is not simultaneously read and written.
[0009]
As a result, writing and reading to one interleave memory are not performed simultaneously, and overwriting of data that has not been read can be prevented. Write data to the interleave memory is written in a 203-byte section excluding the first 1 byte, including a dummy slot. The write address is generated by the write address generator 3, and similarly the read address is generated by the read address generator 4. These address generators 3 and 4 operate with their timings matched by the input superframe timing signal.
[0010]
On the other hand, the read data is interleaved 203-byte data, but is not output because the dummy slot is not transmitted. This can be achieved by controlling the address of the dummy slot portion to be skipped by the read address generator 4. However, since the inner coding speed differs depending on the transmission method, in the example of FIG. 14, the reading speed of the slot of QPSK, r = 1/2 is read at half the speed of the slot of TC8PSK.
[0011]
[Problems to be solved by the invention]
However, when using a conventional interleave circuit, an interleave memory having a storage capacity of two superframes is required to perform the interleave. The capacity is “203 (bytes) × 48 (slots) × 8 (frames) × 2 = 155904 bytes”, and there is a problem that it becomes a heavy burden for LSI implementation.
[0012]
It is an object of the present invention to provide an interleave circuit that requires less storage capacity of an interleave memory.
[0013]
[Means for Solving the Problems]
  An interleave circuit according to the present invention is an interleave circuit in BS digital broadcasting, which specifies an interleave memory and an address for reading data from the interleave memory, and sequentially inputs data to the address from which the data is read. Address generating means for addressing to store and addressing to read out the stored data by interleaving,
The address generating means sets S as the number of slots constituting one frame in BS digital broadcasting, m as the number of main signals constituting one slot in BS digital broadcasting, and n as the number of frames constituting one super frame of BS digital broadcasting. When the depth of interleaving is
  An m-ary counter that counts the number of input main signals;
  an S-adic counter that counts the carry of the m-adic counter;
  A multiplier for multiplying the count value of the S-adic counter by (n × m);
  When the count main signal value reaches (m-1), increment the interleave depth.An offset value counting means that counts the main signal in the slot direction and repeats in a similar manner until the count value reaches (n × m);
  Adding means for adding the output of the multiplier and the count value of the offset value counting means;
  And the output of the adding means is address data A.
[0014]
According to the interleave circuit of the present invention, data is read from the address of the interleave memory specified by the address generating means, and the address is specified to store the sequentially input data at the address from which the data is read. In addition, an address is designated to read out the stored data by interleaving. Therefore, the storage capacity of the interleave memory is small.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Next, an interleave circuit according to the present invention will be described with reference to an embodiment.
[0016]
FIG. 1 is a schematic block diagram showing a configuration of an interleave circuit according to an embodiment of the present invention. The interleave circuit according to the embodiment of the present invention exemplifies a case where trellis coding (TC) 8PSK has 46 slots, QPSK (coding rate r = 1/2) has 1 slot, and a dummy has 1 slot.
[0017]
An interleaving circuit according to an embodiment of the present invention includes an address generator 5 that receives address data, a read / write signal (R / W), and a write gate signal in response to a superframe timing signal and a transmission mode signal, and data and address The interleave memory 6 that receives the data and the read / write signal, writes the data to the address position designated based on the write instruction by the read / write signal, reads the data from the address position designated based on the read instruction, and the superframe timing signal A timer 7 for generating a buffer read start signal delayed by one slot period, and a buffer memory 8 for writing and reading data read from the interleave memory 6 in response to a write gate signal and a buffer read start signal It is equipped with a.
[0018]
Here, the address generator 5 discriminates the dummy slot based on the transmission mode signal, generates a write gate signal in which the position of the dummy slot determined based on the transmission mode signal is removed, and deletes the dummy slot in the buffer memory 8. To do.
[0019]
As described above, in the interleave circuit according to the embodiment of the present invention, instead of using the conventional 2-superframe interleave memory to alternately perform writing and reading, the following address is read at the address where the reading has been completed. By writing the input data, one address generator 5 is provided, and the interleave memory 6 has a storage capacity for one superframe. Further, since the output from the interleave memory 6 has a multiplexed frame structure of 203 bytes including the dummy slot, the dummy slot is deleted and the speed is converted by the buffer memory 8 composed of a FIFO of about 1 slot length.
[0020]
FIG. 2 shows a timing chart of each signal in the interleave circuit according to the embodiment of the present invention. FIG. 2 shows a timing chart for one frame. For example, 46 slots are transmitted in TC8PSK and 1 slot is transmitted in QPSK (r = 1/2), and operations other than the address (FIG. 2B) are repeated in units of frames.
[0021]
The address generator 5 and the timer 7 are initialized by a super frame pulse (FIG. 2A) which is a super frame timing signal, and writing to the interleave memory 6 is started. The R / W signal (FIG. 2D) is a read operation at a high potential and a write operation at a low potential. For the address output from the address generator 5 (FIG. 2 (b)), first the data after interleaving (FIG. 2 (e)) is read, and then the data before interleaving (FIG. 2 (c)) to the same address. ). The hatched portion in the timing chart of FIG. 2 is dummy data.
[0022]
The interleaved and read data is input to the buffer memory 8, and the coding rate is converted for the transmission mode with dummy data. A buffer memory write gate signal (FIG. 2 (f)) is output from the address generator 5 in accordance with the transmission mode so that the dummy data is not written to the buffer memory 8. When the buffer memory write gate signal is at a low potential, writing to the buffer memory 8 is not performed. The storage capacity of the buffer memory 8 is sufficient for at most one slot.
[0023]
Therefore, data is read from the buffer memory 8 by starting the reading from the buffer read start signal (FIG. 2 (g)) generated by the timer 7 after delaying the super frame pulse by one slot, 2 (h)) is read out. In this example, there is one slot of QPSK (r = 1/2) with a transmission efficiency of 1.0, so that one slot is output at a speed of 1/2 (slot # 47 in FIG. 2 (h)).
[0024]
Next, the address generator 5 will be described. Before the address generator 5 is described in detail, addressing will be described by taking interleaving depth n × block length m = 4 × 5 as an example.
[0025]
3 and 4 are schematic diagrams illustrating interleaving of interleaving depth n × block length m = 4 × 5. In FIG. 3, the addresses are described in the upper part of the cells of the memory matrix, the data numbers are described in the lower part, and the list of addresses is shown in FIG. Data is first written on the memory matrix shown in FIG. The address generator 5 sequentially outputs A [0], A [1], A [2], A [3], A [4], A [5]... A [18], A [19]. And data is written. This written data stream is always in the order of D [0], D [1], D [2], D [3], D [4], D [5]..., D [18], D [19]. is there. Since the address from the address generator 5 is simply an increment, this is set as a basic address set.
[0026]
Next, since reading from the interleave memory 6 may be performed in the depth direction, the read address order is A [0], A [5], A [10], A [15], A [1], A [ 6]... A [14] and A [19], and the data order output from the interleave memory 6 is D [0], D [5], D [10], D [15], D [1], D [6] ..., D [14], D [19]. This address order is address set (number) 1. On the read address, the next set of data is D [0], D [1], D [2], D [3], D [4], D [5 as shown in FIG. ], D [18] and D [19] are written in this order.
[0027]
To interleave and read the data written by the address set 1, the addresses are A [0], A [6], A [12], A [18], A [5], A [11]. If generated as [13], A [19], the read data is D [0], D [5], D [10], D [15], D [1], D [ 6]..., D [14], D [19], and it can be seen that they are correctly interleaved. This is address set (number) 2. On the read address, the next set of data is D [0], D [1], D [2], D [3], D [4], D [5, as shown in FIG. ], D [18] and D [19] are written in this order.
[0028]
FIG. 4 summarizes this addressing in a list. The address set number x is displayed in the top row, and the address number y is displayed in the leftmost column. The address set number “0” is a basic address set. Addresses are generated in the order of address numbers. It can be seen that the data written in the basic address set order is read in the order of the address set number 1, and the data written by the address set number 1 is read out in the order of the address set number 2 to be interleaved.
[0029]
The procedure for performing interleaving will be described with reference to FIG.
(1) Read from address set number x = 0,
(2) Write to address set number x = 0,
(3) Read from address set number x = 1,
(4) Write to address set number x = 1,
(5) Read from address set number x = 2,
(6) Write to address set number x = 2,
…
(17) Read from address set number x = 8,
(18) Write to address set number x = 8,
(19) Read from address set number x = 9 (= 0),
Thus, the input data is sequentially written at the address from which the data is read. As described above, the addressing in the interleaving with m × n = 5 × 4 circulates in a cycle in which the address set number x is 9. The cycle of the address set number is 9, which is denoted as cycle X. The period X = 0 has no meaning and X = 0 is excluded. The period X of the address set number x will be described later.
[0030]
Next, this addressing is generalized. When the depth of interleaving is n, the number of data in the writing direction (block length) is m, the address set number is x, the address number is y, and the address is A, the following relational expression is obtained.
A = (Abase (x) × y) mod (n × m−1) (1)
This is the case of (y ≠ n × m−1)
Abase (x + 1) = (Abase (x) × m) mod (n × m−1)
Abase (0) = 1
However, a mod b is a remainder obtained by dividing the integer a by the integer b.
A = y (2)
This is the case of (y = n × m−1).
[0031]
FIG. 5 shows a flowchart of address generation based on the above equations (1) and (2). When address generation is started, initialization of x = 0 and Abase (0) = 1 is performed (step S1), and y = 0 is set (step S2). Following step S2, it is checked whether y = 0 (step S3). If y = 0 is not determined, it is checked whether y = (m × n + 1) (step S4).
[0032]
If it is determined in step S4 that y = (m × n−1) is not satisfied, an operation of A = A + Abase (x) is performed (step S5), and then whether A> (m × n−1) is checked. (Step S6). When it is determined in step S6 that A> (m × n−1) is not satisfied, A is determined as an address, and address A is output (step S7).
[0033]
If it is determined in step S3 that y = 0, A = 0 is set (step S8), step S7 is executed, the address is fixed at A = 0, and the data is output. When it is determined in step S4 that y = (m × n−1), A = (m × n−1) is calculated (step S9), step S7 is executed, and the address is A = (m Xn-1) is determined and output. If it is determined in step S6 that A> (m × n−1), A = A− (m × n−1) is calculated (step S10), step S7 is executed, and the address is A = A− (m × n−1) is determined and output.
[0034]
Following step S7, it is checked whether y = m (step S11). If it is determined that y = m is not satisfied, it is checked whether y = (m × n−1) (step S12). . When it is determined in step S11 that y = m, calculation of Abase (x + 1) = A is performed following step S11 (step S13), and step S12 is executed.
[0035]
When it is determined in step S12 that y = (m × n + 1), x = x + 1 is calculated subsequent to step S12 (step S14), and then executed again from step S2. When it is determined in step S12 that y = (m × n−1) is not satisfied, y = y + 1 is calculated following step S12 (step S15), and then executed again from step S3. An address is obtained by executing the above steps.
[0036]
Moreover, said (1) Formula and (2) Formula can also be written like the following (3) Formula and (4) Formula.
A = y × m^xmod (n × m−1) (3)
This is the case of (y ≠ n × m−1)
A = y (4)
This is the case of (y = n × m−1).
[0037]
Here, the address set number x and the period X are obtained by obtaining x other than 0 that satisfies A = 1 when y = 1 in the equation (3). For example, when m = 5 and n = 4, the period X = 9 as described above. (Y × m^x) Is less than (n × m−1), A = (y × m^x) Is generated.
[0038]
The above equations (3), (4) and FIG. 5 are generalized for interleaving on a two-dimensional matrix, but can also be applied to BS digital broadcasting interleaving. FIG. 11 shows an interleave memory space in this BS digital broadcasting system. In the BS digital broadcasting system, since interleaving is 8 depths in the frame direction within the same slot, it can be treated as a collection of 48 (slots) of a two-dimensional matrix of 203 (bytes) × 8 (frames). That is, the memory space for one superframe is divided into 48, and 203 × 8 interleaving is performed in each area. However, it should be noted that the slot needs to be moved every 203 bytes.
[0039]
In the interleave circuit according to the embodiment of the present invention, a memory matrix of one superframe is defined as shown in FIG. m (= 203 (bytes)) × n (= 8 (frame)) × S (= 48 (slot)), the address is a 203 × 8 two-dimensional matrix, incremented from address 0 to the m direction, and then n If it is shifted by one step in the direction and incremented again in the m direction, and so on, the final address of one slot is 1623. In the slot direction, an offset is added by n × m = 1624 in the direction from the first slot to the 48th slot.
[0040]
Also in this case, the period X of the address set number x is obtained from x in which A = 1 when y = 1 in the equation (3), and the period X of the address set number x is 180.
[0041]
Next, address data generation in the address generator 5 will be described in detail. FIG. 6 shows an embodiment of the address data generator in the address generator 5, and FIGS. 7 and 8 show flowcharts for its operation.
[0042]
  As shown in FIG. 6, the address data generator in the address generator 5 includes a strobe pulse generator 50, a strobepulseA slot number detecting unit 51 for designating a slot number in cooperation with the generating unit 50, and a modulo calculating unit 52 for performing a modulo operation and sending out address data in cooperation with the strobe pulse generating unit 50 and the slot number detecting unit 51. And. Here, m = 203 (number of bytes of main signal in one slot), n = 8 (depth of interleaving), S = 48 (number of slots in one frame), F = 8 (number of frames constituting one super frame) Where F = n = 8) and X = 180 (cycle of address set count x). Here, the modulo arithmetic unit 52 excluding the adder 70 described later corresponds to the offset value counting means.
[0043]
The strobe pulse generator 50 is supplied with interleave write and read gate pulses output from a timing signal generator (not shown) provided in the address generator 5 and outputs the interleave write and read gate pulses during a high potential period. An m-adic counter 53 that counts clock pulses in response to a clock pulse, an S-adic counter 54 that counts the carry output of the m-adic counter 53, and an F-adic counter 55 that counts the carry output of the S-adic counter 54; An X-ary counter 56 that counts the carry output of the F-adic counter 55, a count value mcnt of the m-ary counter 53, a count value Scnt of the S-adic counter 54, a count value Fcnt of the F-adic counter 55, and the X-adic counter 56 A decoder 57 that receives the count value xcnt and generates a strobe pulse is provided.
[0044]
Since the count value of the S-adic counter 54 is incremented every time the m-ary counter 53 counts the clock pulse from 0 to 203 times, the S-adic counter 54 detects the slot number. The slot number detection unit 51 includes a multiplier 58 that receives the count value of the S-adic counter 54 and multiplies (n × m), and based on the count value of the S-adic counter 54, the slot number start address data 0, 1624, 3248,..., 76328 are generated. Data A0, which will be described later, is added to this output from the slot number detector 51 to obtain address data A.
[0045]
The modulo operation unit 52 receives a setter 59 that initializes the A offset register 60 to a set value 1, a strobe pulse sa, and receives an A offset register 60 and a strobe pulse sb in which the value of the R offset register 61 is entered. R offset register 61 for storing the address data A0, adder 62 for adding the numerical values of the address data A0 and the A offset register 60, the addition output of the adder 62 and the set value (n × m) of the setter 63 And the setting of the setting device 65 from the addition output of the adding device 62 based on the output of the comparing device 64 when (added output of the adding device ≧ setting value of the setting device 63 (n × m)). The value obtained by subtracting the value (n × m−1) is output as the address data A〃, and the ratio is obtained when (addition output of adder 62 ≧ set value of setter 63 (n × m)) is not satisfied The addition output of the adder 62 based on the output of the vessel 64 and a subtracter 66 to output as address data A〃.
[0046]
The modulo arithmetic unit 52 further includes an Amcnt register 67 that receives the strobe pulse sc as address value A〃 output from the subtractor 66, and an address data A〃 output from the subtractor 66 and the Amcnt register 67. A selector 68 for selecting one of the numerical values by a select pulse sp, a latch 69 composed of DF / F for delaying the address data A ′ output from the selector 68 for a period of one clock pulse, and latched address data A0 An adder 70 for adding the output of the multiplier 58 is provided, and the output of the adder 70 is address data A.
[0047]
The strobe pulse sa to the A offset register 60 is output in synchronization with the carry output of the F-adic counter 55. However, when xcnt = X−1, 1 is set, and when xcnt ≠ X−1, the set value Rofset of the R offset register 61 is set. The strobe pulse sb to the R offset register 61 is output when the count value Fcnt of the F base counter 53 is 0, the count value Scnt of the S base counter 52 is 0, and the count value mcnt of the m base counter 53 is n. The
[0048]
The strobe pulse sc to the Amcnt register 67 is output when the count value Scnt of the S-adic counter 52 is 0 and the count value mcnt of the m-ary counter 53 is 0. The select pulse sp to the selector 68 is output when the count value mcnt of the m-ary counter 53 = m−1 and the count value Scnt ≠ S−1 of the S-ary counter 52, and the numerical value of the Amcnt register 67 is set. Selected.
[0049]
The value placed in the A offset register and the address data A0 are added by the adder 62, and the addition result is sent to the comparator 64 and the subtractor 66. The address data A0 is address data on a two-dimensional matrix of 203 × 8, and the count value Scnt of the S-adic counter 54 that counts the number of slots is multiplied by n × m by the multiplier 58 (that is, offset in the slot direction). ) The addition result of the value and the address data A0 becomes the address data A.
[0050]
The comparator 64 outputs a subtraction instruction to the subtractor 66 when the addition output of the adder 62 becomes (n × m (= 1624)) or more, and the subtractor 66 receives the subtraction instruction and receives the subtraction instruction. (N × m−1) set in the setting device 65 is subtracted from the addition output from If the addition output of the adder 62 is not equal to or greater than (n × m (= 1624)), no subtraction is performed, and the addition output of the adder 62 is output from the subtractor 66 as it is.
[0051]
The Amcnt register 67 stores the address data A〃 at the time when the strobe pulse sc is generated. When the selector 68 receives the select signal sp, the value A〃 of the Amcnt register 67 is selected and output. The output from the selector 68 is taken as address data A ′. The address data A ′ is latched by the latch 69, and the latch output is address data A0. Further, the R offset register 61 receives the strobe pulse sa, and the data A0 at that time is entered. Further, the numerical value of the R offset register 61 is output to the A offset register 60, and is stored in the A offset register 60 in response to the strobe pulse sa.
[0052]
The m-adic counter 53, the S-adic counter 54, the F-adic counter 55, the X-adic counter 56, and the latch 69 operate with a common clock pulse. However, the operation is performed when the interleave memory write / read gate pulse is at a low potential. Stop.
[0053]
  Figure7And figure8The operation of the address data generator in the address generator 5 will be described based on the flowchart of FIG.
[0054]
When the interleaving is started, the value Aofset of the A offset register 60 is initialized to 1, and the count value xcnt of the X-ary counter 56, that is, the address set number x is initialized to 0 (step S21). Also, the count value mcnt of the m-ary counter 53, the count value Scnt of the S-ary counter 54, and the count value Fcnt of the counter F54 are initialized to 0, the latch 69 is also initialized, and the address data A0 is also initialized (step). S22).
[0055]
The data A の at this time is placed in the Amcnt register 67, but in this case, 0 is placed (step S23). Further, since the strobe pulse sc becomes high potential when the count value mcnt of the m-ary counter 53 is 0 and the count value Scnt of the S-ary counter 52 is 0, the number in the Amcnt register 67 is incremented by the F-ary counter 55. Will be done every time.
[0056]
The value entered in the Amcnt register 67 output via the selector 68 is latched by the latch 69, and the address data A0 is determined (step S24). The decoder 57 checks whether the count value Fcnt = 0 of the F-adic counter 55, the count value Scnt = 1 of the S-adic counter 54, and the count value mcnt = 0 of the m-ary counter 53, that is, Scnt × 203 + mcnt = 203 ( Step S25).
[0057]
When it is determined in step S25 that the count value Fcnt = 0 of the F-adic counter 55, the count value Scnt = 1 of the S-adic counter 54, and the count value mcnt = 0 of the m-adic counter 53, that is, the address number y = 203 are determined. The pulse sb is output, the address data A0 is entered in the R offset register 61 (step S26), and step S27 is executed. However, since the count value mcnt of the m-ary counter 53 is 0 at this time, steps S25 to S27 are executed.
[0058]
Until the count value mcnt of the m-ary counter 53 reaches the count value mcnt = m−1 (= 202) in step S27, the count value mcn of the m-ary counter 53 is not shown in FIG. Is incremented, and then step S28 is executed. In step S28, the adder 62 adds the address data A0 and the numerical value stored in the A offset register 60 (step S28). When the addition output A ′ ′ of the adder 62 is equal to or greater than (n × m (= 1624)) (step S29), (n × m−1 (= 1623)) is subtracted from the addition output A ′ ′. The process is executed from step S24 (step S30). When the addition output A ′ ′ of the adder 62 is not (n × m (= 1624)) or more, the process is executed from step S24 following step S29.
[0059]
When the above operation is compared with the above general formula of addressing, the value set in the A offset register 60 is equal to n to the power of x (when n raised to the power of (n × m−1), (n Xm-1) is equal to the remainder when the subtraction is repeated), and the x power of y × n is equal to the cumulative addition of x power of n. Also, the (n × m−1) modulo operation is performed when the data A ′ ′ does not exceed twice (n × m−1), and therefore when (n × m−1) is exceeded ( By subtracting n × m−1), the configuration can be simplified. At the final address where the data A ′ ′ is equal to (n × m−1), subtracting (n × m−1) becomes 0, causing a problem.
[0060]
However, since A〃 ′ is equal to (n × m−1) only at the final address, the subtraction condition is subtracted (n × m−1) when (n × m) is exceeded. Then, this can be avoided by changing. This is equivalent to simplifying the condition of A = y when y = n × m−1 in the general formula of addressing.
[0061]
When the count value mcnt of the m-adic counter 53 becomes m−1 (= 202), a conditional branching step based on the count value Scnt of the S-adic counter 54 is executed (step S31). Step S32 is executed until the count value Scnt of the S-adic counter 54 reaches S-1 (= 47), and step S32 and step S24 are repeatedly executed. In step S32, the count value Scnt of the S-adic counter 54 is incremented, the count value mcnt of the m-ary counter 53 is reset, and the numeric value of the Amcnt register 67 is output as the address data A '(step S32). That is, the value of the Amcnt register 67 is selected by the selector 68. This operation is for making the initial value of the address data A of each slot equal within the frame.
[0062]
For example, the address data A0 of each slot starts from 0 in the first frame, and starts from 203 in the second frame. Therefore, in the second frame, it is necessary to load 203 to the address data A0 every time the slot is changed. At this time, the count value Fcnt of the F-adic counter 55 is 0, that is, the first frame, so that 0 that is set in the Amcnt register 67 is loaded every time the slot is incremented. The above operation is repeated until the count value Scnt of the S-adic counter 54 becomes S-1 (= 47).
[0063]
When the count value Scnt of the S-adic counter 54 becomes S-1 (= 47), a conditional branch step based on the count value Fcnt of the F-adic counter 55 is executed (step S35). In step S35, if the count value Fcnt of the F-adic counter 55 is less than F-1, step S36 is executed, the count value Fcnt of the F-adic counter 55 is incremented, and the count value Scnt and m-adic of the S-adic counter 54 are incremented. The count value mcnt of the counter 53 is reset (step S36). Subsequently, A0 is accumulated in the A offset register 60 (step S37). This is because the initial value of the address data A0 when the frame is changed is the next value of the final value data A0 of the previous frame.
[0064]
That is, when the address set number x is 0, the final address data A0 of the first frame is 202, and the value of the A offset register 60 is 1 at the beginning of the second frame, so 202 + 1 = 203. . As a result of step S35, step S38 is executed, and data A ′ ≧ (n × m) is checked. As a result of step S38, step S39 is selectively executed, and then step S23 is executed. When the data A ′ exceeds (n × m), (n × m−1) is subtracted (step S39) as in the case described above. Further, this result is entered in the Amcnt register 67 in step S23 and becomes a value loaded every time the slot is changed.
[0065]
If the count value Fcnt of the F-adic counter 55 becomes F-1 (= 7) in step S35, interleaving for one superframe is completed at this point. If the address set number x has not reached x = X-1 (= 179) by the conditional branch (step S40) based on the count value xcnt of the X-ary counter 56, step S41 is executed, and in step S26. The counted value of the R offset register 61 is stored in the A offset register 60 (step S41). Further, the address set number x is incremented (step S42).
[0066]
This operation will be described with reference to the general addressing formulas (3) and (4).
[0067]
The numerical value of the A offset register 60 is equal to the mth power of x, that is, the address data A in the case of y = 1 ((A = 1 × m to the power of x)) (as described above, m When the value exceeds (n × m−1), it is equal to the remainder when the subtraction is repeated at (n × m−1)). The value Aofset ′ of the A offset register 60 of the next address set is the same. 1 × m raised to the (x + 1) th power = 1 × m raised to the xth power × m, which is equal to the address data A when y = 203
[0068]
In other words, if the address data A of the current y = 203 is stored, this becomes Aofset ′ which is the value of the A offset register 60 of the next address set number x, and the calculation circuit can be omitted. Since the address data A when y = 203 is stored in the R offset register 61 in steps S25 and S26, it is written in the A offset register 60 before proceeding to the next address set. When the count value xcnt of the X-ary counter 56 becomes X-1 (= 179), all are initialized.
[0069]
A part of the address data A generated according to the present embodiment is shown in FIGS. From the relationship of space, the address set number x is up to 18 and the address number y is up to 55.
[0070]
As described above, according to the interleave circuit according to the present embodiment, read (R), write (W), read (R), address data A to the interleave memory generated by the address data generator, Reading is performed prior to writing, such as writing (W),..., And data is written to an address that is vacant as a result of reading data, thereby improving the memory usage efficiency. .
[0071]
【The invention's effect】
According to the interleave circuit of the present invention, interleaving can be performed with an interleave memory having a storage capacity for one superframe, and the number of parts and the circuit scale can be greatly reduced. In particular, when an integrated circuit is formed, the number of gates can be greatly reduced, the chip area can be reduced, and the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a configuration of an interleave circuit according to an embodiment of the present invention.
FIG. 2 is a timing diagram of each signal in the interleave circuit according to the embodiment of the present invention.
FIG. 3 is a schematic diagram for explaining the principle of interleaving in the interleaving circuit according to the embodiment of the present invention.
FIG. 4 is a schematic diagram for explaining the principle of interleaving in the interleaving circuit according to the embodiment of the present invention.
FIG. 5 is a flowchart for address generation by an interleave circuit according to an embodiment of the present invention;
FIG. 6 is a block diagram showing a configuration of an address data generator provided in the address generator in the interleave circuit according to the embodiment of the present invention.
FIG. 7 is a flowchart for explaining an address generation operation in the interleave circuit according to the embodiment of the present invention;
FIG. 8 is a flowchart for explaining an address generation operation in the interleave circuit according to the embodiment of the present invention;
FIG. 9 is a schematic diagram showing a part of generated addresses in the interleave circuit according to the embodiment of the present invention;
FIG. 10 is a schematic diagram showing a part of a generated address in the interleave circuit according to the embodiment of the present invention.
FIG. 11 is a schematic diagram for explaining an interleave memory space in BS digital broadcasting.
FIG. 12 is a schematic diagram for explaining an interleave writing operation in BS digital broadcasting;
FIG. 13 is a schematic diagram for explaining an interleave reading operation in BS digital broadcasting.
FIG. 14 is a schematic block diagram showing a configuration of a conventional interleave circuit.
[Explanation of symbols]
5 Address generator
6 Interleaved memory
7 Timer
8 Buffer memory
50 Strobe pulse generator
51 Slot number detector
52 Modulo operation unit
53, 54 m base counter, S base counter
55, 56 F base counter, X base counter
57 Decoder
58 multiplier
59, 63, 65 Setting device
60, 61 A offset register, R offset register
62, 70 Adder
64 comparator
66 Subtractor
67 Amcnt register
68 selector
69 Latch

Claims (1)

An interleave circuit in BS digital broadcasting, which specifies an interleave memory, an address for reading data from the interleave memory, and an address for storing sequentially inputted data at the address from which the data is read, And address generating means for performing address designation for reading the stored data by interleaving ,
The address generating means sets S as the number of slots constituting one frame in BS digital broadcasting, m as the number of main signals constituting one slot in BS digital broadcasting, and n as the number of frames constituting one super frame of BS digital broadcasting. When the depth of interleaving is
An m-ary counter that counts the number of input main signals;
an S-adic counter that counts the carry of the m-adic counter;
A multiplier for multiplying the count value of the S-adic counter by (n × m);
When the count main signal value reaches (m-1), the interleaving depth is incremented and the main signal is counted in the slot direction. Similarly, the count is repeated until the count value reaches (n × m). Value counting means;
Adding means for adding the output of the multiplier and the count value of the offset value counting means;
And an interleave circuit characterized in that the output of the adding means is address data A.

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