JP3666863B2 - Waveform observation device - Google Patents

Description

となり、この周波数ｆｓのサンプリング信号Ｓでサンプリングを行なえば、データ信号Ｘの１０（＝Ｎ）フレーム毎に、０．１ｐｓ（＝ΔＴ）ずつ遅れてサンプリングを行なうことができる。
【００５１】
なお、このサンプリング周波数ｆｓは、信号発生器２５の内部で例えば１０ＧＨｚの信号を発生させ、これを分周器で１／１０００００００００１に分周し、その分周出力を逓倍器で１００００倍することで得ることができる。
【００５２】
次に、制御部３３は、入力された各パラメータに基づいて観測期間毎のサンプリング開始タイミングを、サンプリング周期単位で算出する（Ｓ３）。
【００５３】
この観測期間毎のサンプリング開始タイミングは、入力端子２０ｂから入力された一つのフレーム同期信号Ｆを基準にして求める。
【００５４】
即ち、入力端子２０ｂから入力されるフレーム同期信号Ｆと信号発生器２５から出力されるサンプリング信号Ｓとは非同期で周期も異なるが、ここでは、図５の（ａ）に示しているように、ある一つのフレーム同期信号Ｆが入力したタイミングに、図５の（ｃ）のように、信号発生器２５がサンプリング信号Ｓを出力するように強制同期させる。
【００５５】
この強制同期のタイミングを基準タイミングとすれば、図５の（ｂ）のように、データ信号Ｘのフレーム内の任意の観測開始ビット位置ｊは、基準タイミングから（ｊ−１）／Ｂが経過したタイミングであることがわかる。
【００５６】
サンプリング信号Ｓの周期Ｔｓは、データ信号のＮフレーム毎にΔＴずつずれるから、この時間（ｊ−１）／ＢをΔＴで除算することで、サンプリング信号Ｓの出力タイミングが観測開始ビット位置ｊになるまでのサンプリング信号の出力回数Ａ（１）を求めることができ、その回数Ａ（１）が最初の観測期間のサンプリング開始タイミングとなる。
【００５７】
なお、基準タイミングから観測開始ビット位置ｊの信号が入力されるまでの時間は（ｊ−１）／Ｂで一定であるから、これを観測分解能ΔＴで除算して得られるサンプリング開始タイミングＡ（１）も一定であり、パラメータが指定された時点で予め求めておくことができる。
【００５８】
次に、観測期間の数が複数の場合、２回目以降の各観測期間のサンプリング開始タイミングを以下のようにして求める。
【００５９】
即ち、２回目以降の各観測期間のサンプリング開始タイミングが、初回の観測期間のサンプリング開始タイミングと同一位置からサンプリングされるためには、前の観測期間のサンプリング開始タイミングと次の観測期間のサンプリング開始タイミングとの間隔が、サンプリング信号の周期ＴｓにＰより大きい整数Ｖを乗じた値で、且つデータ信号Ｘのフレーム周期Ｔｘの整数Ｕ倍に一致する必要がある。
【００６０】
つまり、
Ｖ・Ｔｓ＝Ｕ・Ｔｘ
となり、各周期Ｔｓ、Ｔｘは既知であるから、
Ｔｓ／Ｔｘ＝Ｕ／Ｖ
を満たす整数のＶ、Ｕの組合せのうち、Ｐより大きい最小のＶを求める。
【００６１】
数値例で示すと、前記したように、ｆｘ＝Ｂ／ｎ＝１０ｋＨｚ、サンプリング信号Ｓの周波数ｆｓを、
ｆｓ＝１０×１０^３／（１０．００００００００１）Ｈｚ
とすれば、
Ｔｓ／Ｔｘ＝ｆｘ／ｆｓ＝１０．００００００００１＝Ｕ／Ｖ
となる。
【００６２】
ここで、各観測期間内のサンプリング数Ｐを例えば１０２４とすれば、

と表すことができ、その最小のＶの値は２０００００００００＝２×１０^９となる。
【００６３】
したがって、最初の観測期間のサンプリング開始タイミングＡ（１）から（２×１０^９）・Ｔｓが経過したタイミングに次の観測期間のサンプリングを開始すればよく、これをカウンタ３０の計数値（最初の観測期間のサンプリング開始タイミング時の初期値を０とする）で表せば、２回目の観測期間の開始タイミングは計数値Ｃｓ＝Ａ（２）＝Ａ（１）＋（２×１０^９）のときであり、３回目の観測期間の開始タイミングは計数値Ｃｓ＝Ａ（３）＝Ａ（１）＋（４×１０^９）のときであり、同様にｉ回目の観測期間の開始タイミングは計数値Ｃｓ＝Ａ（ｉ）＝Ａ（１）＋［（ｉ−１）×２×１０^９］のときであり、最後のＱ回目の観測期間の開始タイミングは計数値Ｃｓ＝Ａ（Ｑ）＝Ａ（１）＋［（Ｑ−１）×２×１０^９］のときである。
【００６４】
以上の演算を行なうことで、各観測期間のサンプリング開始タイミングＡ（１）〜Ａ（Ｑ）を、サンプリング信号Ｓの周期単位で求めて図示しないメモリに記憶する。
【００６５】
なお、上記処理Ｓ２の演算で得られた周波数等の理想値の下位の全ての有効な値を信号発生器２５に設定できる場合には設定誤差が生じないが、演算で得られた周波数等の理想値の下位の全ての有効な値を信号発生器２５に設定できず、設定できない下位の有効な値を切り捨てた場合には設定誤差が生じ、その設定誤差によってサンプリングタイミングに誤差が生じる。
【００６６】
したがって、ここで設定誤差があるか否かを判定し、設定誤差がない場合には、観測期間を表す変数ｉを１に初期化し、前記したように、一つのフレーム同期信号Ｆが入力したタイミングにサンプリング信号Ｓを強制的にフレーム同期信号Ｆに同期させ、カウンタ３０をリセットする（Ｓ４〜Ｓ８）。
【００６７】
そして、カウンタ３０の計数値Ｃｓを監視して、その計数値ＣｓがＡ（ｉ）−１になった直後に、第１のゲート回路３１をオン状態にし、その次のサンプリング信号Ｓから最初の観測期間のサンプリングを開始させる（Ｓ９、Ｓ１０）。
【００６８】
そして、この最初の観測期間に対するサンプリングがＰ回行なわれて、カウンタ３０の計数値ＣｓがＡ（ｉ）＋Ｐ−１になると、制御部３３は第１のゲート回路３１をオフ状態にしてサンプリング部２１によるサンプリングを停止させ、観測期間を示す変数ｉが最終値Ｑか否かを確認する（Ｓ１１〜Ｓ１３）。
【００６９】
ここで、単発観測モードの場合にはＱ＝１であり、最終値となるので測定が終了するが、繰り返し観測モードの場合には、変数ｉを１だけ増加更新して、その変数ｉに対応する次の観測期間のサンプリング開始タイミングＡ（ｉ）を読み出し、カウンタ３０の計数値ＣｓがＡ（ｉ）−１になるまで待つ（Ｓ１４、Ｓ１５）。
【００７０】
そして、カウンタ３０の計数値ＣｓがＡ（ｉ）−１になると、その次に入力されるサンプリング信号からサンプリング部２１に入力されるように第１のゲート回路３１をオン状態に戻して次の観測期間のサンプリングを開始させ、処理Ｓ１１に戻る（Ｓ１６）。
【００７１】
以下、同様の処理を変数ｉを１ずつ増加させながらＱに達するまで行い、Ｑ回の観測期間のサンプリングが終了する。
【００７２】
各観測期間中にサンプリング部２１でサンプリングされたデータＤｓは、表示制御手段２２に入力され、その入力順に内部のメモリの各観測期間に対応する領域にアドレス順に記憶され、そのデータが読み出されて表示器２３に出力され、波形表示される。
【００７３】
例えば、同一データ列がフレーム単位で繰り返されるデータ信号Ｘに対して単発観測モードを行なった場合には、図６の（ａ）のように、データ信号のｊビット目からの信号波形が表示される。
【００７４】
また、フレーム毎にデータ列が異なるデータ信号Ｘに対して繰り返し観測モードを行なった場合には、図６の（ｂ）のように、複数の観測期間で得られた波形が重ね合わせ表示されるため、その重ね合わせ波形のビット境界部分の線の太さから、データ信号のジッタの大小を把握できる。この場合、一つのフレーム同期信号Ｆの入力タイミングを基準にしてデータ信号をサンプリングしているので、フレーム同期信号Ｆ自体のジッタの影響を受けず、データ信号自体のジッタ成分のみを正確に把握できる。
【００７５】
一方、処理Ｓ４で前記設定誤差があると判定された場合には、図３に示しているように信号発生器２５に実際に設定した基準周波数ｆｒ、対象機器１の逓倍数ｍ、前記数値Ｎ、入力された観測分解能ΔＴから、実際に入力されるデータ信号ＸのビットレートＢに正確に対応したサンプリング信号の理想周期Ｔｓｒを、
Ｔｓｒ＝Ｎ／（ｍ・ｆｒ）＋ΔＴ
の演算で求める（Ｓ１７）。
【００７６】
そして、信号発生器２５から実際に出力されるサンプリング信号Ｓの周期Ｔｓの理想周期Ｔｓｒに対するの誤差ｅを、
ｅ＝Ｔｓｒ−Ｔｓ
の演算で求める（Ｓ１８）。
【００７７】
この誤差ｅはサンプリング信号の出力毎に累積されるが、その累積値Ｅが観測分解能ΔＴに等しくなるか越える毎に、時間軸とサンプリングデータとの対応関係を補正処理して、誤差累積によるサンプリングタイミングのずれを防止することができる。なお、この補正動作は、期間に関係なくその累積値Ｅが観測分解能ΔＴに等しくなるか越える毎に直ちに行なう場合と、観測期間中に発生するものについてはその都度行い、観測期間とその次の観測期間の間に発生するものについてはその間にまとめて行なう場合とがあるが、ここでは前者の場合について説明する。
【００７８】
また、誤差ｅは、設定されるパラメータ等に応じて正の場合と負の場合とがあり、誤差が正の場合、即ち、実際のサンプリング周期Ｔｓが理想周期Ｔｓｒよりも短い場合と、誤差ｅが負の場合、即ち、実際のサンプリング周期Ｔｓが理想周期Ｔｓｒよりも長い場合とでは補正の方法が異なる。
【００７９】
そこで、誤差ｅの正負を判別し、誤差ｅが正のとき、何回のサンプリングで累積誤差Ｅが観測分解能ΔＴに等しくなるか越えるかを表す累積回数Ｍを、ΔＴ／ｅが整数の場合に、
Ｍ＝（ΔＴ／ｅ）
の演算で求め、ΔＴ／ｅが小数の場合に、その商Ｇに対して、
Ｍ＝Ｇ＋１
の演算で求める（Ｓ１９、Ｓ２０）。
【００８０】
そして、変数ｉを１に初期化し、補正回数を表す変数ｕを０に初期化して、前記同様に、一つのフレーム同期信号Ｆが入力したタイミングにサンプリング信号Ｓを強制的にフレーム同期信号Ｆに同期させ、カウンタ３０をリセットして、カウンタ３０の計数値Ｃｓを監視し、その計数値ＣｓがＡ（ｉ）−１になるまで待機するが、その待機中に、信号発生器２５からＭ−１個のサンプリング信号Ｓが出力されて、カウンタ３０の計数値Ｃｓが（ｕ＋１）Ｍ＋ｕ−１（この場合ｕ＝０）になると、制御部３３によって第２のゲート回路３２が１サンプリング周期Ｔｓだけオフ状態となり、次（Ｍ個目）のサンプリング信号のカウンタ３０および第１のゲート回路３１への出力が規制され、変数ｕが１だけ増加更新される（Ｓ２１〜Ｓ２８）。
【００８１】
このとき誤差ｅの累積値Ｅが、観測分解能ΔＴに等しい状態かあるいは僅かに越えた状態なので、上記のようにカウンタ３０に対するＭ個目のサンプリング信号の入力を規制することで、Ｍ＋１個目のサンプリング信号が入力されたときのタイミングを、理想周期Ｔｓｒで計数したときに計数値がＭとなるタイミングに合わせることができ、累積誤差Ｅをキャンセルすることができる。
【００８２】
この累積誤差の補正は、信号発生器２５からサンプリング信号ＳがＭ−１個出力される毎に行なわれ、カウンタ３０の計数値ＣｓがＡ（ｉ）−１になると、第１のゲート回路３１がオン状態となり、次に信号発生器２５から出力されるサンプリング信号が、サンプリング部２１に入力されて、初回の観測期間のサンプリングが開始される（Ｓ２９）。
【００８３】
この観測期間中、即ち、カウンタ３０の計数値ＣｓがＡ（ｉ）＋Ｐ−１に達する前に、信号発生器２５からサンプリング信号ＳがＭ−１個出力されて、カウンタ３０の計数値Ｃｓが（ｕ＋１）Ｍ＋ｕ−１に等しくなると、前記同様に累積誤差の補正のために第２のゲート回路３２を１サンプリング周期Ｔｓだけオフ状態にして次のサンプリング信号Ｓのカウンタ３０および第１のゲート回路３１に対する出力を停止させて、カウンタ３０の歩進およびデータ信号に対するサンプリングを１回だけ規制してから、第２のゲート回路３２をオン状態に戻して、変数ｕを１だけ増加するという処理を繰り返す（Ｓ３０〜Ｓ３３）。
【００８４】
このような処理を行なっている間にデータ信号に対するＰ回のサンプリングが行なわれて、計数値ＣｓがＡ（ｉ）＋Ｐ−１に達すると、第１のゲート回路３１をオフ状態にしてサンプリングを停止させ、変数ｉが最終値Ｑか否かを確認する（Ｓ３４、Ｓ３５）。
【００８５】
前記した単発観測モードの場合には、この段階でサンプリングが終了して、そのサンプリングで得られたＰ個のデータに基づいて波形が表示される。
【００８６】
また、繰り返し観測モードの場合には、変数ｉを１だけ増加させて、カウンタ３０の計数値Ｃｓが次の観測期間のサンプリングタイミングを示す値Ａ（ｉ）の直前の値Ａ（ｉ）−１となるまで待機するが、この間に前記同様に計数値Ｃｓが（ｕ＋１）Ｍ−１＋ｕに達すると、前記した処理Ｓ３０〜Ｓ３２と同様の処理がなされ、サンプリング信号の出力規制がなされる（Ｓ３６〜Ｓ４０）。
【００８７】
そして、計数値Ｃｓが次の観測期間の開始タイミングの直前を表す値Ａ（ｉ）−１になると、第１のゲート回路３１がオン状態となり、次の観測期間のサンプリングが開始されて、処理Ｓ３０に戻る（Ｓ４１）。
【００８８】
以下、同様の処理が繰り返されてＱ回の観測期間のサンプリングが行なわれ、そのＱ回の観測期間のサンプリングで得られた波形データが同一時間軸上で重ね合わせ表示される。
【００８９】
このように誤差ｅが正の場合、累積誤差が観測分解能ΔＴに等しくなるか越える毎にカウンタ３０およびサンプリング部２１へのサンプリング信号の出力を規制することで、カウンタ３０の計数値が示すタイミング（つまり時間軸）とサンプリングされるデータとが対応するように補正される。
【００９０】
このため、累積誤差Ｅを増大させることなく常に分解能ΔＴの範囲内に抑えることができ、時間軸に対して観測分解能ΔＴ以上の誤差が含まれないように表示させることができる。
【００９１】
例えば、誤差ｅが正で、累積回数Ｍ＝Ｐ−４、即ち、１回目の観測期間中に補正タイミングが発生する場合の例を図に基づいて説明する。
【００９２】
図７は、初回の観測期間のサンプリング開始タイミング（強制同期タイミング）からの動作を示すものであり、図７の（ａ）に示す理想周期Ｔｓｒのサンプリング信号の出力タイミングに対して、実際のサンプリング信号の出力タイミングは図７（ｂ）に示すように誤差ｅの累積分ずつ進んでゆく。なお、図７はサンプリング信号の出力間隔のうちのＮ・Ｔｘ分を省略して表したものであり、理想周期の場合をΔＴ、実際の周期の場合をΔＴｅとする。
【００９３】
図７の（ｂ）のようにサンプリング信号が出力される前に、図７の（ｃ）のように制御部３３の制御によって第２のゲート回路３２がオン状態、図７の（ｆ）のように第１のゲート回路３３がオン状態となり、信号発生器２５から出力されるサンプリング信号は図７の（ｇ）のようにサンプリング部２１に入力されて、データ信号Ｘに対するサンプリングが順次行なわれる。
【００９４】
そして、サンプリング信号の累積誤差Ｅは、Ｐ−４（＝Ｍ）回目のサンプリングが行なわれるタイミングに観測分解能ΔＴに等しくなるか越えるが、制御部３３の制御によってＰ−５（＝Ｍ−１）回目のサンプリングが行なわれた直後に図７の（ｃ）のように、第２のゲート回路３２がオフ状態になる。
【００９５】
このため、信号発生器２５からＰ−４回目に出力されたサンプリング信号は、図７の（ｄ）のように、カウンタ３０およびサンプリング部２１に入力されず、カウンタ３０の計数値も図７の（ｅ）のようにＰ−５のままとなる。
【００９６】
そして、信号発生器２５からＰ−４回目のサンプリング信号が出力された直後に、第２のゲート回路３２がオン状態に戻るので、信号発生器２５からＰ−３回目のサンプリング信号が出力されたときに、データ信号Ｘに対するサンプリングが再開され、カウンタ３０が１つ歩進してその計数値ＣｓがＰ−４となる。
【００９７】
このタイミングは、理想周期ＴｓｒによるＰ−４回目のサンプリングタイミングとほぼ一致するので、累積誤差Ｅはほぼキャンセルされる。
【００９８】
以後は、この状態のままサンプリングが行なわれ、カウンタ３０の計数値ＣｓがＡ（１）−Ｐ−１に達して、Ｐ回のサンプリングによるデータが得られると、第１のゲート回路３１がオフ状態となってサンプリングが停止し、カウンタ３０の計数値Ｃｓが次の観測期間のサンプリング開始タイミングになるまで待機する。
【００９９】
上記の補正動作は、初回の観測期間中のものであったが、２回目以降の観測期間や観測期間と次の観測期間との間の待機期間の場合も同様であり、カウンタ３０がＭ−１（Ｍの近傍であればよい）回歩進する毎に行なわれて、累積誤差がキャンセルされるので、サンプリングタイミングおよび各観測期間のサンプリング開始タイミングのずれは、常に観測分解能ΔＴ以内に収まり、データ信号Ｘのビット周期に対してΔＴが十分小さければ、ΔＴ分の誤差による表示波形のずれは無視できる。
【０１００】
このため、データ信号自体のジッタによる時間軸の波形変動を、フレーム同期信号Ｆのジッタ成分の影響を受けることなく、正確に把握できる。
【０１０１】
一方、誤差ｅが負の場合には、図４に示しているように、累積回数Ｍを、ΔＴ／｜ｅ｜が整数の場合に、
Ｍ＝（ΔＴ／｜ｅ｜）
の演算で求め、ΔＴ／｜ｅ｜が小数の場合に、その商Ｇに対して、
Ｍ＝Ｇ＋１
の演算で求める（Ｓ４２）。
【０１０２】
そして、前記同様に変数ｉを１に初期化し、変数ｕを０に初期化して、一つのフレーム同期信号Ｆが入力したタイミングにサンプリング信号Ｓを強制的にフレーム同期信号Ｆに同期させ、カウンタ３０をリセットして、カウンタ３０の計数値Ｃｓを監視して、その計数値ＣｓがＡ（１）−１になるまで待機するが、その待機中に、信号発生器２５からＭ−１個のサンプリング信号Ｓが出力されて、カウンタ３０の計数値Ｃｓが（ｕ＋１）Ｍ−１−ｕ（この場合ｕ＝０）になると、制御部３３からのパルス信号が第２のゲート回路３２を介して挿入されて、カウンタ３０が強制的に１つ歩進され、変数ｕが１だけ増加更新される（Ｓ４３〜Ｓ５０）。
【０１０３】
このとき誤差ｅの累積値Ｅが、観測分解能ΔＴに等しい状態かあるいは僅かに越えた状態なので、上記のようにカウンタ３０にパルスを入力してその計数値をＭにすることで、信号発生器２５からＭ個目のサンプリング信号が入力されたときのタイミングを、理想周期Ｔｓｒで計数したときに計数値がＭ＋１となるタイミングに合わせることができ、累積誤差Ｅをキャンセルすることができる。
【０１０４】
この累積誤差の補正は、信号発生器２５からサンプリング信号ＳがＭ−１回出力される毎に行なわれ、カウンタ３０の計数値ＣｓがＡ（１）−１になると、第１のゲート回路３１がオン状態となり、次に信号発生器２５から出力されるサンプリング信号が、サンプリング部２１に入力されて、初回の観測期間のサンプリングが開始される（Ｓ５１）。
【０１０５】
この観測期間中、即ち、カウンタ３０の計数値ＣｓがＡ（ｉ）＋Ｐ−１に達する前に、カウンタ３０がＭ−１回歩進して計数値Ｃｓが（ｕ＋１）Ｍ−１−ｕに等しくなると、制御部３３は、第１のゲート回路３１を一時的にオフ状態にして前記同様に累積誤差の補正のためにパルスを第２のゲート回路３２を介して入力してカウンタ３０を１つ歩進させるとともに、表示制御手段２２に対してデータの追加を指示し、変数ｕを１だけ増加するという処理を繰り返す（Ｓ５２〜Ｓ５５）。
【０１０６】
このデータの追加指示を受けた表示制御手段２２は、その前にサンプリング部２１から出力されたデータと同一のデータを、新たなにサンプリングされたデータとして記憶する。
【０１０７】
このような処理を行なっている間にデータ信号に対するＰ回のサンプリングが行なわれて、計数値ＣｓがＡ（ｉ）＋Ｐ−１に達すると、第１のゲート回路３１をオフ状態にしてサンプリングを停止させ、変数ｉが最終値Ｑか否かを確認する（Ｓ５６、Ｓ５７）。
【０１０８】
単発観測モードの場合ここでサンプリングが終了して、得られたＰ個のデータに基づいて波形が表示される。
【０１０９】
また、繰り返し観測モードのときには、変数ｉを１だけ増加させて、カウンタ３０の計数値Ｃｓが次の観測期間のサンプリングタイミングを示す値Ａ（ｉ）の直前の値Ａ（ｉ）−１となるまで待機するが、この待機中に前記同様に計数値Ｃｓが（ｕ＋１）Ｍ−１−ｕに達すると、前記した処理Ｓ４７〜Ｓ４９と同様の処理がなされ、制御部３３による強制歩進が行なわれる（Ｓ５８〜Ｓ６２）。
【０１１０】
そして、計数値Ｃｓが次の観測期間の開始タイミングの直前を表す値Ａ（ｉ）−１になると、第１のゲート回路３１がオン状態となり、次の観測期間のサンプリングが開始されて、処理Ｓ５２に戻る（Ｓ６３）。
【０１１１】
以下、同様の処理が繰り返されてＱ回の観測期間のサンプリングが行なわれ、そのＱ回の観測期間のサンプリングで得られた波形データが同一時間軸上で重ね合わせ表示される。
【０１１２】
このように誤差ｅが負の場合に、上記のように、累積誤差が観測分解能ΔＴに等しくなるか越える毎にカウンタ３０を強制歩進し、観測期間であれば、データわ追加させることで、カウンタ３０の計数値が示すタイミング（つまり時間軸）とサンプリングされるデータとが対応するように補正される。
【０１１３】
例えば、誤差ｅが負で前記同様に累積回数Ｍ＝Ｐ−４、即ち、１回目の観測期間中に補正タイミングが発生する場合を図で説明する。
【０１１４】
図８の（ａ）に示す理想周期Ｔｓｒのサンプリング信号の出力タイミングに対して、実際のサンプリング信号の出力タイミングは図８（ｂ）に示すように誤差ｅの累積分ずつ遅れてゆく。なお、図８は前記同様にサンプリング信号の出力間隔のうちのＮ・Ｔｘ分を省略して表したものであり、理想周期の場合をΔＴ、実際の周期の場合をΔＴｅとする。
【０１１５】
図８の（ｂ）のようにサンプリング信号が出力される前には、制御部３３の制御によって、図８の（ｆ）のように、第１のゲート回路３１がオン状態となり、信号発生器２５から出力されるサンプリング信号は図８の（ｇ）のようにサンプリング部２１に入力されて、データ信号Ｘに対するサンプリングが順次行なわれる。
【０１１６】
そして、サンプリング信号の累積誤差Ｅは、Ｐ−４（＝Ｍ）回目のサンプリングが行なわれるタイミングに観測分解能ΔＴに等しくなるか越えるが、制御部３３の制御によってＰ−５（＝Ｍ−１）回目のサンプリングが行なわれた直後に、図８の（ｆ）のように第１のゲート回路３１が一時的にオフ状態となり、その間に、図８の（ｃ）のように、パルスが第２のゲート回路３２を介して挿入され、表示制御手段２２に対してデータの追加指示がなされる。
【０１１７】
このパルスの挿入により、カウンタ３０が１つ歩進してその計数値Ｃｓは図８の（ｅ）のようにＰ−４となる。
【０１１８】
そして、信号発生器２５からＰ−４回目のサンプリング信号が出力されると、カウンタ３０の計数値Ｃｓが１だけ歩進してＰ−３となる。
【０１１９】
このタイミングは、理想周期ＴｓｒによるＰ−３回目のサンプリングタイミングとほぼ一致するので、累積誤差Ｅはほぼキャンセルされる。
【０１２０】
以後は、この状態のままサンプリングが行なわれ、カウンタ３０の計数値ＣｓがＡ（１）−Ｐ−１に達して、Ｐ回のサンプリングによるデータが得られると、第１のゲート回路３１がオフ状態となってサンプリングが停止し、カウンタ３０の計数値Ｃｓが次の観測期間のサンプリング開始タイミングになるまで待機する。
【０１２１】
なお、図９の（ａ）に示すように、Ｐ−５回目のサンプリングが行なわれた直後に制御部３３からデータの追加指示を受けた表示制御手段２２は、図９の（ｂ）のように、サンプリング部２１からＰ−５回目に出力されたデータＤｓ（Ｐ−５）を内部のメモリに記憶してから、それと同一のデータを次のデータとしてメモリに記憶して、カウンタ３０の計数値Ｃｓとデータ数とを対応させる。
【０１２２】
上記の補正処理は、初回の観測期間中のものであったが、２回目以降の観測期間および観測期間と次の観測期間との間の待機期間の場合も同様であり、カウンタ３０がＭ−１（Ｍの近傍であれはよい）回歩進する毎に行なわれて、累積誤差がキャンセルされるので、各サンプリングタイミングおよび各観測期間のサンプリング開始タイミングのずれは、観測分解能ΔＴ以内に収まり、データ信号Ｘのビット周期に対してΔＴが十分小さければ、ΔＴ分の誤差による表示波形のずれは無視できる。
【０１２３】
前記説明では、フレーム同期信号Ｆにサンプリング信号Ｓを強制同期し、そのタイミングを基準にして、各観測期間のサンプリング開始タイミングを求めていたが、強制同期をおこなわずに、サンプリング信号の出力タイミングとフレーム同期信号Ｆの入力タイミングとから、指定された観測開始ビット位置ｊがサンプリング部２１に入力されるタイミングと、信号発生器２５がサンプリング信号Ｓを出力するタイミングとが最初に一致するまでのサンプリング信号の出力回数を求めてもよい。
【０１２４】
例えば、図１０の（ａ）に示すように、時刻ｔ１にフレーム同期信号Ｆが入力されたとすると、図１０の（ｂ）のように、時刻ｔ１から（ｊ−１）／Ｂが経過する時刻ｔ３に観測開始ビット位置ｊのデータ信号が入力されることになるが、その間の時刻ｔ２に図１０の（ｃ）のようにサンプリング信号Ｓが出力されたとすると、サンプリング信号Ｓの出力タイミングと観測開始ビット位置ｊのデータ信号が入力されるタイミングとの差Ｔｄはｔ３−ｔ２となる。
【０１２５】
サンプリング信号Ｓの出力タイミングはデータ信号がＮフレーム入力される毎にΔＴだけずれるので、この差時間Ｔｄを観測分解能ΔＴで除算して得られる値Ａに等しい回数だけサンプリング信号が出力されたときにちょうど観測開始ビット位置ｊのデータがサンプリング部２１に入力されることになる。
【０１２６】
つまり、上記差時間Ｔｄを求めて、その時間差Ｔｄを観測分解能ΔＴで除算して、観測期間に対するサンプリング開始タイミングまでのサンプリング信号の出力回数Ａを求め、カウンタ３０がＡ回歩進したときを最初の観測期間に対するサンプリング開始タイミングとすることができる。
【０１２７】
なお、図９の（ｃ）の点線で示しているように、フレーム同期信号Ｆとそのフレームの観測開始ビット位置ｊの間にサンプリング信号Ｓの出力タイミングがこない場合には、差時間ＴｄをＴｘ−｜ｔ３−ｔ２｜で求めればよい。
【０１２８】
この開始タイミングの判別は、フレーム同期信号Ｆが入力された時点（ｔ１）から最初のサンプリング信号Ｓが出力されたタイミングを基準にしてカウンタ３０の歩進回数を監視することで行なうが、前記したように、設定誤差がある場合、サンプリング開始タイミングがくる前に累積回数Ｍに達したときには、前記した補正処理を行なう。
【０１２９】
また、前記した例では、設定誤差の補正を、サンプリング信号に対する処理で行なっていたが、設定誤差の補正をサンプリング部２１から表示制御手段２２へのデータの出力に対する処理で行なうこともできる。
【０１３０】
例えば、図１１に示す波形観測装置２０′のように、第２のゲート回路３２の代わりに、サンプリング部２１から表示制御手段２２に対するデータＤｓの出力を制御するデータ出力制御手段３５を設ける。
【０１３１】
そして、誤差ｅが正のとき、補正タイミングが観測期間内にある場合に制御部３３からの指示を受けたデータ出力制御手段３５が、補正タイミングにサンプリングで得られたデータの表示制御手段２２への出力を規制（破棄）する。
【０１３２】
ただし、この場合には、破棄したデータの分もカウンタ３０が歩進するので、その観測期間のサンプリング終了タイミングを破棄したデータの数だけ遅らせる。なお、観測期間でない場合には、補正タイミングになる毎に次の観測期間のサンプリング開始タイミングの値Ａ（ｉ）を１ずつ増加補正する。
【０１３３】
また、誤差ｅが負のとき、補正タイミングが観測期間内にある場合に制御部３３からの指示を受けたデータ出力制御手段３５が、補正タイミングにサンプリングで得られたデータを２回連続して表示制御手段２２へ出力する。
【０１３４】
ただし、この場合には、１回よけいに出力したデータの分に対するカウンタ３０の歩進がなされないので、その観測期間のサンプリング終了タイミングを追加したデータの数だけ早める。なお、観測期間でない場合には、補正タイミングになる毎に次の観測期間のサンプリング開始タイミングの値Ａ（ｉ）を１ずつ減少補正する。
【０１３５】
また、前記した波形観測装置２０では、第１のゲート回路３１によってサンプリング部２１に対するサンプリング信号の入力を規制していたが、前記した波形観測装置２０′のようにサンプリング部２１でサンプリングされたデータの表示制御手段２２に対する出力を制御できるように構成した場合には、第１のゲート回路３１も省略して、信号発生器２５から出力されたサンプリング信号Ｓ観測期間と無関係にサンプリング部２１に常時入力して、制御部３３とデータ出力制御手段３５とによって、サンプリング部２１から出力されるデータのうち、観測期間の間に出力されたものだけを表示制御手段２２へ出力するように制御してもよい。
【０１３６】
また、上記説明では、繰り返し観測モードのときに２回目以降の観測期間のサンプリング開始タイミングを示す値Ａ（２）〜Ａ（Ｑ）を全て求めてからサンプリングを開始させていたが、始めに前記した観測期間の間隔を表す値Ｖのみを求めて、観測期間のサンプリングを開始し、その観測期間の間（あるいはその観測期間が終了した直後）に、次の観測期間の開始タイミングを前記Ｖに基づいて求め、その演算で求めた値とカウンタ３０の歩進回数とを比較して、次の観測期間のサンプリングを開始してもよい。
【０１３７】
また、前記説明では、フレーム同期信号Ｆとサンプリング信号Ｓとを同期させた時点から最後の観測期間の終了までカウンタ３０による計数動作を継続させているが、このように長い時間の計数を連続的に行なうためにはカウンタ３０の桁数が膨大となり、その桁上がりの遅延時間が無視できない場合がある。
【０１３８】
これはカウンタ３０を適当なタイミングでリセットしながら計数継続することで解決することができる。
【０１３９】
その場合には、リセットする直前の計数値を制御部３３がメモリに記憶しておき、その記憶値とカウンタ３０の計数値とを加算して、その加算結果で、観測期間の終了や開始のタイミングあるいは補正タイミングを判定すればよい。
【０１４０】
なお、このリセットタイミングは任意であるが、前記した補正タイミングや、各観測期間の直前、直後等に行うことができ、このようにカウンタ３０のリセットを行いながら、サンプリング信号の計数を継続することで、カウンタ３０として桁数の少ない高速なものが使用でき、カウンタ３０の動作速度の遅れによるタイミングの誤差も少なくすることができる。
【０１４１】
また、カウンタ３０のキャリー信号の出力回数を制御部３３で計数して、その出力回数にカウンタ３０の計数上限値を乗じた結果と、カウンタ３０の計数値とを加算して、その加算結果で観測期間の終了や開始のタイミングや補正タイミングの判定を行なってもよい。
【０１４２】
また、前記実施形態では観測開始位置をビット単位で指定する場合について説明したが、これは本発明を限定するものでなく、時間単位で指定してもよい。
【０１４３】
また、前記実施形態では、データ信号Ｘが電気信号の場合について説明したが、データ信号Ｘが光信号の場合でも本発明を同様に適用できる。
【０１４４】
ただし、光のデータ信号Ｘをサンプリングする方式として、データ信号Ｘを電気信号に変換してからＡ／Ｄ変換によりサンプリングしてディジタルのデータに変換する第１の方式、データ信号Ｘを電気のパルス信号でスイッチングしてサンプリングし、そのサンプリングで得られた光パルス信号を電気のパルス信号に変換して、そのピーク値をディジタルのデータに変換する第２の方式、データ信号Ｘを光パルスでサンプリングし、そのサンプリングで得られた光パルス信号を電気のパルス信号に変換して、そのピーク値をディジタルのデータに変換する第３の方式とがあり、そのいずれを用いてもよい。
【０１４５】
前記第１の方式の場合、例えば図１２に示すサンプリング部２１のように、データ信号Ｘを光電変換器２１ａによって電気の信号Ｅｘに変換してＡ／Ｄ変換器２１ｂに入力し、Ａ／Ｄ変換器２１ｂにサンプリング信号Ｓを与えて、ディジタルのデータＤｓ値に変換して表示制御手段２２に出力する。
【０１４６】
また、第２の方式の場合、図１３に示すサンプリング部２１のように、データ信号Ｘを高速な光スイッチ２１ｃに入力し、サンプリング信号Ｓを受けたパルス発生器２１ｄからサンプリング信号Ｓと等しい周期Ｔｓで出力される幅の狭い電気のパルス信号Ｅｐで光スイッチ２１ｃをオンさせて、被測定信号Ｘをサンプリングし、その光スイッチ２１ｃから出力される光パルス信号Ｐｓを光電変換器２１ａで電気信号Ｅｓに変換し、そのピーク値をＡ／Ｄ変換器２１ｂによってディジタルのデータＤｓに変換して出力する。
【０１４７】
また、第３の方式の場合、例えば図１４に示サンプリング部２１のように、サンプリング信号Ｓを受けた光パルス発生器２１ｅからサンプリング信号Ｓと等しい周期Ｔｓで出射される光パルスＰを、非線型光学結晶等からなる光サンプリング部２１ｆに入射してこの光パルスＰでデータ信号Ｘをサンプリングし、そのサンプリングで得られた光パルス信号Ｐｓを光電変換器２１ａによって電気のパルス信号Ｅｓに変換し、そのパルス信号Ｅｓのピーク値をＡ／Ｄ変換器２１ｂでディジタルのデータＤｓ値に変換して出力するようにサンプリング部２１を構成する。
【０１４８】
なお、電気や光のパルスを用いてデータ信号Ｘのサンプリングを行う第２、第３の方式の場合、そのパルス幅が狭い程、分解能を高くすることができる。
【０１４９】
ここで、電気によるパルス変調で得られる信号（電気および光の信号）の幅は数ｐｓ程度が限界であるが、光パルスの場合には分散減少ファイバを通過させることでその幅を数１０分の１にすることができるので、前記したように０．１ｐｓのサンプリング分解能ΔＴを得ようとする場合には、前記した第３の方式を採用し、光パルス発生器２１ｅの内部で分散減少ファイバを用いてパルス幅の狭い光パルスＰを生成すればよい。
【０１５０】
【発明の効果】
以上説明したように、本発明の波形観測装置は、指定された各パラメータに基づいて、フレーム同期信号の周期の整数倍に対して観測分解能分の差をもつ周期のサンプリング信号を出力する信号発生器と、その信号発生器から出力されるサンプリング信号を計数する計数手段と、データ信号を信号発生器から出力されたサンプリング信号でサンプリングするサンプリング部と、そのサンプリング部から出力される信号に基づいて、データ信号の波形を表示する波形表示手段と、一つのフレーム同期信号が入力したタイミングまたはその直後に信号発生器から出力されるサンプリング信号の出力タイミングを基準タイミングとして、観測開始位置に対応するサンプリング開始タイミングを、ビットレート、観測開始位置および観測分解能に基づいてサンプリング信号の周期単位で求め、計数手段の基準タイミングからの歩進回数が、サンプリング開始タイミングに一致したときから所定回連続のサンプリングで得られたデータが１観測期間の波形データとして波形表示手段に送出されるように制御する制御手段とを備えている。
【０１５１】
このため、データ信号のフレーム内の任意の範囲の波形を観測することができる。
【０１５２】
また、制御手段が、観測期間に対する所定回のサンプリングを複数回繰り返し行なう動作モードが指定されたとき、最初の観測期間のサンプリング開始タイミングを求めたときに用いた基準タイミングを基準にして２回目以降の観測期間のサンプリング開始タイミングを、サンプリング信号の周期単位で求め、計数手段の基準タイミングからの歩進回数が各観測期間のサンプリング開始タイミングに一致したときから所定回までのサンプリングで得られたデータが各観測期間の波形データとして波形表示手段に出力されるように制御するように構成されている。
【０１５３】
このため、データ信号のフレーム内の任意の範囲の波形を繰り返し観測する場合に、フレーム同期信号のジッタの影響を受けずに、データ信号自体の波形を正確に観測することができる。
【０１５４】
また、制御手段が、データ信号のビットレートと観測分解能とからサンプリングの理想周期を算出する理想周期算出手段と、理想周期と信号発生器から実際に出力されるサンプリング信号の周期との誤差を求める誤差算出手段と、誤差を累積した値が観測分解能に等しいか越えるときの累積数を求める累積数算出手段と、信号発生器からサンプリング信号が累積数分出力される毎にカウンタの歩進の規制または追加歩進を行なう補正手段とを備えている。
【０１５５】
このため、装置の設定可能な桁数の制限等による誤差あっても、サンプリングタイミングの誤差を観測分解能以下に抑えることができ、誤差による表示波形のずれがなく、データ信号の波形を正確に把握できる。
【０１５６】
また、制御手段が、計数手段を所定タイミング毎に初期化し、その初期化後の計数手段の計数値と初期化する直前の計数値とに基づいて、計数手段の歩進回数を求めるように構成したものでは、少ない桁数の計数手段を用いることができ、より精度の高い観測が行なえる。
【図面の簡単な説明】
【図１】本発明の実施形態の構成を示すブロック図
【図２】実施形態の要部の処理手順を示すフローチャート
【図３】実施形態の要部の処理手順を示すフローチャート
【図４】実施形態の要部の処理手順を示すフローチャート
【図５】実施形態の動作を説明するためのタイミング図
【図６】観測波形の一例を示す図
【図７】実施形態の動作を説明するためのタイミング図
【図８】実施形態の動作を説明するためのタイミング図
【図９】実施形態の動作を説明するためのタイミング図
【図１０】他の動作例を説明するためのタイミング図
【図１１】他の実施形態の構成を示すブロック図
【図１２】実施形態の要部の構成例を示す図
【図１３】実施形態の要部の構成例を示す図
【図１４】実施形態の要部の構成例を示す図
【図１５】サンプリング方式の波形観測装置の動作を説明するためのタイミング図
【図１６】観測波形の一例を示す図
【符号の説明】
２０……波形観測装置、２１……サンプリング部、２２……表示制御手段、２３……表示器、２５……信号発生器、２６……パラメータ入力手段、３０……カウンタ、３１……第１のゲート回路、３２……第２のゲート回路、３３……制御部、３５……データ出力制御手段[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a waveform observation apparatus for observing the waveform of an electric or optical signal, and a high-speed data signal in which one frame is formed with a predetermined number of bits has a period close to an integral multiple of the frame period. In a waveform observation device that samples with a sampling signal and obtains and displays waveform information in an arbitrary range of the data signal based on the sampling result, the sampling start timing for the data signal can be set arbitrarily, and the set start The present invention relates to a technique for enabling resampling at timing.
[0002]
[Prior art]
Generally, as shown in FIG. 15A, a serial data signal is formed as one frame with a predetermined number of bits n (which may be fixed or variable), and is separated at the receiving side. Are often output together with a frame synchronization signal F as shown in FIG.
[0003]
In such a data signal X, the relationship between the output timing of the frame synchronization signal F and the bit of data in the frame (in the figure, the rising timing of the frame synchronization signal F and the output timing of the first bit of the data signal X match). If the bit rate B of the data signal X is known, the output timing of the data at the arbitrary bit position j in the frame is (j−1) / B from the rising timing of the frame synchronization signal F. It turns out that it is time.
[0004]
Therefore, for example, in order to observe the waveform of the data signal at an arbitrary bit position j for one bit, j / B has elapsed since time (j−1) / B has elapsed from the rising timing of the frame synchronization signal F. What is necessary is just to extract the waveform information in the period up to.
[0005]
When the waveform information is extracted by digital processing, the A / D converter may be used to sample the period with the sampling signal having a frequency several stages higher than the bit rate B of the data signal X. When the bit rate B is high (for example, 10 Gbps), the operation limit of the A / D converter is exceeded, and the above sampling cannot be performed.
[0006]
In order to solve this, as shown in FIG. 15C, there is a method of performing sampling by shifting the time by a little (ΔT) with respect to the rising timing of the frame synchronization signal F of each frame as a reference.
[0007]
In this sampling method, sampling may be performed at a cycle close to the cycle of the frame synchronization signal F or an integer multiple thereof (1 in the figure). For example, even if the data signal has a bit rate of 10 Gbps as described above, If the frequency is much lower, for example, if the number of bits in one frame is 1 Mbit, waveform information can be extracted using a sampling signal of approximately 10 kHz (= 10 Gbps / 1 Mbit).
[0008]
One criterion for observing and evaluating the waveform of a data signal is jitter (phase fluctuation). This jitter is obtained by performing the above observations a plurality of times and applying the waveform obtained in each observation to the same time. This can be grasped by overlaying on the axis.
[0009]
For example, when the jitter of the data signal is small, the rise and fall timing fluctuation of the waveform obtained in each observation is small, so the line thickness of the bit boundary portion of the superimposed waveform is as shown in FIG. When the waveform is thin as shown in (a) and there is a lot of jitter, the rise and fall timing fluctuations of the waveform obtained in each observation are large. Becomes thick as shown in FIG.
[0010]
Therefore, the magnitude of the jitter of the data signal can be grasped by looking at the thickness of the line at the bit boundary portion of the superimposed waveform.
[0011]
[Problems to be solved by the invention]
However, in the sampling method as described above, the sampling timing for the frame to be sampled is obtained with reference to the input timing of the frame synchronization signal F input corresponding to the frame. There is a problem that the jitter of the data signal X cannot be accurately grasped due to the influence.
[0012]
That is, generally, when there is jitter in the data signal X, there is also jitter in the frame synchronization signal F, but the correlation between the jitter of the data signal X and the jitter of the frame synchronization signal F is the same as that of the data signal X and frame synchronization. Depending on the internal configuration and internal state of the device that outputs the signal F, it does not always have a fixed relationship, and the data signal X jitter and the frame synchronization signal F jitter phase are also reversed. There may be.
[0013]
As described above, when the data signal of the frame is sampled with reference to the input timing of the frame synchronization signal F of the sampling target frame, the jitter of the data signal X and the jitter of the frame synchronization signal F are substantially equal. In this case, the jitter of the data signal is canceled by the jitter of the frame synchronization signal, and jitter less than the original jitter of the data signal is observed. Conversely, the phase of the jitter of the data signal X and the jitter of the frame synchronization signal F is almost equal. When inverted, the jitter of the frame sync signal is added to the jitter of the data signal in phase, and a jitter larger than the original jitter of the data signal is observed, so that the original jitter of the data signal can be accurately grasped. I can't.
[0014]
Further, the sampling method requires a complicated configuration in which the period from the reference timing to sampling is gradually changed by ΔT.
[0015]
In order to solve this problem, the input timing of the frame synchronization signal F is used only when the sampling start timing of the first observation period is obtained, and thereafter, a fixed period with reference to the input timing of the frame or the first sampling start timing The sampling timing of each sampling signal is obtained by calculation based on the bit rate B of the data signal X, the bit number n of one frame, the observation resolution ΔT, etc., and the data sampled at the obtained sampling timing is waveform data of the observation period. Can be obtained as.
[0016]
However, the bit rate B of the data signal X to be observed and the number of bits n of one frame vary depending on the type of the data signal X, and parameters necessary for dealing with these take various values. Since the number of digits of a numerical value that can be set in each part of is limited, there may be a case where the lower digit part (fractional part) of the numerical value obtained by calculation cannot be actually set.
[0017]
Since this setting error appears as a sampling timing error, if the sampling timing is calculated sequentially from one reference timing as described above, the error is accumulated and the sampling timing of each observation period becomes inconsistent. A new problem arises that the waveform of the period shifts on the time axis and is observed as if jitter occurred.
[0018]
If the bit rate B of the data signal X, the number of bits n in one frame, and the observation resolution ΔT are fixed, this error problem can be dealt with by finely adjusting the sampling signal cycle Ts accordingly. In order to enable observation of various data signals having different values, it is not possible to cope with the fine adjustment of the sampling frequency described above.
[0019]
The present invention solves these problems, and is capable of accurately observing the original signal waveform of the data signal without being affected by the frame synchronization signal, and without being affected by the parameter value or its setting error. The object is to provide a device.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, a waveform observation apparatus according to claim 1 of the present invention includes:
For receiving a serial data signal in which one frame is formed with a predetermined number of bits and a frame synchronization signal synchronized with the frame of the data signal, and observing a signal waveform in an arbitrary bit range in the frame of the data signal A waveform observation device,
Parameter designation means (26) for designating parameters of the bit rate, observation start position, and observation resolution of the data signal;
A signal generator (25) for outputting a sampling signal having a period having a difference corresponding to the observation resolution with respect to an integral multiple of the period of the frame synchronization signal, based on each designated parameter;
Counting means (31) for counting sampling signals output from the signal generator;
A sampling unit (21) for sampling the data signal with a sampling signal output from the signal generator;
Waveform display means (22, 23) for displaying the waveform of the data signal based on the signal output from the sampling unit;
The sampling start timing corresponding to the observation start position is set to the bit rate, with the timing at which one frame synchronization signal is input or the output timing of the sampling signal output from the signal generator immediately after the timing as a reference timing, Obtained in units of the sampling signal cycle based on the observation start position and the observation resolution, and the number of steps from the reference timing of the counting means was obtained by sampling a predetermined number of times from when the sampling start timing coincided with the sampling start timing And control means (31 to 33) for controlling the data to be sent to the waveform display means as waveform data for one observation period.
[0021]
The waveform observation apparatus according to claim 2 of the present invention is the waveform observation apparatus according to claim 1,
When the operation mode in which the predetermined sampling for the observation period is repeated a plurality of times is specified, the control means performs the second time based on the reference timing used when the sampling start timing of the first observation period is obtained. The sampling start timing of the subsequent observation period is obtained in the cycle unit of the sampling signal, and from the time when the number of steps from the reference timing of the counting means coincides with the sampling start timing of each observation period to the predetermined time Control is performed so that data obtained by sampling is output to the waveform display means as waveform data of each observation period.
[0022]
The waveform observation device according to claim 3 of the present invention is the waveform observation device according to claim 1 or 2,
The control means includes
Ideal period calculation means (S17) for calculating an ideal period of sampling from the bit rate of the data signal and the observation resolution;
Error calculation means (S18) for obtaining an error between the ideal period and the period of the sampling signal actually output from the signal generator;
A cumulative number calculating means (S20, S42) for obtaining a cumulative number when the accumulated value of the error is equal to or exceeds the observation resolution;
Correction means (S25 to S27, S30 to S32, S37 to S39, S47 to S49, each of which controls the step of the counting means or performs an additional step each time the sampling signal is output from the signal generator by the cumulative number. S52 to S54, S59 to S61).
[0023]
Moreover, the waveform observation apparatus of Claim 4 of this invention is a waveform observation apparatus in any one of Claims 1-3,
The control means initializes the counting means at every predetermined timing, and obtains the number of steps of the counting means based on the count value of the counting means after the initialization and the count value immediately before initialization. It is characterized by.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a waveform observation apparatus 20 to which the present invention is applied.
[0025]
The waveform observation apparatus 20 gives a reference signal R to the measurement target device 1 and receives a data signal X and a frame synchronization signal F output from the measurement target device 1, and designates an arbitrary specified in the frame of the data signal X. The signal waveform in the bit range can be observed.
[0026]
Here, it is assumed that the measurement target device 1 outputs a data signal X composed of n bits per frame with a bit period 1 / B equal to 1 / m of the period Tr of the input reference signal R. Also, a frame synchronization signal F synchronized with the first bit of this frame is output.
[0027]
The data signal X may be an electrical signal or an optical signal. Here, the case of the electrical signal will be described first for easy understanding of the invention, and the case of the optical signal will be described later.
[0028]
The waveform observation apparatus 20 receives the data signal X input from the input terminal 20a by the sampling unit 21.
[0029]
The sampling unit 21 includes an A / D converter, samples the data signal X by the sampling signal S of the frequency fs output from the first gate circuit 31 described later, and converts the sampling value into a digital value. Output.
[0030]
The sampling timing of the sampling unit 21 is assumed to be a level transition timing at the rising edge (or falling edge) of the sampling signal S.
[0031]
Data Ds sampled by the sampling unit 21 and converted into a digital value is sequentially input to the display control means 22.
[0032]
The display control means 22 constitutes the waveform display means of this embodiment together with the display 23, stores the data Ds output from the sampling unit 21 in an internal memory (not shown) in the order of addresses, and stores the time in the display 23. In addition to displaying orthogonal coordinates including an axis and an intensity axis, a waveform corresponding to the intensity is displayed on the stored series of data Ds on the orthogonal coordinates.
[0033]
The display control means 22 processes the data Ds stored in the memory according to a mode designated by an operation unit (not shown).
[0034]
For example, when the single-shot observation mode is designated, a predetermined number of data Ds output from the sampling unit 21 is stored in a predetermined area of the memory in the order of addresses, and then the data Ds is read and output to the display unit 23. Waveforms are displayed on the aforementioned orthogonal coordinates.
[0035]
When the continuous observation mode is designated, a predetermined number of data Ds output from the sampling unit 21 in a certain observation period is stored in a predetermined area of the memory in the order of addresses, and the data Ds output in the next observation period is stored. Are stored in the other area of the memory in the order of addresses for the designated number of observation periods, and these data are read out and displayed on the display unit 23 on the same time axis.
[0036]
The number of times of sampling within each observation period is determined by the designated bit range and the observation resolution ΔT, and the upper limit is limited by the capacity of the memory for storing the data obtained by sampling.
[0037]
The signal generator 25 generates a sampling signal S and a reference signal R based on data set by the control unit 33 to be described later, and outputs the sampling signal S to the sampling unit 21 via the gate circuit 31. R is output to the measurement target device 1 via the output terminal 20c.
[0038]
The parameter input means 26 is used for inputting parameters necessary for sampling by an operation unit (not shown). For example, the observation mode, the bit rate B of the data signal X, the number of bits constituting one frame, the observation resolution ( Sampling resolution) ΔT, observation start bit position j, sampling number P (or observation end bit position) for each observation period, observation period number Q, and the like are input.
[0039]
The counter 30 constitutes the counting means of this embodiment. The counter 30 receives the sampling signal S output from the signal generator 25 via a second gate circuit 32 described later and counts the count value Cs. Is output to the control unit 33.
[0040]
The first gate circuit 31 constitutes the control means of this embodiment together with the second gate circuit 32 and the control unit 33, and the input of the sampling signal S to the sampling unit 21 is regulated by the control of the control unit 33. To do.
[0041]
The second gate circuit 32 regulates the output of the sampling signal S from the signal generator 25 to the counter 30 and the first gate circuit 31 under the control of the control unit 33, and outputs the pulse from the control unit 33. Insert and advance counter 30.
[0042]
The control unit 33 obtains the frequencies of the reference signal R and the sampling signal S output from the signal generator 25 based on the parameters input from the parameter input unit 26 and sets the corresponding frequency data in the signal generator 25. In addition, the sampling start timing of each observation period with respect to the timing when one frame synchronization signal F is input from the input terminal 20b is obtained in sampling cycle units, and sampling is started at the obtained sampling start timing. While monitoring the count value of the counter 30, the first gate circuit 31 and the second gate circuit 32 are controlled.
[0043]
2 to 4 are flowcharts showing the processing procedure of the control unit 33. Hereinafter, the operation of the waveform observation apparatus 20 according to the embodiment will be described based on these flowcharts.
[0044]
First, when a parameter for the observation target data signal X is input from the parameter input means 26 and an observation mode is instructed, the control unit 33 turns off the first gate circuit 31 and sets the second gate. After the circuit 32 is initially set to the ON state, the frequency fs of the sampling signal S and the frequency fr of the reference signal R are set based on the bit rate B of the input data signal X, the number of bits n of one frame, and the observation resolution ΔT. The frequency data of the sampling signal S and the reference signal R is set in the signal generator 25 (S1, S2).
[0045]
Here, the frequency fr of the reference signal R is obtained by calculating 1 / m of the bit rate B.
[0046]
The sampling frequency fs is obtained by the following calculation.
That is, the frame period Tx of the data signal X is n / B. If sampling is performed with a shift of ΔT every time the data signal X is input for N frames, the period Ts of the sampling signal is
Ts = N · Tx + ΔT
Therefore, if the sampling frequency fs is fx = 1 / Tx = B / n,
fs = fx / (N + fx · ΔT)
It becomes.
[0047]
If N is determined by the above equation, the sampling frequency fs can be obtained.
The value of N is limited by the frequency variable range of the sampling signal S of the signal generator 25.
[0048]
As numerical examples, B = 10 Gbps, n = 1 Mbit, ΔT = 0.1 ps, the upper limit of the frequency range of the sampling signal S that can be output by the signal generator 25 is fsa = 11 kHz + 1 Hz, and the lower limit is fsb = 1 kHz−1 Hz.
[0049]
Within this range,
fs = fx / (N + fx · ΔT)
When N is satisfied,
fx (1 / fsa−ΔT) ≦ N ≦ fx (1 / fsb−ΔT)
(B / n) (1 / fsa−ΔT) ≦ N ≦ (B / n) (1 / fsb−ΔT)
9.989999 …… ≦ N ≦ 10.01000 ……
And 10 is used as N.
[0050]
If N = 10,

Thus, if sampling is performed with the sampling signal S of this frequency fs, sampling can be performed with a delay of 0.1 ps (= ΔT) every 10 (= N) frames of the data signal X.
[0051]
The sampling frequency fs is generated by, for example, generating a signal of 10 GHz inside the signal generator 25, dividing it by a frequency divider to 1/10000000001, and multiplying the divided output by 10,000 by a multiplier. Can be obtained.
[0052]
Next, the control unit 33 calculates the sampling start timing for each observation period in units of sampling periods based on the input parameters (S3).
[0053]
The sampling start timing for each observation period is obtained on the basis of one frame synchronization signal F input from the input terminal 20b.
[0054]
That is, the frame synchronization signal F input from the input terminal 20b and the sampling signal S output from the signal generator 25 are asynchronous and have different periods, but here, as shown in FIG. Forcibly synchronizing the signal generator 25 to output the sampling signal S as shown in (c) of FIG.
[0055]
If this forced synchronization timing is set as a reference timing, as shown in FIG. 5B, an arbitrary observation start bit position j in the frame of the data signal X has (j−1) / B elapsed from the reference timing. It is understood that it is the timing.
[0056]
Since the cycle Ts of the sampling signal S is shifted by ΔT every N frames of the data signal, the time (j−1) / B is divided by ΔT, so that the output timing of the sampling signal S becomes the observation start bit position j. The number of sampling signal outputs A (1) until that time can be obtained, and the number of times A (1) is the sampling start timing of the first observation period.
[0057]
Since the time from the reference timing to the input of the signal at the observation start bit position j is constant (j−1) / B, the sampling start timing A (1) obtained by dividing this by the observation resolution ΔT. ) Is also constant, and can be obtained in advance when the parameter is designated.
[0058]
Next, when there are a plurality of observation periods, the sampling start timings for the second and subsequent observation periods are obtained as follows.
[0059]
In other words, in order for the sampling start timing of each observation period after the second to be sampled from the same position as the sampling start timing of the first observation period, the sampling start timing of the previous observation period and the sampling start of the next observation period The interval with the timing needs to be a value obtained by multiplying the cycle Ts of the sampling signal by an integer V greater than P and an integer U times the frame cycle Tx of the data signal X.
[0060]
That means
V ・ Ts = U ・ Tx
Since the periods Ts and Tx are known,
Ts / Tx = U / V
Among the combinations of integers V and U satisfying the above, the smallest V greater than P is obtained.
[0061]
In numerical examples, as described above, fx = B / n = 10 kHz, and the frequency fs of the sampling signal S is
fs = 10 × 10 ³ /(10.0000000001)Hz
given that,
Ts / Tx = fx / fs = 10.000000001 = U / V
It becomes.
[0062]
Here, if the sampling number P in each observation period is 1024, for example,

The minimum value of V is 2000000000 = 2 × 10 ⁹ It becomes.
[0063]
Therefore, from the sampling start timing A (1) in the first observation period to (2 × 10 ⁹ ). Sampling for the next observation period may be started at the timing when Ts has elapsed, and if this is represented by the count value of the counter 30 (the initial value at the sampling start timing of the first observation period is 0), 2 The start timing of the second observation period is the count value Cs = A (2) = A (1) + (2 × 10 ⁹ ) And the start timing of the third observation period is the count value Cs = A (3) = A (1) + (4 × 10 ⁹ Similarly, the start timing of the i-th observation period is the count value Cs = A (i) = A (1) + [(i−1) × 2 × 10 ⁹ ], And the start timing of the last Q-th observation period is the count value Cs = A (Q) = A (1) + [(Q−1) × 2 × 10 ⁹ ].
[0064]
By performing the above calculation, the sampling start timings A (1) to A (Q) of each observation period are obtained for each cycle of the sampling signal S and stored in a memory (not shown).
[0065]
It should be noted that when all the effective values lower than the ideal value such as the frequency obtained by the calculation in the processing S2 can be set in the signal generator 25, no setting error occurs, but the frequency obtained by the calculation or the like does not occur. When all the valid values lower than the ideal value cannot be set in the signal generator 25 and the lower valid values that cannot be set are discarded, a setting error occurs, and the setting error causes an error in sampling timing.
[0066]
Therefore, it is determined whether or not there is a setting error. If there is no setting error, the variable i representing the observation period is initialized to 1, and the timing at which one frame synchronization signal F is input as described above. The sampling signal S is forcibly synchronized with the frame synchronization signal F, and the counter 30 is reset (S4 to S8).
[0067]
Then, the count value Cs of the counter 30 is monitored, and immediately after the count value Cs becomes A (i) −1, the first gate circuit 31 is turned on, and the first sampling signal S is started from the next sampling signal S. Sampling of the observation period is started (S9, S10).
[0068]
When the sampling for the first observation period is performed P times and the count value Cs of the counter 30 becomes A (i) + P−1, the control unit 33 turns off the first gate circuit 31 and sets the sampling unit. 21 is stopped, and it is confirmed whether or not the variable i indicating the observation period is the final value Q (S11 to S13).
[0069]
Here, in the single observation mode, Q = 1 and the final value is reached, so the measurement ends. However, in the case of the repeated observation mode, the variable i is incremented by 1 to correspond to the variable i. The sampling start timing A (i) of the next observation period to be read is read and waited until the count value Cs of the counter 30 reaches A (i) -1 (S14, S15).
[0070]
When the count value Cs of the counter 30 reaches A (i) −1, the first gate circuit 31 is returned to the on state so that the next sampling signal is input to the sampling unit 21, and the next Sampling of the observation period is started, and the process returns to the process S11 (S16).
[0071]
Thereafter, the same processing is performed while increasing the variable i by 1 until reaching Q, and sampling of Q observation periods is completed.
[0072]
The data Ds sampled by the sampling unit 21 during each observation period is input to the display control means 22 and stored in the order corresponding to the input address in an area corresponding to each observation period in the internal memory, and the data is read out. Is output to the display 23 and displayed as a waveform.
[0073]
For example, when the single observation mode is performed on the data signal X in which the same data string is repeated in units of frames, the signal waveform from the j-th bit of the data signal is displayed as shown in FIG. The
[0074]
In addition, when the observation mode is repeatedly performed on the data signal X having a different data string for each frame, waveforms obtained in a plurality of observation periods are superimposed and displayed as shown in FIG. 6B. Therefore, it is possible to grasp the magnitude of the jitter of the data signal from the line thickness of the bit boundary portion of the superimposed waveform. In this case, since the data signal is sampled based on the input timing of one frame synchronization signal F, only the jitter component of the data signal itself can be accurately grasped without being affected by the jitter of the frame synchronization signal F itself. .
[0075]
On the other hand, if it is determined in step S4 that there is the setting error, as shown in FIG. 3, the reference frequency fr actually set in the signal generator 25, the multiplication number m of the target device 1, the numerical value N From the input observation resolution ΔT, the ideal period Tsr of the sampling signal accurately corresponding to the bit rate B of the actually input data signal X is
Tsr = N / (m · fr) + ΔT
(S17).
[0076]
Then, an error e of the period Ts of the sampling signal S actually output from the signal generator 25 with respect to the ideal period Tsr is expressed as follows:
e = Tsr-Ts
(S18).
[0077]
This error e is accumulated every time the sampling signal is output. Every time the accumulated value E becomes equal to or exceeds the observation resolution ΔT, the correspondence between the time axis and the sampling data is corrected, and sampling by error accumulation is performed. Timing deviation can be prevented. This correction operation is performed whenever the accumulated value E becomes equal to or exceeds the observation resolution ΔT regardless of the period, and whenever it occurs during the observation period, the correction operation is performed each time. What occurs during the observation period is sometimes performed together during the observation period, but here the former case will be described.
[0078]
Further, the error e may be positive or negative depending on the set parameter or the like. When the error is positive, that is, when the actual sampling period Ts is shorter than the ideal period Tsr, the error e Is negative, that is, when the actual sampling period Ts is longer than the ideal period Tsr, the correction method is different.
[0079]
Therefore, whether the error e is positive or negative is determined, and when the error e is positive, the cumulative number M indicating how many times the cumulative error E is equal to or exceeds the observation resolution ΔT when the error e is positive, and ΔT / e is an integer. ,
M = (ΔT / e)
When ΔT / e is a decimal, the quotient G is
M = G + 1
(S19, S20).
[0080]
Then, the variable i is initialized to 1, the variable u indicating the number of corrections is initialized to 0, and the sampling signal S is forcibly changed to the frame synchronization signal F at the timing when one frame synchronization signal F is input as described above. Synchronize, reset the counter 30, monitor the count value Cs of the counter 30, and wait until the count value Cs reaches A (i) −1. When one sampling signal S is output and the count value Cs of the counter 30 reaches (u + 1) M + u−1 (in this case u = 0), the control unit 33 causes the second gate circuit 32 to be in the sampling period Ts. The output is turned off, the output of the next (M-th) sampling signal to the counter 30 and the first gate circuit 31 is restricted, and the variable u is updated by 1 (S21 to S28).
[0081]
At this time, since the accumulated value E of the error e is equal to or slightly exceeds the observation resolution ΔT, by restricting the input of the Mth sampling signal to the counter 30 as described above, the M + 1th The timing when the sampling signal is input can be matched with the timing when the count value becomes M when counting with the ideal cycle Tsr, and the accumulated error E can be canceled.
[0082]
The accumulated error is corrected every time M−1 sampling signals S are output from the signal generator 25. When the count value Cs of the counter 30 becomes A (i) −1, the first gate circuit 31 is corrected. Is turned on, and the sampling signal output from the signal generator 25 is input to the sampling unit 21 and sampling of the first observation period is started (S29).
[0083]
During this observation period, that is, before the count value Cs of the counter 30 reaches A (i) + P−1, M−1 sampling signals S are output from the signal generator 25, and the count value Cs of the counter 30 is When equal to (u + 1) M + u−1, the second gate circuit 32 is turned off for one sampling period Ts to correct the accumulated error as described above, and the counter 30 and the first gate circuit for the next sampling signal S are set. The output to 31 is stopped, the step of the counter 30 and the sampling for the data signal are restricted only once, the second gate circuit 32 is returned to the ON state, and the variable u is increased by 1. Repeat (S30 to S33).
[0084]
During such processing, the data signal is sampled P times, and when the count value Cs reaches A (i) + P-1, the first gate circuit 31 is turned off to perform sampling. It is stopped and it is confirmed whether or not the variable i is the final value Q (S34, S35).
[0085]
In the case of the single observation mode described above, sampling is completed at this stage, and a waveform is displayed based on P pieces of data obtained by the sampling.
[0086]
In the repeated observation mode, the variable i is incremented by 1, and the count value Cs of the counter 30 is a value A (i) −1 immediately before the value A (i) indicating the sampling timing in the next observation period. However, if the count value Cs reaches (u + 1) M-1 + u in the same manner as described above, processing similar to the processing S30 to S32 described above is performed, and output of the sampling signal is regulated (S36 to S36). S40).
[0087]
Then, when the count value Cs becomes a value A (i) −1 representing immediately before the start timing of the next observation period, the first gate circuit 31 is turned on, sampling of the next observation period is started, and processing is performed. The process returns to S30 (S41).
[0088]
Thereafter, the same processing is repeated to perform sampling for Q observation periods, and the waveform data obtained by sampling for the Q observation periods are superimposed and displayed on the same time axis.
[0089]
In this way, when the error e is positive, the output of the sampling signal to the counter 30 and the sampling unit 21 is regulated every time the accumulated error becomes equal to or exceeds the observation resolution ΔT, thereby the timing indicated by the count value of the counter 30 ( That is, the time axis) is corrected so as to correspond to the sampled data.
[0090]
For this reason, the cumulative error E can be always suppressed within the range of the resolution ΔT without increasing the accumulated error E, and the error can be displayed so as not to include an error higher than the observation resolution ΔT with respect to the time axis.
[0091]
For example, an example in which the error e is positive and the cumulative number M = P−4, that is, the correction timing occurs during the first observation period will be described with reference to the drawings.
[0092]
FIG. 7 shows the operation from the sampling start timing (forced synchronization timing) in the first observation period. Actual sampling is performed with respect to the output timing of the sampling signal having the ideal period Tsr shown in FIG. As shown in FIG. 7B, the signal output timing advances by the accumulated error e. FIG. 7 shows the sampling signal output interval by omitting N · Tx, where ΔT is the ideal period and ΔTe is the actual period.
[0093]
Before the sampling signal is output as shown in (b) of FIG. 7, the second gate circuit 32 is turned on by the control of the control unit 33 as shown in (c) of FIG. As described above, the first gate circuit 33 is turned on, and the sampling signal output from the signal generator 25 is input to the sampling unit 21 as shown in FIG. 7G, and the data signal X is sequentially sampled. .
[0094]
The accumulated error E of the sampling signal becomes equal to or exceeds the observation resolution ΔT at the timing when the P-4 (= M) th sampling is performed, but P-5 (= M−1) is controlled by the control unit 33. Immediately after the second sampling, the second gate circuit 32 is turned off as shown in FIG.
[0095]
Therefore, the P-4th sampling signal output from the signal generator 25 is not input to the counter 30 and the sampling unit 21 as shown in FIG. 7D, and the count value of the counter 30 is also the same as that of FIG. It remains P-5 as in (e).
[0096]
Then, immediately after the P-4th sampling signal is output from the signal generator 25, the second gate circuit 32 returns to the ON state, so that the P-3th sampling signal is output from the signal generator 25. Sometimes, sampling for the data signal X is resumed, the counter 30 is incremented by one, and the count value Cs becomes P-4.
[0097]
Since this timing substantially coincides with the (P-4) th sampling timing based on the ideal period Tsr, the accumulated error E is almost canceled.
[0098]
Thereafter, sampling is performed in this state, and when the count value Cs of the counter 30 reaches A (1) -P-1, and data obtained by P times of sampling is obtained, the first gate circuit 31 is turned off. In this state, sampling is stopped, and the process waits until the count value Cs of the counter 30 reaches the sampling start timing of the next observation period.
[0099]
The above correction operation was performed during the first observation period, but the same applies to the second and subsequent observation periods and the standby period between the observation period and the next observation period. Since the accumulated error is canceled every time 1 (if it is in the vicinity of M) steps, the difference between the sampling timing and the sampling start timing in each observation period is always within the observation resolution ΔT. If ΔT is sufficiently small with respect to the bit period of the data signal X, a display waveform shift due to an error of ΔT can be ignored.
[0100]
Therefore, it is possible to accurately grasp the time-axis waveform fluctuation due to the jitter of the data signal itself without being affected by the jitter component of the frame synchronization signal F.
[0101]
On the other hand, when the error e is negative, as shown in FIG. 4, the cumulative number M is expressed as follows when ΔT / | e |
M = (ΔT / | e |)
When ΔT / | e | is a decimal,
M = G + 1
(S42).
[0102]
Similarly, the variable i is initialized to 1, the variable u is initialized to 0, and the sampling signal S is forcibly synchronized with the frame synchronization signal F at the timing when one frame synchronization signal F is input. Is reset, and the count value Cs of the counter 30 is monitored and waits until the count value Cs reaches A (1) −1. During the wait, M−1 samplings are performed from the signal generator 25. When the signal S is output and the count value Cs of the counter 30 becomes (u + 1) M-1-u (in this case, u = 0), the pulse signal from the control unit 33 is inserted through the second gate circuit 32. Thus, the counter 30 is forcibly incremented by 1, and the variable u is updated by 1 (S43 to S50).
[0103]
At this time, since the accumulated value E of the error e is equal to or slightly exceeds the observation resolution ΔT, a pulse is input to the counter 30 and the count value is set to M as described above, whereby the signal generator The timing when the 25th to Mth sampling signals are input can be matched with the timing at which the count value becomes M + 1 when counted in the ideal cycle Tsr, and the accumulated error E can be canceled.
[0104]
The accumulated error is corrected every time the sampling signal S is output from the signal generator 25 M−1 times. When the count value Cs of the counter 30 becomes A (1) −1, the first gate circuit 31 is corrected. Is turned on, and the sampling signal output from the signal generator 25 is input to the sampling unit 21 and sampling of the first observation period is started (S51).
[0105]
During this observation period, that is, before the count value Cs of the counter 30 reaches A (i) + P−1, the counter 30 advances by M−1 times and the count value Cs reaches (u + 1) M−1−u. When they are equal, the control unit 33 temporarily turns off the first gate circuit 31 and inputs a pulse through the second gate circuit 32 to correct the accumulated error in the same manner as described above. In addition, the process of instructing the display control unit 22 to add data and incrementing the variable u by 1 is repeated (S52 to S55).
[0106]
Upon receiving this data addition instruction, the display control means 22 stores the same data as the data previously output from the sampling unit 21 as newly sampled data.
[0107]
During such processing, the data signal is sampled P times, and when the count value Cs reaches A (i) + P-1, the first gate circuit 31 is turned off to perform sampling. It is stopped and it is confirmed whether or not the variable i is the final value Q (S56, S57).
[0108]
In the single observation mode, sampling is completed here, and a waveform is displayed based on the obtained P pieces of data.
[0109]
In the repeated observation mode, the variable i is incremented by 1, and the count value Cs of the counter 30 becomes the value A (i) -1 immediately before the value A (i) indicating the sampling timing in the next observation period. However, when the count value Cs reaches (u + 1) M-1-u in the same manner as described above, processing similar to the processing S47 to S49 described above is performed, and forced stepping by the control unit 33 is performed. (S58 to S62).
[0110]
Then, when the count value Cs becomes a value A (i) −1 representing immediately before the start timing of the next observation period, the first gate circuit 31 is turned on, sampling of the next observation period is started, and processing is performed. The process returns to S52 (S63).
[0111]
Thereafter, the same processing is repeated to perform sampling for Q observation periods, and the waveform data obtained by sampling for the Q observation periods are superimposed and displayed on the same time axis.
[0112]
As described above, when the error e is negative as described above, the counter 30 is forcibly incremented every time the accumulated error becomes equal to or exceeds the observation resolution ΔT. The timing (that is, the time axis) indicated by the count value of the counter 30 is corrected so as to correspond to the sampled data.
[0113]
For example, the case where the error e is negative and the cumulative number M = P−4, that is, the correction timing occurs during the first observation period, will be described with reference to the drawing.
[0114]
As compared with the output timing of the sampling signal having the ideal period Tsr shown in FIG. 8A, the actual output timing of the sampling signal is delayed by the accumulated error e as shown in FIG. 8B. FIG. 8 shows the output interval of the sampling signal by omitting N · Tx in the same manner as described above, where ΔT is the ideal period and ΔTe is the actual period.
[0115]
Before the sampling signal is output as shown in (b) of FIG. 8, the first gate circuit 31 is turned on as shown in (f) of FIG. The sampling signal output from 25 is input to the sampling unit 21 as shown in FIG. 8G, and sampling for the data signal X is sequentially performed.
[0116]
The accumulated error E of the sampling signal becomes equal to or exceeds the observation resolution ΔT at the timing when the P-4 (= M) th sampling is performed, but P-5 (= M−1) is controlled by the control unit 33. Immediately after the second sampling is performed, the first gate circuit 31 is temporarily turned off as shown in FIG. 8F, and during this time, the second pulse is supplied as shown in FIG. 8C. The data is inserted through the gate circuit 32 and the display control means 22 is instructed to add data.
[0117]
By inserting this pulse, the counter 30 is incremented by one and its count value Cs becomes P-4 as shown in FIG.
[0118]
When the P-4th sampling signal is output from the signal generator 25, the count value Cs of the counter 30 is incremented by 1 and becomes P-3.
[0119]
Since this timing substantially coincides with the (P-3) th sampling timing based on the ideal cycle Tsr, the accumulated error E is almost canceled.
[0120]
Thereafter, sampling is performed in this state, and when the count value Cs of the counter 30 reaches A (1) -P-1, and data obtained by P times of sampling is obtained, the first gate circuit 31 is turned off. In this state, sampling is stopped, and the process waits until the count value Cs of the counter 30 reaches the sampling start timing of the next observation period.
[0121]
As shown in FIG. 9A, the display control means 22 that receives an instruction to add data from the control unit 33 immediately after the P-5th sampling is performed is as shown in FIG. In addition, the data Ds (P-5) output from the sampling unit 21 for the P-5th time is stored in the internal memory, and then the same data is stored in the memory as the next data. The numerical value Cs is associated with the number of data.
[0122]
The above correction processing was performed during the first observation period, but the same applies to the second and subsequent observation periods and the standby period between the observation period and the next observation period. Since the accumulated error is canceled every time 1 step (may be in the vicinity of M) is performed, the deviation of the sampling start timing and the sampling start timing of each observation period is within the observation resolution ΔT. If ΔT is sufficiently small with respect to the bit period of the data signal X, a display waveform shift due to an error of ΔT can be ignored.
[0123]
In the above description, the sampling signal S is forcibly synchronized with the frame synchronization signal F, and the sampling start timing for each observation period is obtained with reference to the timing. However, the sampling signal output timing and Sampling until the timing at which the designated observation start bit position j is input to the sampling unit 21 and the timing at which the signal generator 25 outputs the sampling signal S first coincide with the input timing of the frame synchronization signal F The number of signal outputs may be obtained.
[0124]
For example, as shown in FIG. 10A, if the frame synchronization signal F is input at time t1, the time when (j−1) / B elapses from time t1 as shown in FIG. 10B. The data signal at the observation start bit position j is input at t3. If the sampling signal S is output as shown in FIG. 10C at time t2 during that time, the output timing of the sampling signal S and the observation The difference Td from the timing at which the data signal at the start bit position j is input is t3−t2.
[0125]
Since the output timing of the sampling signal S is shifted by ΔT every time N frames of data signals are input, the sampling signal is output a number of times equal to the value A obtained by dividing the difference time Td by the observation resolution ΔT. The data at the observation start bit position j is just input to the sampling unit 21.
[0126]
That is, the difference time Td is obtained, and the time difference Td is divided by the observation resolution ΔT to obtain the number A of sampling signal outputs up to the sampling start timing for the observation period. Sampling start timing for the observation period.
[0127]
As shown by the dotted line in FIG. 9C, when the output timing of the sampling signal S does not come between the frame synchronization signal F and the observation start bit position j of the frame, the difference time Td is set to Tx. -| T3-t2 |
[0128]
The determination of the start timing is performed by monitoring the number of steps of the counter 30 with reference to the timing at which the first sampling signal S is output from the time (t1) when the frame synchronization signal F is input. Thus, when there is a setting error, the correction process described above is performed when the cumulative number M is reached before the sampling start timing comes.
[0129]
In the above-described example, the setting error is corrected by processing the sampling signal. However, the setting error can be corrected by processing data output from the sampling unit 21 to the display control unit 22.
[0130]
For example, as in the waveform observation device 20 ′ shown in FIG. 11, instead of the second gate circuit 32, data output control means 35 for controlling the output of data Ds from the sampling unit 21 to the display control means 22 is provided.
[0131]
When the error e is positive, when the correction timing is within the observation period, the data output control means 35 that has received an instruction from the control unit 33 goes to the display control means 22 for the data obtained by sampling at the correction timing. Is regulated (discarded).
[0132]
However, in this case, since the counter 30 is incremented by the amount of discarded data, the sampling end timing of the observation period is delayed by the number of discarded data. If it is not the observation period, the value A (i) of the sampling start timing of the next observation period is corrected by 1 every time the correction timing is reached.
[0133]
In addition, when the error e is negative, the data output control means 35 that has received an instruction from the control unit 33 when the correction timing is within the observation period continues the data obtained by sampling twice at the correction timing. Output to the display control means 22.
[0134]
However, in this case, since the counter 30 is not incremented for the data output once, the sampling end timing of the observation period is advanced by the number of added data. If it is not the observation period, the value A (i) of the sampling start timing in the next observation period is corrected to decrease by one every time the correction timing is reached.
[0135]
Further, in the waveform observation device 20 described above, the input of the sampling signal to the sampling unit 21 is restricted by the first gate circuit 31, but the data sampled by the sampling unit 21 as in the waveform observation device 20 'described above. When the output to the display control means 22 can be controlled, the first gate circuit 31 is also omitted, and the sampling unit 21 is always connected irrespective of the sampling signal S observation period output from the signal generator 25. The control unit 33 and the data output control unit 35 control the data output from the sampling unit 21 so that only the data output during the observation period is output to the display control unit 22. Also good.
[0136]
In the above description, the sampling is started after all the values A (2) to A (Q) indicating the sampling start timing in the second and subsequent observation periods are obtained in the repeated observation mode. Only the value V representing the interval of the observed period is obtained, sampling of the observation period is started, and the start timing of the next observation period is set to V during the observation period (or immediately after the end of the observation period). It is also possible to start the sampling of the next observation period by comparing the value obtained by the calculation and the number of steps of the counter 30 with the number of steps.
[0137]
Further, in the above description, the counting operation by the counter 30 is continued from the time when the frame synchronization signal F and the sampling signal S are synchronized to the end of the last observation period. Therefore, there are cases where the number of digits of the counter 30 becomes enormous and the carry delay time cannot be ignored.
[0138]
This can be solved by continuing counting while resetting the counter 30 at an appropriate timing.
[0139]
In that case, the control unit 33 stores the count value immediately before resetting in the memory, adds the stored value and the count value of the counter 30, and the addition result indicates the end or start of the observation period. What is necessary is just to determine a timing or a correction timing.
[0140]
Although this reset timing is arbitrary, it can be performed immediately before or immediately after the above-described correction timing or each observation period. In this way, the count of the sampling signal is continued while the counter 30 is reset. Thus, a high-speed counter 30 with a small number of digits can be used, and timing errors due to a delay in the operation speed of the counter 30 can be reduced.
[0141]
Further, the control unit 33 counts the number of times the carry signal is output from the counter 30, adds the result obtained by multiplying the number of outputs by the count upper limit value of the counter 30, and the count value of the counter 30. The determination of the end or start timing of the observation period and the correction timing may be performed.
[0142]
In the above embodiment, the case where the observation start position is designated in units of bits has been described. However, this does not limit the present invention and may be designated in units of time.
[0143]
In the above-described embodiment, the case where the data signal X is an electric signal has been described. However, the present invention can be similarly applied even when the data signal X is an optical signal.
[0144]
However, as a method of sampling the optical data signal X, a first method of converting the data signal X into an electric signal and then sampling by A / D conversion to convert it into digital data, the data signal X is converted into an electric pulse. The second method of sampling by switching with the signal, converting the optical pulse signal obtained by the sampling into an electrical pulse signal, and converting the peak value into digital data, sampling the data signal X with the optical pulse There is a third method in which the optical pulse signal obtained by the sampling is converted into an electric pulse signal, and the peak value is converted into digital data, and any of them may be used.
[0145]
In the case of the first method, for example, like the sampling unit 21 shown in FIG. 12, the data signal X is converted into an electrical signal Ex by the photoelectric converter 21a and input to the A / D converter 21b, and the A / D converter The sampling signal S is given to the converter 21b, converted into a digital data Ds value, and output to the display control means 22.
[0146]
Further, in the case of the second method, like the sampling unit 21 shown in FIG. 13, the data signal X is input to the high-speed optical switch 21c, and the period equal to the sampling signal S from the pulse generator 21d that receives the sampling signal S. The optical switch 21c is turned on by a narrow electric pulse signal Ep output at Ts, the signal under measurement X is sampled, and the optical pulse signal Ps output from the optical switch 21c is converted into an electric signal by the photoelectric converter 21a. It is converted to Es, and the peak value is converted to digital data Ds by the A / D converter 21b and output.
[0147]
In the case of the third method, for example, as in the sampling unit 21 shown in FIG. 14, the optical pulse P emitted from the optical pulse generator 21 e that receives the sampling signal S at a period Ts equal to the sampling signal S The data signal X is sampled by the optical pulse P incident on the optical sampling unit 21f made of a linear optical crystal or the like, and the optical pulse signal Ps obtained by the sampling is converted into an electrical pulse signal Es by the photoelectric converter 21a. The sampling unit 21 is configured so that the peak value of the pulse signal Es is converted into a digital data Ds value by the A / D converter 21b and output.
[0148]
In the second and third methods in which the data signal X is sampled using an electric or light pulse, the resolution can be increased as the pulse width is narrower.
[0149]
Here, the width of a signal (electrical and optical signal) obtained by electrical pulse modulation is limited to about several ps. In the case of an optical pulse, the width is reduced to several tens of minutes by passing through a dispersion reducing fiber. Therefore, when the sampling resolution ΔT of 0.1 ps is to be obtained as described above, the third method described above is adopted, and the dispersion reducing fiber is provided inside the optical pulse generator 21e. May be used to generate a light pulse P having a narrow pulse width.
[0150]
【The invention's effect】
As described above, the waveform observation apparatus of the present invention generates a signal that outputs a sampling signal having a period having a difference corresponding to the observation resolution with respect to an integer multiple of the period of the frame synchronization signal based on each designated parameter. A sampling unit that counts a sampling signal output from the signal generator, a sampling unit that samples a data signal with a sampling signal output from the signal generator, and a signal output from the sampling unit Sampling corresponding to the observation start position, using the waveform display means for displaying the waveform of the data signal and the timing at which one frame sync signal is input or the output timing of the sampling signal output from the signal generator immediately thereafter as the reference timing Start timing based on bit rate, observation start position and observation resolution The waveform display means is obtained as the waveform data of one observation period, the data obtained by sampling a predetermined number of times from when the number of steps from the reference timing of the counting means coincides with the sampling start timing. And a control means for controlling to be sent out.
[0151]
For this reason, a waveform in an arbitrary range within the frame of the data signal can be observed.
[0152]
In addition, when an operation mode in which the control unit repeats a predetermined number of times of sampling for the observation period is designated, the second and subsequent times based on the reference timing used when obtaining the sampling start timing of the first observation period The sampling start timing of the observation period is obtained in units of the sampling signal cycle, and the data obtained by sampling from the time when the number of steps from the reference timing of the counting means coincides with the sampling start timing of each observation period to the predetermined time Is output to the waveform display means as waveform data for each observation period.
[0153]
For this reason, when a waveform in an arbitrary range within the frame of the data signal is repeatedly observed, the waveform of the data signal itself can be accurately observed without being affected by the jitter of the frame synchronization signal.
[0154]
The control means obtains an error between the ideal period calculation means for calculating the ideal period of sampling from the bit rate of the data signal and the observation resolution, and the period of the sampling signal actually output from the signal generator. Error calculation means, cumulative number calculation means for obtaining the cumulative number when the accumulated error value is equal to or exceeds the observation resolution, and regulation of the counter increment each time the sampling signal is output from the signal generator by the cumulative number Or a correction means for performing an additional step is provided.
[0155]
For this reason, even if there is an error due to restrictions on the number of digits that can be set by the device, the sampling timing error can be kept below the observation resolution, and there is no deviation in the display waveform due to the error. it can.
[0156]
Further, the control means is configured to initialize the counting means at every predetermined timing and obtain the number of steps of the counting means based on the count value of the counting means after the initialization and the count value immediately before the initialization. In this case, counting means with a small number of digits can be used, and more accurate observation can be performed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a flowchart showing a processing procedure of a main part of the embodiment.
FIG. 3 is a flowchart showing a processing procedure of a main part of the embodiment.
FIG. 4 is a flowchart illustrating a processing procedure of a main part of the embodiment.
FIG. 5 is a timing chart for explaining the operation of the embodiment;
FIG. 6 is a diagram showing an example of an observed waveform
FIG. 7 is a timing chart for explaining the operation of the embodiment.
FIG. 8 is a timing chart for explaining the operation of the embodiment.
FIG. 9 is a timing chart for explaining the operation of the embodiment.
FIG. 10 is a timing chart for explaining another operation example;
FIG. 11 is a block diagram showing the configuration of another embodiment.
FIG. 12 is a diagram illustrating a configuration example of a main part of the embodiment.
FIG. 13 is a diagram illustrating a configuration example of a main part of the embodiment.
FIG. 14 is a diagram illustrating a configuration example of a main part of the embodiment.
FIG. 15 is a timing chart for explaining the operation of the sampling type waveform observation apparatus;
FIG. 16 shows an example of an observed waveform
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 20 ... Waveform observation apparatus, 21 ... Sampling part, 22 ... Display control means, 23 ... Display, 25 ... Signal generator, 26 ... Parameter input means, 30 ... Counter, 31 ... 1st Gate circuit 32... Second gate circuit 33... Controller, 35.

Claims (4)

For receiving a serial data signal in which one frame is formed with a predetermined number of bits and a frame synchronization signal synchronized with the frame of the data signal, and observing a signal waveform in an arbitrary bit range in the frame of the data signal A waveform observation device,
Parameter designation means (26) for designating parameters of the bit rate, observation start position, and observation resolution of the data signal;
A signal generator (25) for outputting a sampling signal having a period having a difference corresponding to the observation resolution with respect to an integral multiple of the period of the frame synchronization signal, based on each designated parameter;
Counting means (31) for counting sampling signals output from the signal generator;
A sampling unit (21) for sampling the data signal with a sampling signal output from the signal generator;
Waveform display means (22, 23) for displaying the waveform of the data signal based on the signal output from the sampling unit;
The sampling start timing corresponding to the observation start position is set to the bit rate, with the timing at which one of the frame synchronization signals is input or the output timing of the sampling signal output from the signal generator immediately after the timing as a reference timing, Obtained in units of the sampling signal period based on the observation start position and the observation resolution, and the number of steps from the reference timing of the counting means was obtained by continuous sampling a predetermined number of times from the time when the sampling means coincided with the sampling start timing A waveform observation apparatus comprising control means (31 to 33) for controlling data to be sent to the waveform display means as waveform data for one observation period. When the operation mode in which the predetermined sampling for the observation period is repeated a plurality of times is specified, the control means performs the second time based on the reference timing used when obtaining the sampling start timing of the first observation period. The sampling start timing of the subsequent observation period is obtained in units of the cycle of the sampling signal, and from the time when the number of steps from the reference timing of the counting means coincides with the sampling start timing of each observation period to the predetermined time 2. The waveform observation apparatus according to claim 1, wherein control is performed so that data obtained by sampling is output to the waveform display means as waveform data of each observation period. The control means includes
Ideal period calculation means (S17) for calculating an ideal period of sampling from the bit rate of the data signal and the observation resolution;
Error calculation means (S18) for obtaining an error between the ideal period and the period of the sampling signal actually output from the signal generator;
A cumulative number calculating means (S20, S42) for obtaining a cumulative number when the accumulated value of the error is equal to or exceeds the observation resolution;
Correcting means (S25 to S27, S30 to S32, S37 to S39, S47 to S49, each of which controls the step of the counting means or performs additional step every time the signal generator outputs the accumulated number of sampling signals. The waveform observation apparatus according to claim 1 or 2, further comprising S52 to S54 and S59 to S61). The control means initializes the counting means at every predetermined timing, and obtains the number of steps of the counting means based on the count value of the counting means after the initialization and the count value immediately before initialization. The waveform observation apparatus according to any one of claims 1 to 3.

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