JP3662523B2 - Video codec system, data processing method between the system and external host system, and encoding / decoding control method in the system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a video codec, and more particularly, to a video codec system implemented in a processor independent of a host system, a data processing method between the system and an external host system, and an encoding / decoding control method in the system.
[0002]
[Prior art]
A video codec generally includes an encoder and a decoder, and performs encoding and decoding operations in a system that requires the encoder and decoder. Furthermore, data to be encoded is input from an external system and the encoded result is transmitted again, or encoded data is input and the decoded result is transmitted again. That is, the conventional video codec simply performs an encoding / decoding operation according to a system instruction.
[0003]
Therefore, when the video codec is implemented in an independent processor in the multimedia communication system, transmission / reception data between the multimedia communication system and the video codec needs to be appropriately processed in the video codec. A video codec structure suitable for this is required.
[0004]
[Problems to be solved by the invention]
A technical problem to be solved by the present invention is to provide a video codec system which is implemented in a processor independent of a host system and improves the performance of the video codec by including components that facilitate the operation of an encoder and a decoder. There is to offer.
Another technical problem to be solved by the present invention is to provide a method for appropriately processing data between a video codec system implemented in a processor independent of the host system and the host system.
Still another technical problem to be solved by the present invention is to provide an encoding / decoding control method in a video codec system implemented in a processor independent of a host system.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, an encoder that is implemented in a processor independent of a host system and encodes video data input through a video camera and a video output by decoding the encoded data transmitted from the host system A video codec system according to the present invention having a decoder for outputting to a video machine,
Encoder buffer that temporarily stores an encoded bit stream before transmission to the host system, decoder buffer that temporarily stores encoded data transmitted from the host system, encoder, decoder, encoder buffer, and decoder buffer working status The operation status register that records the pre-assigned bits, the instruction identification register that records the instruction word that must be performed by the encoder and decoder, and the instruction word transmitted from the host system are analyzed and recorded in the instruction identification register. An interface and a control management unit are provided for controlling the encoder and decoder through the instruction identification register after confirming each operation through the status register.
[0006]
In order to achieve the other object, a data processing method between a video codec system embodied in a processor independent of the host system and the host system is provided as follows:
(A) a step of discriminating whether the data input from the external host system is a control command word or transmission data; (b) a command to check if it is a completed command if it is a control command word; If there is a word, the process proceeds to step (a) after accumulating the control command word, and if there is no subsequent command word, writing the command word to be assigned to a pre-assigned bit of the command identification register; A step indicating that there is an instruction to be performed by the encoder and / or decoder in another pre-allocated bit of the register; and (d) checking the content indicated in step (c) in the encoder and / or decoder; Fetching the instruction word entered in
[0007]
In order to achieve the further another object, an encoding / decoding control method in a video codec system according to the present invention embodied in a processor independent of a host system includes:
(A) resetting pre-assigned bits of the work state register in the video codec system so that the encoder and / or decoder is performed if a start command is input from the host system; (b) the encoder and / or (A) confirming reset of the working status register in step (a) to determine whether encoding and / or decoding has been performed; (c) the encoder buffer and decoder buffer in the video codec system are in their own states; And (d) checking the status of the encoder buffer and decoder buffer recorded in the work status register, and then controlling the operation of the encoder and decoder. .
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described with reference to the accompanying drawings.
FIG. 1 is a block diagram for explaining an internal configuration of a video codec system according to the present invention. The video codec system includes an interface and control manager (ICM: Interface & Control Manager) 110, a work status register (TSR) 120, a command identification register (CIR: Command Identification Register) 130, an encoder 140, an encoder buffer 150, A decoder 160 and a decoder buffer 170 are provided.
[0009]
The ICM 110 receives a control command word or transmission data from the multimedia communication system 200 of the host system outside the video codec system 100 using the register file, and transmits a response or data to the system 200. Further, the ICM 110 controls the operations of the encoder 140 and the decoder 160 with reference to a control command word from the TSR 120 or the multimedia communication system 200. The ICM 110 analyzes the control instruction word, transmits the analyzed instruction word to the encoder 140 and the decoder 160 through the CIR 130, and notifies the multimedia communication system 200 of the result as necessary.
[0010]
The encoder buffer 150 is a temporary storage location for transmitting the bit stream encoded by the encoder 140 to an external host system. The encoder buffer 150 indicates the state of the buffer before and after accepting input from the encoder 140, such as an empty level, a full level, a half level, a user-defined level, and the like. At this time, if the state of the encoder buffer does not satisfy the condition for accepting input, the operation of the encoder is stopped.
[0011]
The decoder buffer 170 is a temporary storage location for decoding a bitstream encoded and transmitted from an external host system. Similar to encoder buffer 150, the buffer state is shown before and after accepting input. Furthermore, the encoded bit stream is not recorded unless the state of the decoder buffer is a condition for accepting input.
[0012]
The TSR 120 smoothly encodes and decodes transmission data (ie, an encoded bit stream) input from an external host system and data to be encoded input to the encoder 140 through a video camera (not shown). belongs to. Specifically, for buffer management, the states of the encoder 140, the encoder buffer 150, the decoder 160, and the decoder buffer 170 are recorded in bits assigned in advance. When each of these operations executes a job related to another operation, the ICM 110 checks whether or not the precondition is satisfied through the TSR 120. That is, the encoder 140 and the decoder 160 are controlled based on the work state stored in the TSR 120. The following is an example of the TSR120 format.
tsr [0]: Set if the encoder buffer is empty, otherwise reset.
tsr [1]: Set if the encoder buffer is full, reset otherwise.
tsr [2]: Set if the encoder buffer level is more than half, otherwise reset.
tsr [3]: Set if the encoder buffer level is equal to or higher than the specified level set by the user.
tsr [4]: Set if the decoder buffer is empty, otherwise reset.
tsr [5]: Set if the decoder buffer is full, reset otherwise.
tsr [6]: Set if the decoder buffer level is more than half, otherwise reset.
tsr [7]: Set if the decoder buffer level is equal to or higher than the specified level set by the user.
tsr [8]: If set, the encoder is masked. Updated by encoder.
tsr [9]: If set, the decoder is masked. Updated by decoder.
tsr [10]: If set, encoding is not allowed. Updated by ICM. If reset, the encoder can be processed if necessary. tsr [11]: If set, decoding is not allowed. Updated by ICM. If reset, the decoder can be processed if necessary.
tsr [12]: If set, the encoder buffer is masked. ICM cannot read the encoder buffer. Updated with encoder buffer.
tsr [13]: If set, the decoder buffer is masked. ICM cannot record access to decoder buffer. Updated by decoder buffer.
tsr [14]: If set, encoder buffer is not allowed. The encoder cannot record in the encoder buffer. Updated by ICM.
tsr [15]: If set, decoder buffer is not allowed. The decoder is unreadable from the decoder buffer. Updated by ICM.
tsr [16]: Global mask. If set, all functions are disabled.
[0013]
Next, the ICM 110 records the corresponding instruction word in the CIR 130 when the encoder 140 and the decoder 160 need to perform the instruction word. The encoder 140 and the decoder 160 check the presence / absence of an instruction word through the CIR 130 and execute it when the respective operations are not performed. The following is an example of the format of CIR130.
cir [0]: If set, the encoder has one or more instructions to be executed. The number of instructions is indicated in cir [2: 4].
cir [1]: If set, the decoder has one or more instructions to be executed. The number of instructions is shown in cir [5: 7].
cir [2: 4]: The encoder must command as many times as the number in these bits. The contents of the command can be read with the factor table specified by the table address variable.
cir [5: 7]: The decoder must execute the instruction as many times as the number in these bits. Instruction contents can be read by the factor table specified by the table address variable.
cir [8]: Set after the encoder has fetched all instructions in the factor table.
cir [9]: Set after the decoder fetches all instructions in the factor table.
[0014]
As shown in FIG. 323, H.H. 324 and the like, and as an image codec including an encoder 140 and a decoder 160, H.264 is used. 261, H.H. H.263, MPEG-2, MPEG-4, etc. are applied. The multimedia communication system 200 exchanges data with the outside wirelessly or by wire. The multimedia communication system 200 transmits video-related data, necessary control command words, user input, and the like to the video codec system 100, and receives encoded video data and responses to the control command words as necessary. To do.
[0015]
The format of the command word transmitted from the multimedia communication system 200 to the video codec system 100 is, for example, as illustrated in FIG. Referring to FIG. 2, the instruction word is divided into an actual instruction word portion and a parameter portion. In the 2 bytes corresponding to the actual instruction word portion, the upper bits 15 to 7 indicate the classification of the corresponding instruction word, and the remaining bits 6 to 0 indicate the attribute of the corresponding instruction word.
[0016]
When the instruction word code generation is specifically examined, first, a code based on the instruction classification is generated. The instruction classification is classified into, for example, com_reg [9: 7]: minor classification, com_reg [13:10]: medium classification, and com_reg [15:14]: major classification. Here, com_reg [15:14] is, for example, 00: reserved bits for instruction debugging, 01: instructions related to encoders, 10: instructions related to decoders, 11: related to encoders and decoders or other modules Indicates the command For example, com_reg [13:10] indicates an instruction related to a detailed function of components constituting the encoder and decoder, and com_reg [9: 7] indicates an instruction related to a more detailed function.
[0017]
Next, a code with an instruction attribute is generated.
com_reg [0]: Necessity of response corresponding to the command. When the end flag is 0, it is a response regarding whether or not the command has been correctly received, and when it is 1, it is a response regarding whether or not the command to be executed has been correctly executed. 1: Response required, 0: Response not required.
com_reg [1]: whether or not the set instruction has been completed.
1: Execute accumulated instructions, 0: Have consecutive instructions.
com_reg [3: 2]: whether and how many parameters follow the instruction.
00: No parameter is requested.
01: A parameter of a predetermined byte follows.
In addition to 10:01, a parameter of a predetermined byte further follows.
com_reg [4]: Whether the function corresponding to the instruction is on or off.
1: ON, 0: OFF.
com_reg [5]: Whether the response is an acknowledgment (ACK) or a negative response (NAK).
1: ACK, 0: NAK.
com_reg [6]: Is it an instruction sent from the host to the codec or a response to it?
0: Command from the host to the codec.
1: Response from codec to host.
[0018]
FIG. 3 is a flowchart for explaining a data processing method between the video codec system and the external host system. The external host system transmits a start command to the ICM 110 to start operation of the encoder and decoder. The operation of the video codec system for performing the work of the encoder and decoder after the start command is transmitted will be described as follows.
[0019]
Referring to FIG. 3, first, data is input from an external host system in the ICM 110 (operation 300). It is determined whether the input data is a control command word or transmission data (step 302). For example, a 1-bit control instruction word / transmission data identification bit is added to the header (not shown) portion of the instruction word format shown in FIG. In the case of transmission data, the transmission data is transmitted together with an identification bit instead of the command format shown in FIG.
[0020]
It is determined whether it is a control command word (step 304), and if so, it is confirmed through com_reg [1] whether it is a completed command (step 306). It is determined whether there is a subsequent instruction word (step 308). If so, the control instruction word is accumulated (step 310). That is, in the CIR 130, the number of instruction words is counted for cir [2: 4] and / or cir [5: 7]. After step 310, the process proceeds to step 300 again. That is, the above-described operation is repeated until the value of com_reg [1] is 1.
[0021]
If it is determined in step 308 that there is no instruction word that follows, that is, if it is a completed instruction, the instruction word to be executed, ie, cir [2: 4] and / or cir [5: 7] in the CIR 130, that is, Enter the number of command words (step 312). The number of command words entered indicates the result accumulated in step 310. Next, the CIR 130 indicates that there is an instruction to be performed by the encoder 140 and / or the decoder 160 (step 314). That is, cir [0] and / or cir [1] are set to 1. This is a process in which an instruction word is analyzed in the ICM 110 and the analyzed result is written in a corresponding bit of the CIR 130.
[0022]
Next, the CIR 130 is confirmed in the encoder 140 and / or the decoder 160, and an instruction is fetched (step 316). Specifically, the encoder 140 or the decoder 160 confirms cir [0] or cir [1] after encoding or decoding in units of one frame, and cir [2: 4] or cir [5: 7] fetch the instruction word. Next, an instruction word is performed in the encoder 140 and / or the decoder 160 (that is, after performing encoding and / or decoding operations) to indicate that all instructions are fetched to the CIR 130 (step 318). That is, it is set that the instruction is completed by setting cir [8] and / or cir [9].
[0023]
Next, it is determined whether or not a response to the external host system is required for the input control command word by looking at com_reg [0] (step 320). If the external host system requests a response, the ICM 110 writes ACK or NAK to com_reg [5], dumps the remaining instruction word part as it is, and responds to the system (step 322). Further, the ICM 110 checks the state of the encoder buffer 150 through the TSR 120 according to a transmission command issued from the external host system, and then reads the encoded data and transmits it to the system.
[0024]
On the other hand, if it is not a control command in step 304, the ICM 110 checks the state of the decoder buffer 170 through the TRS 120, and then fills in the transmission data, that is, the encoded bit stream (step 324).
[0025]
FIG. 4 is a flowchart for explaining an encoding / decoding control method in the video codec system. The video codec system causes the encoder and / or the decoder to perform respective operations at the same time when a start command is issued from the external host system.
[0026]
Referring to FIG. 4, the start instruction causes the ICM 110 to enable the encoder 140 and / or the decoder 160 in the TSR 120. That is, tsr [10] and / or tsr [11] are reset (step 400). Next, the encoder 140 and / or the decoder 160 checks corresponding bits in the TSR 120, that is, tsr [10] and tsr [11], respectively, and determines whether encoding and / or decoding has been performed (No. 410). Stage).
[0027]
The encoder buffer 150 and the decoder buffer 170 indicate their states in the corresponding bits in the TSR 120, that is, one of tsr [0] to tsr [3] and one of tsr [4] to tsr [7] (first 420 stage). Next, the ICM 110 controls the encoder 140 and the decoder 160 through the CIR 130 based on the states of the encoder buffer 150 and the decoder buffer 170 recorded in the TSR 120 (operation 430).
[0028]
Illustratively, if tsr [0] = 1 for encoder buffer 150, ICM 110 increases the priority of encoder 140. If tsr [1] = 1, the execution of the encoder 140 is stopped, and tsr [10] = 1 and tsr [14] = 1. If tsr [2] = 1, the priority of the encoder 140 is lowered if a fixed time has not elapsed in the state of tsr [0] = 1. On the other hand, if tsr [1] = 1 does not elapse for a certain time, the priority order of the encoder 140 is increased. tsr [3] = 1 and tsr [7] = 1 are specified by the developer for more precise control, and are processed in the same manner as tsr [2] = 1 and tsr [6] = 1. Is done.
[0029]
If tsr [4] = 1 for the decoder buffer 170, the ICM 110 stops the execution of the decoder 160 and sets tsr [11] = 1. If tsr [5] = 1, the decoder buffer 170 cannot be used, and tsr [13] = 1. If tsr [6] = 1, the priority of the decoder 160 is increased if a fixed time does not elapse in the state of tsr [4] = 1. On the other hand, if the fixed time does not elapse in the state of tsr [5] = 1, the priority of the decoder 160 is lowered.
[0030]
As a result, the ICM 110 refers to the state of each buffer and performs control operations such as stopping and starting the encoder 140 and the decoder 160 so that each buffer does not become full or empty.
[0031]
【The invention's effect】
As described above, the present invention implements a video codec system in a processor independent of the multimedia communication system, and includes components that facilitate the work of the encoder and decoder in the video codec system. There are merits of improving the performance of the codec, having reliability, and facilitating control of encoding and decoding operations. Furthermore, the video codec system according to the present invention is an H.264 standard. 261, H.H. It has a control structure irrespective of the codec type to which H.263, MPEG-2, MPEG-4, etc. are applied.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an internal configuration of a video codec system according to the present invention.
FIG. 2 is a diagram illustrating an example of an instruction word format transmitted from an external host system to a video codec system.
FIG. 3 is a flowchart for explaining a data processing method between a video codec system and an external host system.
FIG. 4 is a flowchart for explaining an encoding / decoding control method in a video codec system.
[Explanation of symbols]
100 Video codec system 110 ICM
120 Work Status Registrar 130 Instruction Identification Register 140 Encoder 150 Encoder Buffer 160 Decoder 170 Decoder Buffer 200 Communication System

Claims (4)

An encoder embodied in a processor independent of a host system and encoding video data input through a video camera, and a decoder for decoding encoded data transmitted from the host system and outputting the decoded data to a video output device Video codec system
An encoder buffer that temporarily stores a bitstream encoded in the encoder before transmission to the host system;
A decoder buffer for temporarily storing encoded data transmitted from the host system;
A working status register that records the working status of the encoder, decoder, encoder buffer and decoder buffer in pre-assigned bits;
An instruction identification register holding information about the state of the instruction word to be executed by the encoder and decoder
An interface and control management unit that analyzes the instruction word transmitted from the host system, records the instruction word in the instruction identification register, checks each operation through the work status register, and controls the encoder and decoder through the instruction identification register And a video codec system. The encoder buffer and decoder buffer are each
The video codec system according to claim 1, further comprising a bit indicating its own state at least one of an empty level, a full level, a half level, and a user-defined level. The instruction identification register is
At least a bit indicating that there is one or more instructions executed by the encoder and decoder, a bit indicating the number of instruction words to be executed, and a bit indicating that the encoder and decoder have fetched all instructions The video codec system according to claim 1. In an encoding / decoding control method in a video codec system implemented in a processor independent of a host system,
(A) resetting a pre-assigned bit of a work status register in the video codec system so that an encoder and / or decoder can operate if a start command is input from the host system;
(B) determining whether the encoder and / or decoder has performed encoding and / or decoding by confirming the reset of the working status register in step (a);
(C) an encoder buffer and a decoder buffer in the video codec system each indicating its own state to other pre-assigned bits of the working state register;
(D) checking the status of the encoder buffer and decoder buffer recorded in the work status register and then controlling the work of the encoder and decoder, and encoding / decoding in a video codec system, Coding control method.

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