JP3657970B2 - Decoding method and apparatus - Google Patents

Description

  The present invention relates to a system for transmitting / accumulating information via a medium having a high error rate such as a radio transmission line, and transmitting / storing a compressed code string obtained by high-efficiency compression coding after error correction / detection coding. The present invention relates to a decoding method and apparatus suitable for storage.

  For example, in a system such as a wireless TV phone, a portable information terminal, and a digital TV broadcast system, which compresses and encodes image and audio information with high efficiency so as to have as little information as possible and transmits the information via a wireless transmission path or the like. Since the error rate of the transmission path is high, how to transmit the obtained code string with high quality becomes an important issue.

  When a code string is transmitted / stored through a medium having a high error rate, error correction codes such as a BCH code, an RS code, and a convolution are often used as means for reducing the error rate. Further, as means for enabling error detection on the receiving side, an error detection code such as a checksum or CRC is used. These error correction / error detection adds an extra bit (redundancy) to the information to be transmitted / stored according to a certain rule, checks whether the code string transmitted / stored at the time of decoding conforms to this rule, Based on the result, error correction and detection are performed.

  However, the method of encoding / transmitting / accumulating the code string obtained by the high-efficiency compression encoding into the error correction / detection code is a method for recovering the loss of synchronization caused by the code word error in the transmission path / medium. The disadvantage is that it becomes difficult to combine with recovery techniques. As a synchronization recovery method, a method of inserting a code called a synchronization code that can be uniquely decoded and restarting decoding from the point in time when the synchronization code is detected when loss of synchronization occurs is often used.

  In order to make the synchronization code a uniquely decodable codeword, it is necessary to configure the codeword so that the same bit pattern as that of the synchronization code does not occur in other codeword combinations. However, in general, in error correction / detection coding, it is difficult to construct a code word so as to avoid the appearance of a specific bit pattern. When the same bit pattern as the synchronization code appears, the synchronization code error is detected. Detection will cause pseudo-synchronization.

  In order to avoid this problem, it is determined whether or not the same bit pattern as the synchronization code exists in the code string after performing error correction / detection coding. A method is used in which dummy bits are inserted according to a certain rule, and the dummy bits are deleted according to the same rule in the decoding apparatus to prevent pseudo-synchronization. However, when a code string is transmitted / stored via a medium that is prone to error, there is a possibility that an error also occurs in this inserted bit, which causes a problem of new loss of synchronization and pseudo synchronization.

  Further, when error correction / detection coding is performed on a code string and a synchronization code is inserted, a remainder of information bits to be error correction / detection coded is conventionally stored at the last part of a synchronization interval sandwiched between the synchronization code and the synchronization code. In order to compensate, it is necessary to add many insertion bits to the code string, and there is a problem that the coding efficiency is lowered.

  On the other hand, in order to increase the error correction / detection capability, it is sufficient to increase the redundancy of information to be transmitted / stored. However, this increases the number of bits necessary to send the same information. For this reason, when the error correction / detection capability is increased, a transmission path with a higher transmission rate is required, or the number of bits of information to be accumulated increases. If the transmission rate and the storage capacity are the same, the higher the redundancy, the less information can be transmitted / stored. When image / sound is compressed and transmitted with high efficiency for transmission / accumulation, redundancy is added to improve error resilience. If the transmission / accumulation rate is the same, compression encoding is performed for a smaller amount of information. As a result, image quality and sound quality are degraded.

  Therefore, there is a method called hierarchical coding as a method of giving high error tolerance with less redundancy. This classifies high-efficiency compression-coded information according to the magnitude of the error that affects the image quality and sound quality. Information with a large influence of error has a higher degree of error correction / detection capability even if the redundancy is high. By using a detection code and using an error correction / detection code that is not very high in error correction / detection capability but low redundancy for information that is not greatly affected by errors, the same error correction / detection code is used throughout. This is a method of increasing error resilience with the same average redundancy.

  For example, a motion compensation prediction that is often used for high-efficiency compression coding of moving images and an encoding method that combines orthogonal transformation, that is, motion compensation prediction is performed on an input moving image signal, and the prediction residual is In the method of orthogonally transforming the signal by DCT (Discrete Cosine Transform) or the like, error correction / An error correction / detection code having a strong detection capability is used, and an error correction / detection code having a weak error correction / detection capability is used as a higher-order coefficient among orthogonal transform coefficients of a prediction residual signal that is less affected by errors.

  In order to realize such hierarchical encoding, it is necessary to switch between error correction / detection codes having different error correction / detection capabilities in the middle of an output code string. As a method of switching between error correction / detection codes having different error correction / detection capabilities, there is a method of adding header information indicating the type of error correction / detection code to a code string. FIG. 11 shows an example of a code string in which header information is added and the error correction / detection code is switched. In this example, two types of error correction / detection codes FEC1 and FEC2 are switched. The headers 1101 to 1104 contain header information indicating the type of error correction / detection code and the number of code words. In the encoding apparatus, the code words that have been subjected to error correction / detection encoding are arranged after the header information, and in the decoding apparatus, the header information is decoded, and the error correction / detection code is decoded accordingly.

  However, the method of switching the error correction / detection code by adding such header information has a problem that the number of bits of the code string that must be transmitted / stored increases by adding the header information. When transmitting / accumulating high-efficiency compression encoding and transmission of images and audio, the number of bits used for header information decreases the number of bits used for high-efficiency compression encoding of images and audio. In addition, image quality and sound quality are degraded.

  As described above, when error correction / detection encoding is performed on a code string obtained by performing high-efficiency compression encoding on a moving image signal or the like, an arbitrary bit pattern is generated. Therefore, error correction / detection encoding is uniquely performed. When combined with a synchronization recovery method using a decodable synchronization code, there is a problem of pseudo-synchronization due to erroneous detection of the synchronization code, and even if an operation to avoid pseudo-synchronization is performed by inserting a dummy bit, There has been a problem that a new synchronization loss or pseudo-synchronization may occur due to an error in.

  Further, when error correction / detection coding is performed on a code string and a synchronization code is inserted, conventionally, it is necessary to use a large number of insertion bits to make up the remainder of information bits to be error correction / detection encoded at the last part of the synchronization interval. Therefore, there is a problem that the encoding efficiency is lowered.

  Furthermore, in an encoding / decoding device that switches error correction / detection codes having different error correction / detection capabilities by adding header information, the number of bits that must be transmitted / stored increases by adding header information. In the case of transmitting / accumulating high-efficiency compression-encoded images and sounds, there is a problem that the amount of information allocated to image and sound information is reduced, resulting in deterioration of image quality and sound quality.

  A main object of the present invention is to provide a decoding method and apparatus capable of solving the problems of pseudo-synchronization and loss of synchronization due to erroneous detection of a synchronization code.

  In order to solve the above problems, a decoding method according to the present invention includes a multiplexed code sequence obtained by multiplexing a plurality of types of variable length codes generated by compressing and encoding an image signal, and is periodically determined in advance. A synchronization code is detected at the synchronization code insertion position in the input code string in which a stuffing bit having a length equal to or shorter than the period of the plurality of synchronization code insertion positions is inserted, and the multiplexed code string in the input code string is detected. On the other hand, a variable length code is generated by performing demultiplexing with reference to the position of the synchronization code detected by the synchronization code detecting means, and the reproduced variable length code is decoded and a reproduced image signal is output. To do.

  A decoding apparatus according to the present invention includes a multiplexed code sequence obtained by multiplexing a plurality of types of variable length codes generated by compressing and encoding an image signal, and a plurality of synchronous code insertion positions that are periodically determined in advance. Synchronization code detecting means for detecting a synchronization code at the synchronization code insertion position in the input code string in which stuffing bits having a length equal to or less than the period are inserted, and the synchronization code for the multiplexed code string in the input code string Demultiplexing means for generating a variable length code by performing demultiplexing with reference to the position of the synchronization code detected by the detection means, and decoding means for decoding the generated variable length code and outputting a reproduced image signal It is characterized by having.

  In the present invention, the synchronization code is a uniquely decodable code inserted in the code string for recovery of synchronization. For example, the code string into which the synchronization code is inserted compresses an image signal input in units of frames. In the case of a multiplexed code string obtained by multiplexing a plurality of types of encoded variable length codes, it is a code indicating a delimiter of encoded frames, a delimiter of a plurality of types of variable length codes, and other delimiters.

  According to the present invention, it is only necessary to perform synchronization detection only at a synchronization code insertion position periodically determined in advance in a multiplexed code string obtained by multiplexing a plurality of types of variable-length codes in an encoding apparatus. Compared to the conventional method in which a synchronization code is inserted at an arbitrary position, the number of synchronization code detections is reduced.

  In addition, since the probability of occurrence of pseudo-synchronization due to the bit string that is input to the decoding device due to a bit error changing to the same bit pattern as the synchronization code decreases with a reduction in the number of synchronization code detections, According to the present invention, the occurrence of pseudo-synchronization can be reduced, and the amount of calculation processing associated with synchronization code detection is also reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows a combination of a coding apparatus having an error correction / detection code switching function according to the present invention and a high-efficiency compression coding apparatus using discrete cosine transform coding, which is a kind of motion compensated adaptive prediction and orthogonal transform coding. It is a block diagram which shows one Embodiment of the moving image encoding device. The coding method combining motion compensated adaptive prediction and discrete cosine transform coding is detailed in, for example, Reference 1: Hiroshi Yasuda, “International Standard for Multimedia Coding”, Maruzen, (June 1991), etc. Only the outline of the operation will be described. In addition, the error correction / detection code used in the present embodiment is such that information bits and check bits are separated as in a BCH code.

  In FIG. 1, an input moving image signal 131 to be encoded input in units of frames is first subjected to motion compensation adaptive prediction in units of small regions such as macroblocks. That is, the motion compensated adaptive predictor 101 detects a motion vector between the input moving image signal 131 and the image signal that has been stored in the frame memory 102 and has already been encoded / locally decoded. A prediction signal 132 is generated by motion compensation prediction based on the vector. In the motion compensated predictor 101, a prediction mode which is suitable for encoding among motion compensation predictive coding and intraframe coding (predicted signal = 0) in which the input moving image signal 131 is coded as it is. Is selected, and a corresponding prediction signal 132 is output.

  The prediction signal 132 is input to the subtractor 103, and the prediction residual signal 133 is output by subtracting the prediction signal 132 from the input moving image signal 131. The prediction residual signal 133 is subjected to discrete cosine transform (DCT) in units of blocks having a certain size in the discrete cosine transformer 104, and DCT coefficients are generated. This DCT coefficient is quantized by the quantizer 105. The quantized DCT coefficient data from the quantizer 105 is divided into two branches, one of which is variable length encoded by the first variable length encoder 106 and the other is dequantized by the inverse quantizer 107. The inverse discrete cosine transformer 108 performs inverse discrete cosine transform (inverse DCT). The output from the inverse discrete cosine transformer 108 is added to the prediction signal 132 in the adder 109 to generate a local decoded signal. This locally decoded signal is stored in the frame memory 102.

  On the other hand, the prediction mode and motion vector information determined by the motion compensated adaptive predictor 101 are variable length encoded by the second variable length encoder 110. The variable length codes (compressed codes) output from the first and second variable length encoders 106 and 110 are multiplexed by the multiplexer 111 to become a multiplexed code string 201.

  The multiplexer 111 outputs a multiplexed code string 201, an FEC type identification signal 202 indicating the type of the error correction / detection code corresponding thereto, and a synchronization code insertion request signal 203 for requesting the insertion of a synchronization code. .

  The code sequence 202, the FEC type identification signal 202, and the synchronization code insertion request signal 203 are encoded by switching the code sequence 202 to a plurality of types of error correction / detection codes having different error correction / detection capabilities. And a final output code string 205 is generated. In the present embodiment, the output encoding device 200 corresponds to the encoding device according to the present invention.

  FIG. 2 is a diagram showing a multiplexing flow in the multiplexer 111. Multiplexing is performed in units of encoded frames. First, the synchronization code 301 is multiplexed. When the synchronization code 301 is multiplexed, the multiplexer 111 outputs a synchronization code insertion request signal 203 to inform the encoding device 200 that the multiplexed code word is a synchronization code. Next, a picture header 302 indicating various encoding modes of the encoded frame is multiplexed on the multiplexed code string 201. Next, prediction mode information 303 indicating a prediction mode in the motion compensated adaptive predictor MC in each region is multiplexed, and further, DCT coefficients of the motion vector information 304 and the prediction residual signal (hereinafter referred to as residual DCT coefficients). 305 is multiplexed. When the picture header 302, the prediction mode information 303, the motion vector information 304, and the residual DCT coefficient 305 are multiplexed, the FEC type identification signal 202 indicating the type of the corresponding error correction / detection code is output.

  An error correction / detection code having a high correction / detection capability is used for the picture header 302, the prediction mode information 303, and the motion vector information 304 whose image quality is greatly deteriorated when an error is mixed. On the other hand, the residual DCT coefficient 305 can prevent a large deterioration in image quality by detecting even if an error is mixed and setting the residual to 0. Therefore, the error correction capability does not need to be so high. It is only necessary to enable error detection.

  FIG. 3 is a block diagram showing a configuration of output encoding apparatus 200 in FIG. The output encoding apparatus 200 includes a bit inserter 211, an error correction / detection switching encoder 212, and a code string assembler 213. FIG. 4 is a diagram illustrating an example of an output code string 205 generated by the output encoding apparatus 200. In FIG. 4, PSC is a synchronization code, PH is a picture header, MODE is prediction mode information, MV is motion vector information, CHK is an error correction / detection code check bit, COEF is a residual DCT coefficient, and STUFF is a stuffing bit (insertion). Bit). This output code string 205 has the following characteristics.

  (1) The synchronization code PSC is inserted only at one of the synchronization code insertion positions indicated by arrows arranged at regular intervals (every sync_period bits). The length of sync_period is larger than the length of the synchronization code PSC and the maximum length of the check bit CHK. The check bit CHK is shifted so as to come immediately before the synchronization code insertion position.

  (2) The error correction / detection code of the last part of one synchronization period sandwiched between one frame, that is, the synchronization code PSC and the next PSC, is a degenerate code that encodes only the last remaining information bit, Bit insertion of the stuffing bit STUFF is performed for the number of bits necessary to shift the position of the bit CHK (CHK6 in the example of FIG. 4).

  (3) The FEC type identification signal indicating the type and number of error correction / detection codes does not exist in the output code string 205 of FIG.

  In this output code string 205, since the check bit CHK is shifted in position as in (1) above, the check bit CHK does not enter the synchronization code insertion position indicated by the arrow. There is no possibility of pseudo-synchronization occurring. Also, when error correction / detection encoding at the end of a frame is performed as in (2) above, it has been necessary to insert many insertion bits (dummy bits) in the conventional technique, but in this embodiment, Since the end of the frame is a degenerate code, the number of inserted bits can be reduced. Further, since the header information indicating the type and number of error correction / detection codes as described in (3) above is not included in the output code string 205, there is no increase in the code amount due to this.

  Hereinafter, with respect to the configuration and operation of the output coding apparatus 200 of FIG. 3 that generates such an output code string 205, the multiplexed code string 201 of FIG. 2 and the output code string 205 of FIG. This will be described in detail.

  When the synchronization code 301 is multiplexed by the multiplexer 111, the synchronization code insertion request signal 203 is output as described above. The synchronization code 301 includes, for example, “0” of the sync_0_len bit, “1” of 1 bit, and “xxx × xxx” of the sync_nb_len bit indicating the type of the synchronization code 301 as shown in FIG. When receiving the synchronization code 301 and the synchronization code insertion request signal 203 from the multiplexer 111, the output encoding device 200 outputs a synchronization code (PSC) as the output code sequence 205 from the code sequence assembler 213.

  Here, since the synchronization code 301 can be inserted only at the synchronization code insertion positions arranged at every sync_period bits in the output code string 205 as shown in FIG. When the output code sequence 205 is not at the end of the synchronization code insertion position, a stuffing bit STUFF is inserted as described later so that the synchronization code 301 is positioned at the synchronization code insertion position.

  When the synchronization code 301 is output to the output code string 205, the picture header 302, the prediction mode information 303, the motion vector information 304, and the residual DCT coefficient 305 are encoded as follows. First, bit insertion for preventing the occurrence of pseudo-synchronization is performed in the bit insertion unit 211 for the multiplexed code sequence 201 output from the multiplexer 111. That is, if there is a bit pattern identical to the code word of the synchronization code 301 in the output code string 205, bit insertion is performed as necessary to prevent the synchronization code 301 from being uniquely decoded. For example, if the synchronization code 301 is a code word in which “0” of the sync_0_len bit is continuous as shown in FIG. 5, “1” is inserted in the code string other than the synchronization code 301 so that “0” does not continue for more than sync_0_len bits. Then, the occurrence of pseudo synchronization can be prevented.

As described above, since the synchronization code 301 is inserted only at the synchronization code insertion position, the bit insertion operation for preventing the occurrence of pseudo synchronization may be performed only at the synchronization code insertion position. Therefore, a count value 221 indicating the total number of bits of the output code string 205 generated so far is output from the code string assembler 213, and whether or not bit insertion is necessary based on the count value 221 by the bit inserter 211. Determine whether. If the count value 221, that is, the total number of bits of the output code string 205 already generated is total_len,
0 <total_len mod sync_period ≦ sync_0_len
The number of “1” s in the multiplexed code string 201 is counted in the interval, and if there is no “1” in this interval, 1-bit “1” is inserted. Here, Amod B represents the remainder when A is divided by B.

  Further, in order to reduce the probability of erroneous detection of the synchronization code 301 due to an error, bit insertion may be performed as follows.

  In order to detect the synchronization code 301 even when an n-bit error is mixed in the synchronization code 301, a codeword having a true synchronization code and a Hamming distance of n or less in an input decoding device of a moving image decoding device to be described later Must be determined as a synchronous code. However, if such a determination is made with the code string other than the synchronization code 301 as it is, a bit pattern having a synchronization code and a Hamming distance of n or less may exist in the code string other than the synchronization code 301. The synchronization code 301 is erroneously determined as being at the synchronization code insertion position.

Therefore, the bit inserter 211 inserts a bit into the multiplexed code string 201 as follows, so that the code string other than the synchronization code at the synchronization code insertion position in the multiplexed code string 201 is hummed with the synchronization code 301. Conversion is performed so that the distance is 2 * n + 1 or more. In particular,
0 <total_len mod sync_period ≦ sync_0_len− (2 * N + 1)
The number of “1” s in the interval (assuming n = n) is counted, and if n0 is 2 * n + 1 or less, 2 * n + 1−n0 bit “1” is inserted into the multiplexed code string 201.

  The encoded sequence 222 after bit insertion by the bit inserter 211 is input to the error correction / detection code switching encoding unit 212 together with the FEC type identification signal 202 indicating the type of error correction / detection code. .

  FIG. 6 is a block diagram showing a configuration of error correction / detection code switching encoding section 212 in FIG. The latch circuit 603 is a circuit that latches the FEC type identification signal 202. When the output of the synchronization code from the multiplexer 111 to the multiplexed code string 201 is completed and the synchronization code insertion request signal 203 is stopped, the FEC type identification signal is detected. The signal 202 is latched, and the latched signal 623 is supplied to the error correction / detection encoder 604.

  The error correction / detection encoder 604 performs error correction / detection encoding on the code string 222 from the bit inserter 211 in accordance with the latched signal 623, and generates and outputs information bits 631 and check bits 632. Further, when error correction / detection encoding of one block is completed, the error correction / detection encoder 604 outputs a latch instruction signal 625 for instructing the latch circuit 603 to latch the next FEC type identification signal 202. The latch circuit 603 performs latching according to the latch instruction signal 625 and supplies the latched signal 623 to the error correction / detection encoder 604.

  The output encoding apparatus 200 repeats the above operation, and the code string 222 after the bit insertion from the bit insertion unit 211 is the FEC type identification signal indicated by the error correction / detection switching encoder 212 from the multiplexer 111. The error correction / detection code is switched while the error correction / detection code is switched according to 202. Since the FEC type identification signal 202 is latched by the latch circuit 603 only at the end of encoding of one block of error correction / detection code, the same error correction / detection code is applied up to this switching point. For example, when an error correction / detection code of FEC1 is used for the picture header 302 and the prediction mode information 303 is FEC2, if the number of bits of the picture header 302 is shorter than the number of information bits of one block of FEC1, the subsequent prediction mode information 303 As the error correction / detection code, FEC1 is used until the number of information bits of FEC1 is reached.

  FIG. 7 is a block diagram showing the configuration of the code string assembler 213 in FIG. The code string assembler 213 includes a counter 701 that counts the number of bits of the output code string 205, a check bit 632 and a buffer 702 that temporarily stores the number of bits, a switch 703 that switches the output code string 205, and a switch The switch controller 704 controls the control 703.

  When the synchronization code insertion request signal 203 is input, the counter 701 is reset to the value of the synchronization code length sync_len, and counts up until the next synchronization code is input in order from the next bit of the synchronization code. After the synchronization code is input, the switch 703 operates so that the information bit 631 is output until the first check bit 632 is input. When the check bit 632 is input, the check bit 632 is stored in the buffer 702, and the number of bits (check bit number) 711 is output from the buffer 702 to the switching controller 704.

Based on the number of check bits 711 and the count value 221 of the counter 701, the switching controller 704 switches the check bit so that the check bit 632 is not output to the synchronization code insertion position as described above. 703 is controlled. For example, if the count value 221 is bit_count and the check bit number 711 is check_len,
bit_count mod sync_period <sync_period− check_len
In this case, information bit 631 is output,
sync_period− check_len ≦ total _bits mod sync_period <sync_period
At this time, the check bit 713 stored in the buffer 702 is output. Thereafter, the above process is repeated while inputting the information bit 631 and the check bit 632.

  The output encoding apparatus 200 uses a degenerate code as an error correction / detection code in the last part of one frame as described above, and inserts bits to shift the position of check bits. Behaves differently than usual. That is, the multiplexer 111 outputs the synchronization code insertion request signal 203 of the next frame when the output of the multiplexed code string 201 of one frame is completed. Correspondingly, the error correction / detection encoder 604 in the error correction / detection switching encoder 212 in FIG. 6 outputs the shortage of the information bits 631 of the error correction / detection code from the insertion bit generator 705. Thus, error correction / detection encoding using a degenerate code is performed on the assumption that the bit pattern is a predetermined bit pattern. In this bit pattern, all bits may be “1”, “0”, or a specific pattern such as “0101...” May be repeated. The supplementary insertion bit is not output to the information bit 631.

In the code string assembler 213 in FIG. 7, after the information bits 631 are output to the end, the switch 703 is switched from the bit generator 705 to the input, and the check bit 713 stored in the buffer 702 is immediately before the next synchronization code. Insert insertion bits so that they are placed in The number of inserted bits stuffing_len is such that the count value 221 of the counter 701 when the last information bit 631 of one frame is output is total_len and the number of check bits 632 to be output last is last_check_len.
stuffing_len = sync_period-last_check _len-(total_len mod sync_period)
It becomes. If the degenerate code is not used, the shortest information bit last_into_len is inserted from the normal information bit into_len (into_len – last_into_len), and then the bit is inserted to shift the check bit. There is a need to do. For this reason, more insertion bits are required than in_len−last_into_len + (into_len−last_into_len) mod sync_period bits compared to the case of using a degenerate code.

  The code string assembler 213 thus outputs the information bit 631 and the insertion bit to the output code string 205 via the switch 703, and finally switches to the check bit 713 and outputs it to the output code string 205.

Next, the moving picture decoding apparatus according to the present embodiment will be described.
FIG. 8 is a block diagram showing a configuration of a moving picture decoding apparatus corresponding to the moving picture encoding apparatus of FIG. The output code string 205 output from the moving picture encoding apparatus of FIG. 1 is input to the input decoding apparatus 800 as an input code string 205 ′ after passing through a transmission / storage system. In the present embodiment, the input decoding device 800 corresponds to the decoding device according to the present invention.

  Input decoding apparatus 800 performs error correction / detection decoding while switching the error correction / detection code based on FEC type identification signal 802 indicating the type of error correction / detection code from subsequent demultiplexer 811. A code string 801, a synchronization code detection signal 803, and an error detection signal 804 are output. The demultiplexer 811 receives the code string 801, the synchronization code detection signal 803, and the error detection signal 804, and separates and outputs the prediction residual code 841 and the motion compensation adaptive prediction information code 842.

  Prediction residual code 841 and motion compensation adaptive prediction information code 842 are input to first and second variable length decoders 806 and 810, respectively. The residual DCT coefficient 831 decoded by the first variable length decoder 806 is subjected to a series of processes of inverse quantization by the inverse quantizer 807 and inverse discrete cosine transform by the inverse DCT 808, and then an adder In 809, it is added to the motion compensated adaptive prediction signal 832 that is an output from the motion compensated adaptive predictor 801, and becomes a reproduced image signal 850. The reproduced image signal 850 is output outside the apparatus and recorded in the frame memory 820. The motion compensated adaptive prediction information decoded by the second variable length decoder 810 is input to the motion compensated adaptive predictor 801, and a motion compensated prediction signal 832 is generated.

  The above processing is processing for reproducing a moving image corresponding to the moving image encoding apparatus of FIG. 1. The processing performed by the inverse quantizer 807, inverse DCT device 808, adder 809, and frame memory 820 is respectively The implementation means of the inverse quantizer 107, the inverse DCT unit 108, the adder 109 and the frame memory 102 in FIG. Further, the processes of the first and second variable length decoders 806 and 810, the demultiplexer 811 and the input decoding apparatus 800 are the same as those of the variable length code shown in FIG. 1 except when an error is mixed in the code string. The processing is the reverse of that of the multiplexers 106 and 110, the multiplexer 111, and the output encoding device 200.

  FIG. 9 is a block diagram showing the configuration of the input decoding device 800. The input decoding apparatus 800 includes a synchronization detector 901 that detects a synchronization code in the input code string 205 ′, a counter 902 that counts the number of bits of the input code string 205 ′, and checks the input code string 205 ′ as an information bit 912. It comprises a code string decomposer 903 that decomposes into bits 913, an error correction / detection decoder 904, and an inserted bit remover 905.

The synchronization detector 901 detects the synchronization code only at the synchronization code insertion position based on the count value 911 of the counter 902. For example, if the synchronization code insertion position interval is sync_period, the count value 911 is bit_count, and the length of the synchronization code is sync_len,
0 <bit_count% sync_period ≦ sync_len
Synchronous detection is performed only when
Here, synchronization code detection may be performed in consideration of synchronization code errors.

  If the bit insertion unit 211 in the output encoding device 200 in FIG. 3 performs code string conversion by bit insertion so that the Hamming distance from the synchronization code is 2 * n + 1 apart in consideration of errors of n bits or less. Even if it is determined that the hamming distance from the true synchronization code is n or less as a synchronization code, detection of erroneous synchronization does not occur if errors of n bits or less are mixed.

  FIG. 10 is a block diagram showing the configuration of the code string decomposer 903. The input code string 205 ′ is switched between an information bit 1021 and a check bit 913 by a first switch 1002 controlled by a controller 1001 described later. When the information bit 1021 is output from the first switch 1002, the information bit 1021 is stored in the buffer 1004 for the information bit length via the second switch 1003. The counter 1005 counts the number of output bits from the second switch 1003. The count value 1023 of the counter 1005 is compared with the information bit length 1024 output from the error correction / detection code information output unit 1007 by the comparator 1006. When the two match, the counter 1005 is reset and error correction is performed. / FEC type identification signal 802 indicating the type of detection code is latched by latch circuit 1008, and information bit 912 is further output from buffer 1004. The output 914 of the latch circuit 1008 is input to the error correction / detection code information output circuit 1007 and also output to the error correction / detection decoder 904 shown in FIG.

As described above, the check bits of the error correction / detection code are shifted in position and are located between the information bits of the error correction / detection code at the rear of the code string 205. The controller 1001 performs control so that the check bit and the information bit subjected to the position shift are separated. When the input of the information bits of the error correction / detection code of one block is completed, the count value 1023 matches the information bit length 1024 in the comparator 1006. In response to this coincidence signal, the controller 1001 takes in the check bit length 1025 from the error correction / detection information output unit 1007 and calculates the position of the check bit included in the next information bit. If the count value 911 of the number of input bits of the code string 205 ′ when it is determined by the comparator 1006 to be coincident is bit_count and the check bit length is check_len, the check bit start position check_start is
check _start = (bit _count / sync_period + 1) * sync_period-check _len
The check bit end position check_end is
check _end = (bit _count / sync_period + 1) * sync_period
It becomes. The controller 1001 controls the switch 1002 so that the check bit 913 is output while the count value 911 is between check_start and check_end.

Since error correction / detection encoding is performed with a degenerate code at the end of one frame, special processing is performed. When the end of one frame is reached, the synchronization detector 901 outputs a signal 803 indicating that the synchronization code of the next frame has been detected. The controller 1001 receives this signal 803 and calculates the position of the check bit of the last error correction / detection code of the frame and the number of insufficient bits of information bits. The count value 911 of the number of bits of the input code string 205 ′ when the last error correction / detection code of one frame starts to be input is pre_last_count, and the count value when the input of the code string 205 ′ of one frame is completed 911 is total_count, the count value 911 at the time of processing is bit_count, the check bit length of the last error correction / detection code of one frame is last_check_len, and the check bit length of the previous error correction / detection code is pre_last_check_len And First, the excess and deficiency of information bits due to the fact that the error correction code is a degenerate code and that bit insertion has been performed is calculated. Of the information bits of the last error correction / detection code of one frame, the number of bits last_info_len included in the output code string 205 is:
last_inf0_len = total_count −last_check _len −pre _last_count −pre _last_check _len
It is. When last_info_len is shorter than the information length info_len of the error correction code, it is determined that the code is a degenerate code. Make up for the shortage of information bits. The output bit pattern from the inserted bit generator 1015 generates the same bit pattern as the inserted bit generator 705 in FIG. 7 of the encoder.

On the other hand, when last_info_len is longer than info_len, it is determined that the bit is inserted, and the information bit 912 is not output for the portion where the count value 1023 is equal to or greater than info_len. For inspection bits,
total _count −check _len <bit _count ≦ total _count
The switch 1002 is controlled so that the output code string 205 at this time is output as a check bit.

  The error correction / detection decoder 904 receives the information bits 912 and the check bits 913 output from the code string decomposer 903 and receives the FEC indicating the type of the error correction / detection code latched by the latch circuit 1008 in FIG. The error correction / detection code is decoded based on the type identification signal 914, and an error-corrected code string 915 and an error detection signal 804 are output.

  The error-corrected code string 915 is input to the insertion bit remover 905. The inserted bit remover 905 performs a process of removing the inserted bits for preventing the pseudo synchronization signal inserted by the bit inserter 211 of the output encoding device 200. As described above, since the bit insertion is performed only at the synchronous insertion position, the synchronous insertion position is determined based on the count value 911 of the counter 902.

  For example, it is assumed that the synchronization code word is shown in FIG. 5, and bit insertion is performed at the “0000...” Portion of the first sync_len bit of the synchronization code so that the Hamming distance from the synchronization code is 2 * n + 1 or more in the bit inserter 211. If it is performed, the number of sync_0_len− (2 * n + 1) bits of “1” (= n0) is counted from the synchronization code insertion position, and if n0 is 2 * n + 1 or less, 2 * n + 1− Delete n0 bits. However, since the inserted bit is determined to be “1”, when the bit determined to be the inserted bit by the inserted bit remover 905 is “0”, an error is mixed in the synchronous code insertion section. In this case, an error detection signal 804 is output.

  The code string 801 decoded by the input decoding apparatus 800 as described above is demultiplexed by the demultiplexer 811. This is an operation for separating and outputting multiplexed codewords as shown in FIG. The demultiplexer 811 operates in conjunction with the first and second variable length decoders 806 and 810.

  First, when the synchronization code detection signal 803 is input from the output decoding apparatus 800, the demultiplexer 811 moves to an initial state of frame processing. Next, the type of error correction / detection code for the picture header is output as the FEC type identification signal 802 indicating the type of error correction / detection code, the code string 801 is input, the picture header 302 is decoded, and an error occurs in the picture header. Judge whether there is any. When there is no error, the type of error correction / detection code for the prediction mode information 303 is output as the FEC type identification signal 802, the code string 801 is input, the prediction mode information is demultiplexed, and the second variable length Output to the decoder 810.

  When the second variable length decoder 810 decodes all prediction mode information, the second variable length decoder 810 outputs a signal indicating that to the demultiplexer 811. In response to this, the demultiplexer 811 outputs an FEC type identification signal indicating the type of error correction / detection code for the motion vector information 304 and starts demultiplexing the motion vector information 304. The demultiplexed motion vector information is output to the second variable length decoder 810 and decoded. When the decoding of all the motion vector information is completed, a signal indicating that is output from the second variable length decoder 810 to the demultiplexer 811. In response to this, the demultiplexer 811 receives the residual DCT coefficient 305. The FEC type identification signal indicating the type of error correction / detection code for is output, and the residual DCT coefficient 305 is demultiplexed and output to the first variable length decoder 806. The residual DCT coefficient 305 is decoded by the first variable length decoder 806.

  As described above, the type of error correction / detection code is determined based on the multiplexing rule determined in the same way as the output encoding apparatus 200 in the demultiplexer 811. Therefore, it is not necessary to include header information indicating the type of error correction / detection code in the output code string 205.

  In the error correction / detection decoder 904, it may be detected by the error detection code that an error is mixed in the input code string 205 ′. Further, as described above, the inserted bit remover 905 may detect an error of the inserted bit. In these cases, the error detection code 804 is output from the input decoding apparatus 800. Furthermore, it is also determined that an error has been mixed when a codeword that is not in the variable-length codeword table is detected in the variable-length decoding process. Also, when it is determined in the demultiplexing process in the demultiplexer 811 that there is a part that violates the multiplexing rule, it is determined that an error is mixed. In these cases, the input decoding apparatus 800 and the demultiplexer 811 perform the following processing so that the reproduced image is not greatly deteriorated.

  (1) If an error is detected in the residual DCT coefficient, the residual of that part is set to zero. When the intra coding mode is selected as the prediction mode, the reproduced image signal of the area may be predicted from the already reproduced frame or the reproduced image signal of the surrounding area.

  (2) When an error is detected in the prediction mode information or motion vector, when the prediction mode information or motion vector information of the area can be estimated from the prediction mode information or motion vector information of the surrounding area, they are used. If impossible, the reproduced image signal of the area is predicted from the already reproduced frame and the reproduced image signal of the surrounding area.

  (3) If an error is detected in the picture header, decoding it as it is may cause a very large image quality degradation. Therefore, the reproduced image of the previous frame is used as it is as the reproduced image of the current frame.

  In the above processes (1), (2), and (3), when variable length coding is used, if an error has spread to subsequent codes up to the next synchronization code, the same applies to that part. Perform the process.

  In the above description, an example in which the synchronization code detector 901 detects the synchronization code only at the synchronization code insertion position (every sync_period bits) is shown. However, depending on the transmission / storage medium, loss of bits or insertion of erroneous bits occurs. In some cases. In such a case, it is only necessary to detect the synchronization code other than the synchronization code insertion position and determine the position where the synchronization code is detected as the synchronization code insertion position.

(Second Embodiment)
Next, a second embodiment according to the present invention will be described with reference to FIGS. The moving picture coding apparatus and moving picture decoding apparatus according to the present embodiment have a transmission path / accumulation in which a part of the bit string is lost and the number of bits is reduced or the number of bits is increased by adding extra bits. Even if code strings are transmitted / stored on a medium, synchronization detection can be reliably performed.

  FIG. 12 is a block diagram showing the principle of synchronization detection processing when such bit addition / erasure is present. Here, as shown in FIG. 12A, a correct synchronization code is assumed to be composed of sync_0_len bit “0” and 1 bit “1”. Note that “x” in FIG. 12 is a bit other than the synchronization code.

  FIGS. 12B to 12E show how the synchronization code changes due to bit addition / erasure. Here, the maximum number of bits added / erased (Nid) is 1 bit. (B) is a summation in which 1-bit deletion has occurred in the bit string before the synchronization code, and the entire synchronization code is shifted forward by 1 bit. (C) shows a case where 1 bit is added in the bit string before the synchronization code, and the entire synchronization code is shifted backward by 1 bit. (D) shows a case where bit deletion has occurred in the synchronous code, and the back is shifted one bit forward from the bit missing position of the arrow in the figure. Further, (e) shows a case where 1 bit is added in the synchronization code, and 1 bit is added at the bit addition position indicated by an arrow in the figure, and the bit after that is shifted backward by 1 bit.

In order to correctly detect synchronization even when bit addition / erasure occurs, the bit strings shown in FIGS. 12B to 12D must also be determined as synchronization codes. As can be seen from FIG. 12, the number of “1” included in the range of ± Nid bits at the correct synchronization code insertion position is the maximum.
sync_0_len -3 * Nid
Is a bit. Therefore, synchronization detection is performed in the range of ± Nid bits of the synchronization code insertion position on the decoding side, and if the number of “1” included in this section is equal to or less than the above value, it may be determined as a synchronization code. Also, the encoding apparatus converts the code string so that the bit patterns of FIGS. 12B to 12D do not occur.

  Hereinafter, such an encoding device / decoding device will be described focusing on differences from the first embodiment.

  The video encoding device according to the second embodiment has the same overall configuration as the video encoding device according to the first embodiment, but the operation of the bit inserter 211 in FIG. 3 is different. FIG. 13 shows the operation of the bit inserter 211. That is, in the bit inserter 211 of the first embodiment, the bit insertion operation is performed only in the synchronization code insertion period, but in the bit inserter 211 in the second embodiment, bit addition / deletion of the maximum Nid bit is performed. In order to prevent the same bit pattern as the synchronization code from occurring even if it occurs, bit insertion is performed in the synchronization code insertion interval ± Nid bit interval.

If the count value 221 in FIG. 3 is total_len and the interval between the synchronization code insertion positions is sync_preriod, the bit inserter 211 is
total _len mod sync_period = sync_period−Nid
(Mod: remainder operation)
From
total_len mod sync_period = sync_0_len -1-3 * Nid
The number of “1” (= n0) in the interval is counted, and if n0 is less than 3 * Nid + 1, “1” of 3 * Nid + 1−n0 bits is inserted.

  FIG. 13 shows an operation example of the bit inserter 211 when sync_period = 12, sync_0_len = 9, and Nid = 1. In this example, since n0 = 2, 3 * Nid + 1−n0 = 2 bits of “1” are inserted.

  By performing bit insertion in this way, the number of “0” s in the synchronization code insertion interval ± Nid bits is guaranteed to be 3 * Nid bits or more, and can be uniquely identified from the synchronization code.

  On the other hand, the moving picture decoding apparatus according to the second embodiment has the same overall configuration as that of the first embodiment, but the operations of the synchronization detector 901 and the inserted bit remover 905 in FIG. 9 are different. . FIG. 14 shows the operation of the insertion bit remover 905.

  In other words, the synchronization detector 901 detects the synchronization code within a range of ± Nid bits before and after the synchronization code insertion position in order to detect synchronization even when bit addition / erasure of the maximum Nid bits occurs.

First, it is determined whether a synchronization code exists for each synchronization code insertion position. That is, when the count value 911 of the counter 902 is bit_count,
bit_count mod sync_period = sync_period-Nid
From
bit_count mod sync_period = sync_0_len −1 + Nid
The number of “0” s in between (= ns0) is counted, and if n0 is 3 * Nid or less, it is determined that there is a synchronization code in this interval.

  The operation example of FIG. 14 shows an example in the case of sync_period = 12, sync_0_len = 9, and Nid = 1. In this example, the number of “0” is counted when (bit_count mod sync_period) is between “11” and “8”. In the example of FIG. 14, since ns0 = 2, it is determined as a synchronous code.

Next, it is determined how many bits the code string has shifted due to the addition / erasure of bits in the synchronization code insertion section where it is determined that there is a synchronization code. In the case of sync_0_len bits as shown in FIG. 14, the shift amount is determined from the last “1” position. Specifically, the first “1” is searched from the start of the sync_0_len + 1 bit from the beginning of the synchronization code determination section, and what bit is present from the start of this synchronization code determination section (= first_1_pos bits) Based on
Number of shift bits = first_1_pos− (sync_0_len + 1 + Nid)
(Negative shift forward, positive shift backward)
Asking. In the example of FIG. 14, first_1_pos = 10.
Number of shift bits = 10− (9 + 1 + 1) = − 1
It can be seen that there is a 1-bit shift forward.

Unlike the first embodiment, the insertion bit remover 905 performs the insertion bit removal process in the interval of the synchronization code insertion position ± Nid bits. That is,
bit_count mod sync_period = sync_period-Nid
From
bit_count mod sync_period = sync_0_len -1-3 * Nid
The number of “1” (= n0) in the interval is counted, and if n0 is 3 * Nid + 1 or less, “1” of 3 * Nid + 1−n0 bits is removed.

  In the second embodiment, when it is possible to determine in some form the section where bit addition / erasure has occurred in the transmission path or the storage medium, the synchronization detection processing, bit insertion processing, and bit removal processing considering bit addition / erasure are: You may make it carry out only in the area.

  Note that in the video decoding apparatus according to the first embodiment described above, the synchronization detector 901 uses the second embodiment in order to perform synchronization detection corresponding to bit addition / erasure in the transmission path and the storage medium. Similarly, synchronization detection may be performed in a synchronization code insertion interval ± Nid bit interval. In this case, there is a possibility that pseudo-synchronization in which a part other than the synchronization code is erroneously determined as the synchronization code may occur. However, in a transmission path / storage medium in which bit addition / erasure is likely to occur, quality degradation of the decoded image due to synchronization detection error is suppressed. Can improve image quality.

  In addition, when it is possible to determine in some form the section where bit addition / erasure has occurred in the transmission path or storage medium, this processing is performed only in that section, and normal synchronization detection is performed in other sections. Good.

  Furthermore, in the first and second embodiments described above, synchronization may be further protected using information indicating the frame length (hereinafter referred to as frame length information). FIGS. 15, 16 and 17 show examples of code strings when the frame length information POINTER is used.

  In the example of FIG. 15, immediately after the synchronization code PSC, frame length information POINTER and an error correction / detection code check bit CHKP for protecting the frame length information POINTER follow. The frame length information POINTER records information indicating the number of bits of the previous frame, that is, the number of bits from the synchronization code of the previous frame to the synchronization code of the current frame.

  The encoding apparatus counts the number of code string bits in one frame, converts this into frame length information POINTER, and further performs error correction / detection encoding to generate check bits CHKP. Then, as shown in FIG. 15, a code string is generated immediately after the synchronization code of the next frame.

  On the other hand, in the decoding apparatus, after detecting the synchronization code by the same method as described in the first and second embodiments, the subsequent frame length information POINTER and the check bit CHKP are extracted from the code string, and the error is detected. Correction / detection decoding is performed to decode the frame length information POINTER. Then, the decoded frame length information POINTER is compared with a value (frame length count value) obtained by counting the number of bits from the synchronization code detected immediately before to the position of the current synchronization code. Check for false detections.

  If the frame length count value is different from the code length of the previous frame indicated in the frame length information POINTER, there is a possibility that an erroneous detection of the synchronization code has occurred, so that it is erroneously detected using the frame length information POINTER. Re-detection of the synchronization code. That is, it is assumed that there is a synchronization code that cannot be detected ahead by the number of bits indicated by the frame length information POINTER from the current synchronization code. In this case, the interval from the previous synchronization code to the current synchronization code is the interval from the previous synchronization code to the position indicated by the frame length information POINTER and the current synchronization code. The decoding process is performed by dividing the frame into two frames.

  However, if the number of bits indicated by the frame length information POINTER is greater than the number of bits from the previously detected synchronization code to the position of the current synchronization code, the frame length information POINTER is erroneous. The above-mentioned re-detection process is not performed.

  When the number of bits of the frame length information POINTER and the check bit CHKP is large, the synchronization code PSC, the frame length information POINTER, and the check bit CHKP may extend over a plurality of synchronization sections as shown in FIG. In this case, the bit length processing in the encoding device and the bit deletion processing in the decoding device for ensuring that the code string other than the synchronization code keeps a constant Hamming distance from the synchronization code includes frame length information POINTER and check bits. It may not be performed in a section where CHKP exists.

  In the example of FIGS. 15 and 16, when information indicating the type of the synchronization code is included in the latter half of the synchronization code PSC (such as the distinction between the frame synchronization code and the GOB synchronization code), not only the frame length information POINTER, The latter half of the synchronization code PSC may be protected with an error correction code. As a result, not only the position of the synchronization code but also its type can be detected accurately, and the tolerance to errors is further improved.

  In the example of FIG. 17, the frame length information POINTER and the check bit CHKP are placed at the end of the frame (immediately before the synchronization code of the next frame). In this case, in the decoding apparatus, after detecting the synchronization code of the next frame, the immediately preceding frame length information POINTER and check bit CHKP are extracted and error correction / detection decoding is performed, and the same processing as in FIGS. 15 and 16 is performed. Re-detect the synchronization code.

  In the example of FIG. 15, since the synchronization code exists only at the synchronization code insertion position, the frame length information POINTER may record a value obtained by dividing the number of bits of the frame by the synchronization code insertion interval (= sync_period bits). . Thereby, the frame length can be expressed by a small number of bits.

  In the first and second embodiments, an example in which hierarchical encoding is performed in accordance with the importance of information for encoding an error correction / detection code has been described. However, the same error correction / detection is performed within a frame. A code may be used, or an error correction / detection code may not be used. Even in such a case, a bit insertion process for maintaining a hamming distance of a code string other than the synchronization code as shown in the present embodiment above a predetermined value with the synchronization code, and a synchronization code detection process corresponding thereto Thus, the ability to detect synchronization is improved over the conventional method.

  In the above description of each embodiment, an example of transmitting / accumulating a moving image signal after performing high-efficiency compression coding has been shown. However, the present invention can also be applied to transmission / accumulation of still images, audio, data, and the like. Is possible. For example, when high-efficiency compression coding is performed on a still image signal using orthogonal transform, the error correction / detection code may be switched and used so as to more strongly protect the low frequency component of the transform coefficient. In a method of encoding speech by modeling speech as a drive source and a vocal tract filter, the error correction / detection code may be switched so as to strongly protect the pitch period and vocal tract parameters.

(Third embodiment)
Next, a third embodiment according to the present invention will be described. This embodiment differs from the first and second embodiments in that no error correction / detection code is used.

  FIG. 18 is a block diagram of a video encoding apparatus according to this embodiment. The same reference numerals are assigned to the portions corresponding to those in FIG. 1 and the differences from the first embodiment will be mainly described. In this embodiment, the configuration and operation of the output encoding device 200 are different. The basic operation of the multiplexer 111 is the same as that of the multiplexer 111 in FIG. 1, but only the multiplexed code string 201 and the synchronization code insertion request signal 203 are used because the error correction / detection code is not used. Is output.

  FIG. 19 is a block diagram showing a configuration of output encoding apparatus 200 in FIG. The output encoding apparatus 200 includes a counter 1701 that counts the number of bits of the output code string 205, a switch 1703 that switches the output code string 205, a switching controller 1704 that controls the switch 1703, and a stuffing bit that generates a stuffing bit. The generator 1705 is configured.

  FIG. 20 is a diagram illustrating an example of an output code string 205 generated by the output encoding device 200 of FIG. Code words corresponding to the output code string of FIG. 4 are represented using the same symbols. As in FIG. 4, the synchronization code PSC is inserted periodically, that is, only at any one of the synchronization code insertion positions indicated by arrows arranged at certain intervals (sync_period bits). 20 is different from FIG. 4 in that the check bit CHK of the error correction / detection code is not included. A stuffing bit STUFF is inserted into the last part of one frame of the output code string 205 so that the synchronization code PSC is inserted at the synchronization code insertion position. The number of stuffing bits STUFF is less than or equal to sync_period bits.

  Hereinafter, the configuration and operation of the output encoding apparatus 200 of FIG. 19 that generates such an output code string 205 will be described in detail.

  The counter 1701 is set to “1” when the synchronization code insertion request signal 203 is input from the multiplexer 111 and the first bit of the synchronization code 301 is input as the multiplexed code sequence 201, and all the bits of the synchronization code 301 are set. Is input, the synchronization code length sync_len is set. Thereafter, the counter 1701 counts up sequentially from the next bit of the synchronization code 301 until the bit immediately before the next synchronization code is output.

  The switching controller 1704 switches the switch 1703 to the multiplexed code string 201 side when the first bit of the synchronization code to the previous bit of the next synchronization code are input as the multiplexed code string 201. Control is performed so that the multiplexed code string 201 is output as the output code string 205.

  In the last part of one frame, bit insertion (bit stuffing) is performed so that the next synchronization code is inserted at the synchronization code insertion position. When the output of the multiplexed code string 201 for one frame is completed, the multiplexer 111 outputs the synchronization code insertion request signal 203 for the next frame. In response to this, the switching controller 1704 switches the switching unit 1703 to the stuffing bit generator 1705 side, and outputs the stuffing bit 1223 as the output code string 205. All of the stuffing bits 1223 may be “1”, “0”, or a specific pattern such as “0101...”.

Next, the moving picture decoding apparatus according to the present embodiment will be described.
FIG. 21 is a block diagram showing a configuration of a moving picture decoding apparatus corresponding to the moving picture encoding apparatus of FIG. The same reference numerals are assigned to the parts corresponding to those in FIG. 8 and the differences from the first embodiment will be mainly described. In this embodiment, the configuration and operation of the input encoding device 800 are different. Further, the signals input from the input decoding apparatus 800 to the demultiplexer 811 are only the code string 801 and the synchronization code detection signal 803, and there are no signals input from the demultiplexer 811 to the input decoding apparatus 800.

  FIG. 22 is a block diagram showing the configuration of input decoding apparatus 800. The input decoding apparatus 800 includes a synchronization detector 1901 that detects a synchronization code in the input code string 205 ′ and a counter 1902 that counts the number of bits of the input code string 205 ′.

  The counter 1902 is reset to “0” at the initial stage of decoding, and counts up the count value 1911 by “1” every time one bit of the input code string 205 ′ is input.

The synchronization detector 1901 detects the synchronization code only at the synchronization code insertion position based on the count value 1911 of the counter 1902. For example, if the synchronization code insertion interval is sync_period, the count value 1911 is bit_count, and the length of the synchronization code is sync_len,
0 <bit_count mod sync_period ≦ sync_len
Synchronous detection is performed only when Here, A mod B represents the remainder when A is divided by B. When the synchronization detector 1901 detects the synchronization code, it outputs a synchronization code detection signal 803.

  The input code string 205 ′ is output as it is from the code string 801 from the input decoding apparatus, and is input to the demultiplexer 811. Thereafter, the demultiplexing and decoding processes are performed in the same manner as the moving picture decoding apparatus in FIG.

  When the last stuffing bit STUFF of the frame is a predetermined bit pattern, the demultiplexer 811 determines whether the stuffing bit STUFF matches the predetermined pattern. It may be determined that there is an error in the column 205 ′, and processing for preventing the image quality deterioration from increasing as described in the moving image encoding apparatus shown in the first embodiment may be performed.

(Fourth embodiment)
Next, a fourth embodiment according to the present invention will be described.
The overall configuration of the video encoding apparatus according to this embodiment is the same as that of the video encoding apparatus of FIG. 18, and the operation of the output encoding apparatus is different from that of the third embodiment.

  FIG. 23 is a block diagram showing a configuration of output encoding apparatus 200 in FIG. When the same reference numerals are given to portions corresponding to those of the output encoding apparatus in FIG. 19 and the difference will be mainly described, a bit inserter 1211 for performing bit stuffing processing for preventing pseudo-synchronous codes is added. .

  In the bit inserter 1211, bit insertion for preventing the occurrence of pseudo synchronization is performed on the multiplexed code string 201. This is a process for preventing the synchronization code from being uniquely decoded when the output code string 205 has the same bit pattern as the synchronization code. For example, as shown in FIG. 5, when the sync code is composed of sync_0_len bit “0”, 1 bit “1”, and sync_nb_len bit “xxx × xxx” indicating the type of the sync code, the code other than the sync code Generation of pseudo-synchronization can be prevented by inserting “1” so that “0” does not continue for more than sync_0_len bits in the column.

The synchronization code is inserted only into the synchronization code insertion device. Therefore, the bit insertion operation for preventing the occurrence of pseudo synchronization may be performed only at the synchronization code insertion position. Therefore, it is determined whether bit insertion is necessary based on the count value 1221 indicating the total number of bits of the output code string 205. If the count value 1221 is total_len,
0 <total_len_mod_sync_period ≦ sync_0_len
The number of “1” s in the multiplexed code string 201 is counted in the interval, and if there is no “1” in this interval, “1” of 1 bit is inserted. Here, A mod B represents the remainder when A is divided by B.

  Further, in order to reduce the probability of erroneous detection of a synchronization code due to an error, bit insertion may be performed as follows.

  In order to detect a synchronization code even when an n-bit error is mixed in the synchronization code, a code word having a true synchronization code and a Hamming distance of n or less in an input encoding device of a moving image encoding device described later is a synchronization code. It is necessary to judge. However, if such a determination is made with the code string other than the synchronization code as it is, there may be a bit pattern whose synchronization code and Hamming distance are n or less in the code string other than the synchronization code. If it is in the insertion position, it is erroneously determined as a synchronization code.

Therefore, the bit insertion unit 211 performs bit insertion into the multiplexed code sequence 201 as follows, so that a code sequence other than the synchronization code at the synchronization code insertion position in the multiplexed code sequence 201 is a Hamming distance from the synchronization code. Are converted so as to be 2 × n + 1 or more apart. In particular,
0 <total_len_mod_sync_period ≦ sync_0_len− (2 × n + 1)
The number of “1” s in the interval (assumed to be n0) is counted. If n0 is less than 2 × n + 1, “1” of 2 × n + 1−n0 bits is inserted into the multiplexed code string 201.

  The code string 1222 after the bit insertion is performed is subjected to bit insertion (STUFF in FIG. 20) in the last section of the frame in the same manner as the output encoding apparatus in FIG. .

  Next, the moving picture decoding apparatus according to the present embodiment will be described. The overall configuration of the moving picture decoding apparatus is the same as that of the moving picture decoding apparatus in FIG. 21, and the operation of the input encoding apparatus 800 is different from that of the third embodiment.

  FIG. 24 is a block diagram showing the configuration of the input decoding apparatus 800. A bit remover 1905 that adds the same reference numerals to the parts corresponding to those of the input decoding apparatus in FIG. 22 and that mainly describes differences from the third embodiment is added.

  The input code string 205 ′ is input to the insertion bit remover 1905 and performs processing for removing the insertion bits for preventing the pseudo-synchronous code inserted by the bit insertion unit 1211 of the output encoding device in FIG. As described above, since the bit insertion is performed only at the synchronization code insertion position, the synchronization code insertion position is determined based on the count value 1911 of the counter 1902.

  For example, it is assumed that the synchronization code is the code word shown in FIG. 5, and bit insertion is performed at the first “0000...” Portion of the synchronization code so that the Hamming distance from the synchronization code is 2 × n + 1 or more in the bit inserter 1211. If it is performed, the number of sync_0_len− (2 × n + 1) bits of “1” is counted from the synchronization code insertion position, and if n0 is less than 2 × n + 1, 2 × n + 1−n0 bits are deleted.

  Here, since the inserted bit is defined as “1”, when the bit determined to be the inserted bit is “0”, it is considered that an error has been mixed in the synchronous code insertion section. In this case, an error detection signal (not shown) may be output to the demultiplexer 811 and a process that does not cause a large deterioration in the reproduced image may be performed as described in the first embodiment.

  In the bit insertion process in the bit inserter 1211 of FIG. 23, a predetermined number of inserted bits may be inserted into all the synchronization code insertion sections other than the synchronization code. 25 shows an example of the output code string 205 when such a bit insertion process is performed. In the drawing, SB indicates a bit inserted.

  For example, as shown in FIG. 5, when the sync code is composed of sync_0_len bit “0”, 1 bit “1”, and sync_nb_len bit “xxxx” indicating the type of the sync code, sync_0_len bits from the beginning of the sync code insertion interval A 1-bit insertion bit SB is inserted at a predetermined position in the interval.

  The insertion bit SB may always be “1”. Further, the insertion bit SB may be adaptively determined so that the number of “1” in the section becomes one or more according to the bit pattern of the section of sync_0_len bits from the beginning of the synchronization code insertion section.

  Furthermore, by making the inserted bit SB an odd parity in the interval of sync_0_len bits from the beginning of the synchronization code insertion interval, it is possible to avoid the appearance of the same bit pattern as the synchronization code and to detect errors mixed in this bit pattern. It is possible.

  FIG. 25B shows an output code string subjected to such bit insertion processing. In this example, a 1-bit insertion bit SB is inserted in the first part from the synchronization code insertion position. The insertion bit SB is determined so that the number of “1” s in the section obtained by combining this and the next bit from the sync_0_len−1 bit is necessarily an odd number. For example, in the example on the left side of FIG. 25B, the insertion bit SB is “1”. In the example on the right side of FIG. 25 (b), since the inserted bit SB is “1” even if all the sections of the sync_0_len−1 bit from the bit next to the inserted bit SB are “0”, the synchronization code is inserted. A “1” of 1 bit or more is always included in the section, and the same bit pattern as the synchronization code does not occur. Further, since the inserted bit SB also functions as a parity check bit, it is possible to detect a bit error mixed in this section.

  Further, the inserted bit SB may be an odd parity check bit of all bits up to the next synchronization code insertion position. However, the insertion bit SB is always set to “1” in order to avoid the appearance of the same bit pattern as the synchronization code only when the sync_0_len−1 bits from the SB-order bit of the insertion bit are all “0”. Thereby, it is possible to perform error detection by parity check of all bits.

  In order to reduce the probability of erroneous detection of a synchronization code due to an error, it is desirable to insert a larger number of bits. For example, in order to correctly detect synchronization even when an error of n bits is input, 2 × n + 1 bits of “1” are inserted at predetermined positions in this interval.

  In the present embodiment, the operation of the bit remover 1905 in FIG. 24 is also different from the operation of the bit inserter 1211 described above. That is, the bit remover 1905 performs a process of deleting the inserted bit SB at a predetermined position where the bit insertion is performed by the bit inserter 1211.

  Here, when the insertion bit SB is always “1”, when the bit at the bit insertion position in the input code string 205 ′ is “0”, it is determined as a bit error, and an error detection signal (illustrated) No) may be output to the demultiplexer 811 and processing for preventing the decoded image from being significantly degraded may be performed.

  In the first to fourth embodiments, the multiplexing in the multiplexer 111 is performed by combining the prediction mode information 303, the motion vector information 304, and the residual DCT count 305 in units of encoded frames as shown in FIG. Although an example of multiplexing has been shown, as shown in FIG. 26, the prediction mode information 303, motion vector information 304, and residual DCT count 305 may be multiplexed so as to be integrated in units of coding regions (for example, macroblocks, GOB, etc.). Good. In this case, different error correction / detection codes may be used for the picture header 302 and other information, or the same error correction / detection code may be used. Alternatively, an error correction / detection code may be used only for the picture header, or an error correction / detection code may be used for a partial code string of a predetermined number of bits of each frame, or an error correction / detection may be performed. It is not necessary to use a code at all.

  Also, it is possible to multiplex not only in units of frames (pictures) but also in partial areas within the frames or in units of layers in which a plurality of frames are combined, and by inserting a synchronization code for each of these units of multiplexing (layer units) Good.

  FIG. 28 shows an example of such multiplexing. In the example of FIG. 28, multiplexing is performed for each of four layers of a macro block in which a plurality of encoded blocks are grouped, a GOB in which a plurality of macro blocks are grouped, a picture (frame), and a session in which a plurality of pictures are grouped. Among these, the session, picture, and GOB layers use respective synchronization codes (SSC, SEC, PSC, and GSC in the figure). Different codes are used for SSC, SEC, PSC, and GSC, respectively, so that it is possible to distinguish which layer synchronization code is detected. In the case of using the synchronization code as shown in FIG. 5, it is only necessary to distinguish these synchronization codes by the sync_nb_len bit portion indicating the type of the synchronization code.

  Even when such multiplexing is performed, processing similar to the frame synchronization code in the above-described embodiment may be performed on some or all of the synchronization codes of the session, picture, and GOB. FIG. 29 shows an example of an output code string subjected to such processing. As shown in the figure, a stuffing bit STUFF is inserted before PSC and GSC, and SSC, PSC and GSC are inserted at the synchronization code insertion positions indicated by arrows in the figure. For this reason, the detection accuracy of each synchronization code is improved as described for the frame synchronization code PSC in the above-described embodiment.

  It is also possible to add length information similar to the frame length information POINTER in FIGS. 15, 16, and 17 to each synchronization code of session, picture, and GOB. As shown in FIGS. 15 and 16, when the frame length information POINTER is protected by the error correction / detection code, not only the frame length information POINTER but also the sync_nb_len bit portion indicating the type of the synchronization code In addition, by using the error correction / detection code, the probability that not only the position of the synchronization code but also the type thereof can be detected correctly is improved. In addition, some or all of the header information (SH, PH, GF in the figure) of the session, picture, and GOB may be combined and protected using an error correction / detection code. Will also improve.

  When performing stuffing processing for preventing pseudo-synchronous codes as in this embodiment, it is possible to make the synchronous code insertion interval sync_period less than or equal to the length of the synchronous code by performing the following processing.

First, the process in the output coding amount of the moving image coding apparatus will be described. Here, as shown in FIG. 5, the synchronization code is a code word composed of sync_0_len bit “0” and 1 bit “1”. 23, if the count value 1221 indicating the number of bits output from the bit inserter 1211 is total_len, the remainder obtained by dividing total_len by the synchronization code insertion interval sync_period is the first “0” of the synchronization code. When the value obtained by subtracting 1 from the number of bits sync_0_len is divided by the sync_period, that is,
total_len mod sync_period
= (Sync_0_len -1) mod sync_period (1)
Then, the number of “1” s in the output bits from the current output bit to (sync — 0_len−1) bits before (when n1) is counted, and if there is no “1” (that is, n1 = If it is 0) Insert a 1-bit "1".

  FIG. 33A shows an example of an output code string obtained by performing such processing. In the drawing, a downward arrow indicates a synchronization code insertion position, and the synchronization code includes 23 bits of “0” (that is, sync — 0_len = 23) and 1 bit of “1”. In the illustrated example, the synchronization code insertion interval sync_perod is 8, which is shorter than the length of the synchronization code (= 24 bits).

  In the figure, intervals 1 to 4 indicate intervals for counting n1 described above. The number n1 of “1” is sequentially counted in each section, and if n1 = 0, a stuffing bit is inserted into the next bit in the section. In section 1, n1> 0, so stuffing is not necessary. Since n1 = 0 in section 2, 1-bit stuffing bit 3301 is inserted next to this section. In section 3, since stuffing 3301 is inserted, n1 = 1, so that it is not necessary to insert stuffing bits.

  By performing the bit stuffing process as described above, the same bit pattern as that of the synchronization code is eliminated in the portion other than the synchronization code in the output code string, so that pseudo synchronization does not occur.

  On the other hand, in order to reduce the probability of erroneous detection of a synchronization code due to a transmission path error, bit insertion may be performed as follows.

  In order to correctly detect a synchronization code even when an n-bit error is mixed in the synchronization code, the Hamming distance between the portion other than the synchronization code in the output code string and the synchronization code is 2 × n + 1 or more in the bit insertion 1211 The bit insertion process may be performed so that

This is because the remainder obtained by dividing the count value 1221 total_len indicating the total number of bits of the output code string 205 in FIG. 23 by the synchronization code insertion interval sync_period subtracts 2 × n + 1 from the first bit number sync_0_len of the synchronization code. When the value is equal to the remainder divided by sync_period, that is,
total_len mod sync_period
= (Sync_0_len− (2 × n + 1)) mod sync_period (2)
Then, the number of “1” s (n1) in the output bits from the current output bit to (sync — 0_len− (2 × n + 1)) bits before is counted, and the number of “1” is (2 × n + 1), ie
n1 <2 × n + 1
In this case, (2 × n + 1−n1) bit “1” is inserted.

  In the case of using a synchronization code starting from “0” of a plurality of bits as shown in FIG. 5, if the number of “1” s in the bit string immediately before the synchronization code is small, synchronization erroneous detection may occur at this portion. In order to prevent this, the bit insertion in the last section of the frame is performed so that the number of bits of “1” in the section of the sync_period bit from the synchronization code to the immediately preceding synchronization code insertion position is 2 × n + 1 bits or more (FIG. 20). STUFF) may be output.

  For this, an STUFF including “1” of 2 × n + 1 bits or more may be used, or the STUFF may be determined according to the output code string. That is, STUFF may be determined so that the number of “1” bits of the sync_period bits immediately before the synchronization code in the output sequence including STUFF is 2 × n + 1 bits or more.

  FIG. 33B shows an example of an output code string obtained by performing such processing. In the figure, intervals 1 to 4 indicate intervals for counting n1 described above. In each section, the number of “1” s is sequentially counted as n1, and if n1 <2 × n + 1, a stuffing bit is inserted into the next bit of the section. Since n1 = 1 in section 2, stuffing bit 3311 of (2 × n + 1) −1 = 2 bits is inserted next to this section. In section 3, since stuffing 3311 is inserted, n1 = 3, so that it is not necessary to insert a stuffing bit.

  Further, STUFF is determined as follows to prevent erroneous detection of the synchronization code in the portion immediately before the synchronization code. The bit immediately before STUFF is 3312. Since the number of “1” s between the sync_period bits (section 5) from the synchronization code insertion position immediately before this bit 3312 to the synchronization code insertion position immediately after is only 1 bit, a plurality of “0” s as shown in FIG. When continuous synchronization codes are used, there is a possibility that erroneous synchronization detection occurs at this portion. For this reason, the position where the synchronization code is inserted is shifted to the next synchronization code insertion position, and STUFF 3313 including many “1” s is output. Accordingly, since the sync_period bit section (section 6) immediately before the synchronization code includes “1” of 2 × n + 1 bits or more, erroneous synchronization detection can be prevented.

  By performing the bit stuffing process as described above, the hamming distance from the synchronization code in the portion other than the synchronization code in the output code string can be set to 2 × n + 1 or more, so the probability of synchronization error detection decreases.

  Next, processing in the input decoding device of the moving image decoding device will be described. In the bit remover 1905 of FIG. 24, if the count value 1905 indicating the number of bits of the input code string is total_len, when the total_len reaches a value satisfying the condition of 1, from the input bit at that time (sync_0_len − 1) Count the number of “1” s in the input bits up to the previous bit (assuming n1). If there is no “1”, that is, if n1 = 0, delete 1 bit.

In order to detect a synchronization code even when an n-bit error is mixed in the synchronization code, the bit inserting unit 1211 causes the Hamming distance force between the portion other than the synchronization code in the output code string and the synchronization code to be 2 × n + 1 or more. When the bit insertion processing is performed on the above, the following processing may be performed. When total_len reaches a value satisfying equation (2), the number of “1” s in the output bits from the current input bit to (sync — 0_len− (2 × n + 1)) bits before is counted (assumed as n1). And the number of “1” is less than (2 × n + 1), that is,
n1 <(2 × n + 1)
(2 × n + 1−n1) bits are deleted.

  By performing the above processing in the output encoding device and the input decoding device, the synchronization code insertion interval sync_period is set to a short number of bits less than or equal to the length of the synchronization code, thereby reducing the number of bits of the stuffing but STUFF, Encoding efficiency is improved. In particular, when the length of the synchronization code is long or when many synchronization codes are inserted, the degree of improvement in coding efficiency by reducing the number of bits of the stuffing bits STUFF is large. For example, in a method of dividing a screen into one or a plurality of macroblocks or macroblock lines and inserting a synchronization code for each unit, such as GOB / slice in moving image encoding, many synchronization codes are inserted. Therefore, the degree of encoding efficiency due to the reduction in the number of bits of STUFF is further increased.

  When multiplexing a plurality of layer structures as shown in FIG. 28, synchronization codes having different lengths may be used depending on the layers.

  FIG. 34 (a) shows an example of such a synchronization code. Of the four types of synchronization codes, SSC, SEC, and PSC are each composed of 23 bits of “0”, 1 bit of “1”, and 8 bits indicating the type of synchronization code, for a total of 32 bits. On the other hand, the synchronization code GSC of the GOB layer is a 17-bit synchronization code composed of 16 bits “0” and 1 bit “1”, and is a codeword shorter than other synchronization codes.

  The reason why only GSC is used as a short codeword is that a GOB is a coding unit composed of one or a plurality of macroblocks (MB) and is divided into small areas in the screen. This is because the number of codes is larger than that of other synchronization codes, and the code amount of the output code string can be reduced by shortening the synchronization codeword length. In addition, if the code amount is the same, more GSC can be output, and the screen can be divided into smaller GOB areas and encoded, resulting in a transmission line error. The quality of the playback image is improved.

  The process for preventing pseudo-synchronization as described in the fourth embodiment, that is, bit stuffing processing that prevents the same bit pattern as the synchronization code from occurring in the code string other than the synchronization code is performed. May be. Bit stuffing processing for reducing the probability of erroneous detection of a synchronization code due to a transmission path error, for example, the same bit pattern as a synchronization code having a long bit length (SSC, SEC, PSC in the example of FIG. 34A) is generated If bit stuffing processing is performed so that the same pattern as the shortest synchronization code (GSC in the example of FIG. 34 (a)) does not occur even for a bit string that is guaranteed not to exist, all synchronization codes It is possible to prevent the same bit pattern from occurring. This process may be performed on the code sequence of all layers, or may be performed on the code sequence of a layer lower than the layer using the shortest code (GOB layer and macroblock layer in the example in the figure). However, the processing may be performed on a code string of a layer (picture layer, GOB layer, macroblock layer) below the layer one layer above that layer. Furthermore, this process may be performed only on a code string of a predetermined layer.

  In order to make it easy to identify synchronization codes having different lengths even if a transmission path error occurs, the synchronization code word and the processes before and after the synchronization code word may be performed as follows.

  (i) When using a synchronization code consisting of a plurality of bits “0” followed by “1”, the relative position of the long codeword and the short codeword as viewed from the synchronization code insertion position of “1” is It may be different. In the example of FIG. 34 (b), the PSC “1” 3411 and the GSC “1” 3412 are in different positions, and the bits of the same amount in another synchronization code (3413 for 3411 and 3414 for 3412) are Both are “0”. By doing so, the Hamming distance between the re-synchronization code and its subsequence is increased, so that different synchronization codes can be easily identified even if a transmission path error occurs.

  (ii) A stuffing bit may be inserted before a synchronization code having a short length. For example, by inserting a stuffing bit 3401 composed of one or a plurality of “1” s before a short GSC as shown by 3401 in the figure, the Hamming distance between the OSC and another subsequence of the synchronization code is increased. be able to.

  (iii) A stuffing bit may be inserted after the short synchronization code. For example, the bit insertion 3402 may be performed after the GSC so that the Hamming distance to the portion for identifying the type of the synchronization code in the long synchronization code is increased.

(Fifth embodiment)
Next, a fifth embodiment according to the present invention will be described.
The overall configuration of the video encoding device and the video decoding device according to this embodiment is the same as that of the first embodiment, and the first and last synchronization intervals of the output encoding device 200 and the input decoding device 800 are the same. The processing in the part is different from the previous embodiments.

  FIGS. 27A, 27B, and 27C are diagrams illustrating an example of an output code string 205 from the moving image encoding apparatus according to the present embodiment. The output code string 205 includes a part 2701 of the code string of the previous frame (frame n−1) after the synchronization code PSC, and a boundary 2703 between the code string 2701 and the code string of the current frame (n frame). There is pointer information 2702 (SA) indicating the boundary of the multiplexed code sequence (in other words, the start point of the code sequence of the current frame), and accordingly, the last stuffing bit (STUFF in FIG. 4) of one frame is lost. This is different from the output code string of FIG.

  The output encoding device 200 in the moving image encoding device checks the number of bits resid_bit of the remaining code string of the frame at each synchronization code insertion position. If the sum of the number of bits of resid_bit, synchronization code PSC, and pointer information SA is less than the synchronization code insertion interval sync_period bits, before outputting the remaining code string of the frame in the output code string 205, the synchronization code PSC Is output. Next, pointer information SA (in this case, represents resid_bit) is output, and then the remaining code string 2701 is output. Thereafter, the code string of the next frame is output.

  In the input encoding device 800 in the moving image decoding device, the synchronization code is detected at each synchronization code insertion position. When the synchronization code is detected, the pointer information SA and the remaining information of the frame follow. The process is performed as it is continued.

  The boundary part between frame n-1 and frame n in FIG. 27 will be described as an example. After the decoding process up to 2704 immediately before the synchronization code PSC is completed, a synchronization code is detected in the subsequent synchronization code insertion section, and synchronization is performed. If a code is detected, the pointer information 2702 is then decoded to determine how many bits there are in the code sequence of frame n-1. Based on this, the number of bits indicated by the pointer information is extracted from the code string immediately after the pointer information (up to 2703 in FIG. 27), and the code string 801 is output as a result following this 2704. The subsequent code string (from 2703 in FIG. 27) is processed as the next frame, that is, frame n.

  In the present embodiment, as shown in FIG. 27A, error correction / detection encoding may be performed on a part or all of the output code string. In this case, all types of error correction / detection codes may be the same or different.

  Further, as shown in FIG. 27B, error correction / detection encoding may not be performed.

  Furthermore, as shown in FIG. 27C, frame length information POINTER indicating the number of code string bits of one frame as shown in FIG. 15 or FIG. 16 may be inserted. In this case, the frame length information POINTER may represent the number of bits from the synchronization code PSC of the frame to the synchronization code PSC of the next frame.

  When error correction / detection encoding is performed as shown in FIG. 27A, error correction / detection encoding of the portion from the synchronization code PSC to the next check bit CHK is performed by using the pointer information SA and the remaining frame n-1. The error correction / detection code is performed as a single information bit by combining the code string 2701 and the code string of frame n after 2703.

  The pointer information SA may be information that has been subjected to error correction / detection coding. In this case, the error correction / detection coding may be performed by combining the synchronization code PSC (or part thereof), the frame length information POINTER, and the pointer information.

  Next, a specific example of the stuffing bit STUFF will be described.

  FIGS. 30A and 30B are diagrams showing examples of code tables of stuffing bits STUFF as specific examples of the above-described stuffing bits STUFF. Each of FIGS. 30A and 30B is characterized in that it can be uniquely decoded from the reverse direction of the output code string, and thereby the start position of the stuffing bit STUFF can be uniquely specified. Therefore, by comparing the decoding end position of the code string immediately before the stuffing bit STUFF and the start position of the stuffing bit STUFF, an error mixed in the code string can be detected, and a code for decoding backward from the synchronous code When used in the conversion method, the starting point of backward decoding can be specified.

  Further, the stuffing bit STUFF shown in the code table of FIGS. 30A and 30B always has “0” as its first bit, and error detection by simple decoding as described later is possible.

  FIG. 31 shows an example of the decoding process of the code string including the stuffing bit STUFF shown in the code table of FIGS. 30 (a) and 30 (b). FIG. 31 shows an example of the stuffing bit immediately before the synchronization code insertion position, but it is also possible to perform the same processing by inserting a stuffing bit bit immediately before any other synchronization code insertion position. . In FIG. 31, arrows 3101 to 3103 are examples of the decoding end position of the code string (indicated by “xxx...”) Immediately before the stuffing bit STUFF when decoding is performed in the forward direction. Indicates the decoding end position. If no error is mixed in the code string and decoding is performed normally, the decoding end position of the code string immediately before the stuffing bit STUFF matches the start position of the stuffing bit STUFF as indicated by an arrow 3101. .

  On the other hand, when an error is mixed in the code string, the decoding end position of the code string immediately before the stuffing bit STUFF is shifted from the start position of the stuffing bit STUFF as indicated by arrows 3102 and 3103. In such a case, it is determined that there is an error in the code string.

  In the decoding apparatus, when decoding of the code string immediately before the stuffing bit STUFF is completed, the stuffing bit STUFF is read up to the next synchronization code insertion position, which is the code table shown in FIGS. 30 (a) and 30 (b). Determine if it matches the sign. If the stuffing bit STUFF does not match any code in the code table, it is determined that an error has occurred.

  When determining a match between the stuffing bit STUFF and the code table, an error of a small number of bits may be allowed. By doing so, it is possible to reduce erroneous detection of errors when errors occur in the stuffing bit STUFF itself.

  The code table of FIG. 30A always starts with “0” and the subsequent bits are “1”. Therefore, error detection may be performed by determining only whether the next bit of the decoding end position of the code string immediately before the stuffing bit STUFF is “0”, or the first “0” and the following Error detection may be performed from only a few “1” s. In this way, the error detection accuracy is slightly reduced, but the amount of processing required for decoding is reduced. In this way, when a code table starting from a specific bit pattern consisting of specific bits or a plurality of bits is used for all stuffing bits STUFF, the decoding process can be simplified.

  Further, the stuffing bit STUFF shown in the code table of FIGS. 30A and 30B includes many “1” bits, and a synchronization code including many “0” and a part thereof as shown in FIG. Since the hamming distance is long, there is an advantage that the probability of occurrence of pseudo-synchronization is low. Specifically, in the code table of FIG. 30A, since only the first bit of the stuffing bit STUFF is all “0” and all other bits are “1”, the synchronization code is all “0”. The hamming distance with a part thereof is (the length of the stuffing bit STUFF-1). In the code table of FIG. 30B, only the first and last bits of the stuffing bit STUFF are “0”, and all other bits are “1”. Therefore, the Hamming distance between the synchronization code and a part thereof Is (the stuffing bit STUFF length-2). In this way, by selecting the hamming distance between the stuffing bit STUFF and the synchronization code and a part thereof to a predetermined value or more, for example, (the length of the stuffing bit STUFF−2) or more, even if an error is mixed in the code string, the pseudo synchronization code Is unlikely to occur.

  This effect will be described with reference to FIG. FIGS. 32 (a-0) and (b-0) are code strings obtained by using normal stuffing bits (all bits are “0”) and stuffing bits STUFF shown in the code table of FIG. 30 (a), respectively. An example is shown, and (a-1) and (b-1) show examples when a 1-bit error is mixed in (a-0) and (b-0), respectively. As can be seen from FIG. 32 (a-1), only one bit error is mixed in a normal stuffing bit in which all bits are “0”, and as shown by the broken line in (a-1), Since the same bit pattern is generated, pseudo synchronization occurs. On the other hand, the stuffing bit STUFF shown in the code table of FIG. 30A does not become the same pattern as the synchronous code even if an error is mixed as shown in FIG. do not do.

  As described above, the stuffing bit according to the present embodiment has an advantage that an error in the code string can be easily detected, and even if an error is mixed in the code string, a pseudo-synchronous code is hardly generated and has a strong error resistance.

  Further, the stuffing bit according to the present embodiment can be uniquely decoded from the reverse direction, and the start position, that is, the end position of the code string immediately before the stuffing bit bit STUFF can be specified, so that the information code string is reversed from the forward direction. In the case of a codeword that can also be decoded from the direction, the code string immediately before STUFF can be decoded from the reverse direction, as indicated by an arrow 3104 in FIG.

  In the embodiment described above, the stuffing bit STUFF may be determined as follows.

  (1) When the sync code includes “0” of the sync_0_len bit as shown in FIG. 5, the stuffing bit STUFF or at least all the bits at the sync code insertion position are set to “1”, thereby The Hamming distance between the “0” portion and the stuffing bit STUFF can be separated. Therefore, by doing this, it is possible to reduce the probability that an error is mixed in the stuffing bit STUFF and pseudo synchronization occurs.

  (2) The stuffing bit STUFF may be a code word indicating the length. In the decoding apparatus, the length of the STUFF is determined from the point where the decoding of the code string other than the stuffing bit STUFF is completed, and the STUFF is decoded to decode the STUFF length information. In this case, if the two do not match, it can be determined that an error is mixed in the code string.

  The code word of the stuffing bit STUFF may be a binary representation of the length. For example, when STUFF is 5 bits, it is good also as "00101" which expressed "5" in binary number. Alternatively, a binary representation of the value of the complement of “1” or “2” may be used as the code word of the stuffing bit STUFF, thereby reducing the number of “0” bits in the STUFF. As described in (1), the occurrence of pseudo synchronization can be suppressed.

  (3) When encoding is performed using a codeword that can be decoded not only in the forward direction but also in the reverse direction, the decoding apparatus decodes the stuffing bit STUFF in the reverse direction from the end point of the frame, and the start point It is necessary to know (the boundary point between STUFF and another code word). In such a case, for example, STUFF may be defined as a code word starting with 1 or multiple bits of “0”, such as “01111111”, and the remainder being “1”. Thus, if the STUFF is decoded from the reverse direction and a position having “0” is found, the point can be uniquely determined as the start point of the STUFF. In this example, the bits other than the first part of the stuffing bit STUFF are “1”, and the probability of occurrence of pseudo-synchronization is reduced as described in (1).

  (4) The stuffing bit STUFF may be a check bit of an error correction / detection code of a part or all of the output code string, a parity check bit, or the like. Thus, it is possible to correct / detect bit errors mixed in the output code string.

  As in the above example, by generating the stuffing bit STUFF according to a predetermined rule, the decoding device checks the stuffing error STUFF in the input code string against the generation rule, and if it violates the generation rule If it is determined, it can be determined that an error is mixed in the input code string. As a result, it is possible to improve the quality of the reproduced image when an error is mixed in the input code string by performing processing so that the reproduced image does not significantly deteriorate in the video decoding device.

  Furthermore, in the above embodiment, the synchronization code insertion interval sync_period may be determined as follows.

  (1) When an error correction / detection code is used, the synchronization code insertion interval sync_period is the minimum number of bits for which synchronization detection is performed by the decoding apparatus, that is, the sum of the length of the synchronization code and the maximum value of the check bits of the error correction / detection code The above is enough. Since the average value of the number of bits of the last stuffing bit STUFF in the frame is sync_period / 2, the number of bits of the stuffing bit STUFF is reduced and the coding efficiency is improved by taking the sync_period as the minimum bit capable of synchronous detection. To do.

  (2) When no error correction / detection code is used, it is sufficient that the synchronization code insertion interval sync_period is equal to or greater than the minimum number of bits for detecting synchronization in the decoding apparatus, that is, the length of the synchronization code. Since the average number of bits of the last stuffing bit STUFF in the frame is sync_period / 2, the number of bits of the stuffing bit STUFF is reduced and the coding efficiency is improved by taking the sync_period as the minimum bit that can be detected synchronously. .

  (3) As shown in FIGS. 15, 16, 17 and 27, when using frame length information POINTER, the synchronization code insertion interval sync_period may be shorter than the length of the synchronization code. Thereby, the number of bits of the stuffing bit STUFF is reduced, and the encoding efficiency is improved.

  (4) When transmission / accumulation is performed by dividing into packets or cells having a predetermined interval in the transmission path or storage medium, the synchronization code insertion interval sync_period is adjusted to the packet or cell interval or a divisor of the interval. It may be. As a result, the beginning of the packet or cell always becomes the synchronization code insertion position, so that it is possible to detect the synchronization code even when a packet or cell occurs due to packet loss or cell loss.

  (5) The synchronization code insertion interval sync_period is preferably shorter than the minimum necessary number of bits of one frame. Thereby, the number of bits of the stuffing bit STUFF is reduced, and the encoding efficiency is improved.

(Sixth embodiment)
Next, a sixth embodiment according to the present invention will be described.
FIG. 35 is a diagram illustrating an example of an output code string of the video encoding device in the present embodiment. In this output code string, bit insertion processing as described in the above-described actual travel example is performed in order to reduce the false detection probability of the synchronization code due to an error. In addition, information such as header information is included at a predetermined position or a predetermined position relative to the synchronization code.

  FIG. 35A shows a code string before the bit insertion process, and FIG. 35B shows an output code string after the bit insertion process. In the figure, hatched portions 3201, 3202, 3261, and 3262 are information to be placed in a predetermined amount (a position that is determined relative to the synchronization code), and white arrows 3211 and 3212 indicate the information. It is the position to put. The code string information 3261 and 3262 in FIG. 35B correspond to the code string information 3201 and 3202 in FIG. 35A, respectively, and in some cases, when converting the code string (a) to the code string (b), These pieces of information may also be converted (ie, conversion from information 3201 to information 3261 and conversion from information 3202 to information 3262).

  353 in FIG. 35B is a bit inserted by the bit insertion process. This bit insertion process shifts the bit string following the inserted bit backward, so that a part of the code string immediately before the information is moved backward so that the information to be entered at the predetermined position enters the fixed position. Do. For example, if the total number of inserted bits from the synchronization code 3205 immediately before the information 3201 is Ns1, the Ns1 bit indicated by the symbol 3221 in FIG. 35A immediately before the information 3201 is immediately after the information 3201. What is necessary is just to move to the part of the symbol 3231 in FIG.35 (b).

  If the information 3201, 3202 includes information such as a pointer indicating a specific position in the code string, a process of converting this may be performed. Specifically, for example, when information indicating the position indicated by the arrow 3241 is included in the information 3201, the information 3261 indicates the position indicated by the arrow 3251 behind the position by the number Ns1 of insertion bits. The information indicating the position of is converted.

The block diagram which shows the structure of the moving image encoder which concerns on the 1st and 2nd embodiment of this invention. The figure which shows the rule of the multiplexing in the multiplexer in the moving image encoder of FIG. The block diagram which shows the structure of the output encoding apparatus in the moving image encoding apparatus of FIG. The figure which shows the example of the output code sequence from the moving image encoder of FIG. Diagram showing examples of synchronization codes FIG. 3 is a block diagram showing a configuration of an error correction / detection switching encoding unit in the output encoding apparatus of FIG. The block diagram which shows the structure of the code sequence assembler in the output coding apparatus of FIG. The block diagram which shows the structure of the moving image decoding apparatus which concerns on the 1st and 2nd embodiment of this invention. The block diagram which shows the structure of the input decoding apparatus in the moving image decoding apparatus of FIG. The block diagram which shows the structure of the code sequence decomposer in the input decoding apparatus of FIG. The figure which shows the example of the code sequence obtained with the conventional error correction / detection code switching encoding apparatus The figure which shows the example of the synchronous code which the error produced by the bit addition / erasure of the transmission line for demonstrating the 2nd Embodiment of this invention The figure for demonstrating operation | movement of the bit insertion device in FIG. 3 in 2nd Embodiment. The figure for demonstrating operation | movement of the synchronous detector in FIG. 9, and an insertion bit remover in 2nd Embodiment. The figure which shows the example of the code sequence which performed synchronization protection using frame length information in 1st and 2nd embodiment The figure which shows the other example of the code sequence which performed synchronization protection using frame length information in 1st and 2nd embodiment The figure which shows another example of the code string which performed synchronization protection using frame length information in 1st and 2nd embodiment The block diagram which shows the structure of the moving image encoder which concerns on the 3rd and 4th embodiment of this invention. The block diagram which shows the structure of the output encoding apparatus of the moving image encoder which concerns on the 3rd Embodiment of this invention. The block diagram which shows the example of the output code sequence from the moving image encoder which concerns on the 3rd Embodiment of this invention. The block diagram which shows the structure of the moving image decoding apparatus which concerns on the 3rd and 4th embodiment of this invention. The block diagram which shows the structure of the input decoding apparatus of the moving image decoding apparatus which concerns on the 3rd Embodiment of this invention. The block diagram which shows the structure of the output coding apparatus of the moving image encoder which concerns on the 4th Embodiment of this invention. The block diagram which shows the structure of the input decoding apparatus of the moving image decoding apparatus which concerns on the 4th Embodiment of this invention. The block diagram which shows the example of the output code sequence from the moving image encoder which concerns on the 4th Embodiment of this invention. The figure which shows the rule of the multiplexing in the multiplexer in a moving image encoder The block diagram which shows the example of the output code sequence from the moving image encoder which concerns on the 5th Embodiment of this invention. The figure which shows the other example of the multiplexing by the multiplexer in a moving image encoder. The figure which shows the output code sequence which processed with respect to each synchronous code at the time of performing the multiplexing shown by FIG. The figure which shows the code | symbol table for demonstrating the example of the stuffing bit used by this invention The figure for demonstrating the process of the decoding apparatus at the time of using the stuffing bit of FIG. The figure for demonstrating the characteristic of the stuffing bit of FIG. The figure which shows the example of an output code sequence at the time of making a synchronous code insertion space shorter than a synchronous code The figure which shows the example which uses the synchronous code of different length The figure which shows the output code sequence from the moving image encoder which concerns on the 6th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Motion compensation adaptive predictor 102 ... Frame memory 104 ... Discrete cosine transformer 105 ... Quantizer 107 ... Inverse quantizer 108 ... Inverse discrete cosine transformer 111 ... Multiplexer 131 ... Input video signal 200 ... Output code 201 ... multiplexed code sequence 205 ... output code sequence 301 ... synchronous code 302 ... picture header 303 ... prediction mode information 304 ... motion vector information 305 ... DCT coefficient of prediction residual signal 402 ... synchronous code insertion position 212 ... bit insertion 211: Code sequence assembler 603 ... Latch circuit 604 ... Error correction / detection encoder 701 ... Counter 702 ... Buffer 705 ... Insertion bit generator 801 ... Motion compensated adaptive predictor 820 ... Frame memory 807 ... Inverse quantizer 808 ... Inverse discrete cosine transformer 811 ... Demultiplexer 800 ... Input decoding Device 850: Reproduced image signal 901, 1901: Synchronous code detector 902, 1902 ... Counter 903 ... Code sequence decomposer 904 ... Error correction / detection code decoder 905, 1905 ... Insertion bit remover 1005 ... Counter 1006 ... Comparator 1015: Insertion bit generator 1101-1104: Header information 1211: Bit inserter

Claims (9)

  Stuffing including a multiplexed code sequence obtained by multiplexing a plurality of types of variable-length codes generated by compressing and encoding an image signal, and having a length equal to or shorter than a period of a plurality of synchronization code insertion positions determined in advance periodically A synchronization code is detected at the synchronization code insertion position in the input code string in which the bit is inserted, and the position of the synchronization code detected by the synchronization code detection means with respect to the multiplexed code string in the input code string is used as a reference A decoding method comprising: generating a variable-length code by performing demultiplexing, decoding the generated variable-length code, and outputting a reproduced image signal. Stuffing including a multiplexed code sequence obtained by multiplexing a plurality of types of variable-length codes generated by compressing and encoding an image signal, and having a length equal to or shorter than a period of a plurality of synchronization code insertion positions determined in advance periodically Synchronization code detection means for detecting a synchronization code at the synchronization code insertion position in the input code string into which the bit is inserted;
Demultiplexing means for demultiplexing the multiplexed code string in the input code string with reference to the position of the synchronization code detected by the synchronization code detection means to generate a variable length code;
And a decoding unit that decodes the generated variable length code and outputs a reproduced image signal. In the multiplexed code string, the variable length code is multiplexed in frame units of the image signal,
The decoding apparatus according to claim 2, wherein the demultiplexing means demultiplexes the multiplexed code string in units of frames. In the multiplexed code string, the variable length code is multiplexed in units of partial areas of the frame of the image signal,
The decoding apparatus according to claim 2, wherein the demultiplexing means demultiplexes the multiplexed code string in units of the partial areas. In the multiplexed code string, the variable length code is multiplexed in frame units of the image signal,
The synchronization code detection means detects the synchronization code at a synchronization code insertion position positioned immediately before or immediately after the end portion of each multiplexing unit multiplexed in the frame unit of the multiplexed code string,
The decoding apparatus according to claim 2, wherein the demultiplexing means demultiplexes the multiplexed code string in units of frames. In the multiplexed code string, the variable length code is multiplexed in units of partial areas of the frame of the image signal,
The synchronization code detecting means detects the synchronization code at a synchronization code insertion position located immediately before or immediately after the end portion of each multiplexing unit multiplexed in the partial region unit of the multiplexed code string;
The decoding apparatus according to claim 2, wherein the demultiplexing means demultiplexes the multiplexed code string in units of the partial areas.   Code string conversion for converting a code string other than the synchronization code converted so that a hamming distance to the synchronization code is not less than a predetermined value at the synchronization code insertion position of the input code string to the original code string The decoding device according to claim 2, further comprising: means.   In the input code string, stuffing bits that are uniquely decodable from the reverse direction of the input code string and that have a hamming distance between the synchronization code and a part thereof are greater than or equal to a predetermined value are inserted. The decoding device according to claim 2, wherein:   The decoding apparatus according to claim 8, wherein the stuffing bit is arranged immediately before the synchronization code in the input code string.

Images