JP3597844B2 - Encoding method and apparatus - Google Patents

Description

  The present invention relates to a system for transmitting / accumulating information via a medium having a high error rate such as a wireless transmission path, and performing error correction / detection encoding on a transmission / decoding code stream obtained by high-efficiency compression encoding. The present invention relates to an encoding method and apparatus suitable for storing.

  For example, in a system such as a wireless TV phone, a portable information terminal, and a digital TV broadcast system, which efficiently compresses and encodes image and audio information so that the amount of information is as small as possible and transmits the information through a wireless transmission path or the like. However, since the error rate of the transmission path is high, how to transmit the obtained code string with high quality becomes an important issue.

  When transmitting / accumulating a code string via a medium having a high error rate, error correction codes such as a BCH code, an RS code, and convolution are often used as means for reducing the error rate. As means for enabling error detection on the receiving side, an error detection code such as a checksum or CRC is used. In these error correction / error detection, extra bits (redundancy) are added to information to be transmitted / stored according to a certain rule, and at the time of decoding, it is checked whether a transmitted / stored code string complies with this rule. Error correction and detection are performed based on the result.

  However, the method of encoding and transmitting / accumulating a code string obtained by the high-efficiency compression encoding into an error correction / detection code as described above is a method of recovering out-of-synchronization caused by a codeword error in a transmission line / medium. The disadvantage is that it is difficult to combine with a recovery technique. As a synchronization recovery method, a method is often used in which a code called a uniquely decodable synchronization code is inserted, and when synchronization is lost, decoding is restarted from the time when the synchronization code is detected.

  In order to make the synchronization code a code word that can be uniquely decoded, it is necessary to configure the code word so that the same bit pattern as the synchronization code does not occur in a combination of other code words. However, in error correction / detection coding, it is generally difficult to configure a code word so as to avoid the appearance of a specific bit pattern. The detection will cause pseudo-synchronization.

  To avoid this problem, after performing error correction / detection coding, it is determined whether or not the same bit pattern as the synchronization code exists in the code sequence. A method is used in which dummy bits are inserted according to a certain rule therein, and dummy bits are deleted according to the same rule in a decoding device, thereby preventing pseudo synchronization. However, when a code string is transmitted / stored through a medium in which an error is likely to occur, an error may also occur in the inserted bit, and there is a problem that a new loss of synchronization or a pseudo synchronization is caused.

  In addition, when a code string is subjected to error correction / detection coding and a synchronization code is inserted, conventionally, the remainder of information bits to be error-corrected / detection-coded at the last portion of a synchronization section sandwiched between the synchronization codes. Since a large number of insertion bits need to be added to the code string to compensate, there is also a problem that the coding efficiency is reduced.

  On the other hand, in order to enhance the error correction / detection ability, the redundancy of the information to be transmitted / stored may be increased, but in this case, the number of bits required to transmit the same information increases. For this reason, if the error correction / detection capability is enhanced, a transmission line with a higher transmission rate is required, and the number of bits of information that must be stored increases. Also, if the transmission rate and the storage capacity are the same, the higher the redundancy, the less information can be transmitted / stored. When transmitting / accumulating video and audio data with high efficiency in compression / encoding, adding redundancy to improve error resilience means compressing / encoding to a smaller amount of information if the transmission / accumulation rate is the same. And the quality of the image and the sound quality deteriorate.

  Therefore, as a method of providing high error tolerance with less redundancy, there is a method called hierarchical coding. This classifies highly efficient compression-encoded information according to the magnitude of the error that affects the image quality and sound quality. The same error correction / detection code is used as a whole by using an error correction / detection code that does not have a very high error correction / detection capability but has a small degree of redundancy for information that is not so greatly affected by errors by using a detection code. This is a method in which error resilience is further improved with the same average redundancy than in the case.

  For example, a coding method that combines motion compensation prediction and orthogonal transformation, which are often used for high-efficiency compression coding of moving images, that is, performs motion compensation prediction on an input moving image signal, and calculates the prediction residual In the method of performing orthogonal transform by DCT (Discrete Cosine Transform) or the like, error correction / correction is applied to motion vector information that causes a large deterioration in image quality when an error occurs, and low-order coefficients among orthogonal transform coefficients of a prediction residual signal. An error correction / detection code having a strong detection capability is used, and an error correction / detection code having a low error correction / detection capability is used as a higher-order coefficient among orthogonal transform coefficients of a prediction residual signal having a small effect of errors.

  In order to realize such hierarchical coding, it is necessary to switch error correction / detection codes having different error correction / detection capabilities in the middle of the output code string. As a method of switching between error correction / detection codes having different error correction / detection capabilities, there is a method of adding header information indicating the type of error correction / detection code to a code string. FIG. 11 shows an example of a code string in which error correction / detection codes are switched by adding header information. In this example, two types of error correction / detection codes FEC1 and FEC2 are switched. Headers 1101 to 1104 contain header information indicating the type of error correction / detection code and the number of codewords. The encoding device arranges the code words subjected to the error correction / detection encoding following the header information, and the decoding device decodes the header information, and decodes the error correction / detection code according to the header information.

  However, the method of switching the error correction / detection code by adding such header information has a problem that the number of bits of a code string that must be transmitted / stored by the addition of header information increases. When transmitting / accumulating an image or audio with high-efficiency compression encoding, dividing the number of bits in the header information reduces the number of bits used for high-efficiency compression encoding of the image or audio. In addition, image quality and sound quality are deteriorated.

  As described above, when error correction / detection coding is performed on a code sequence obtained by performing high-efficiency compression coding of a moving image signal or the like, an arbitrary bit pattern is generated. When combined with a synchronization recovery method using a decodable synchronization code, there is a problem of pseudo-synchronization due to erroneous detection of a synchronization code. However, there is a problem that a new out-of-synchronization or a pseudo-synchronization is caused by the error of.

  Further, when a code string is subjected to error correction / detection encoding and a synchronization code is inserted, conventionally, it is necessary to use a large number of insertion bits in the last part of a synchronization section in order to compensate for the remainder of information bits to be error correction / detection encoded. Therefore, there is a problem that the coding efficiency is reduced.

  Furthermore, in an encoding / decoding device that switches between error correction / detection codes having different error correction / detection capabilities by adding header information, the number of bits that must be transmitted / stored by adding header information increases. In the case of transmitting / accumulating an image or a sound with high-efficiency compression encoding, there is a problem that the amount of information allocated to the information of the image or the sound is reduced, and the image quality and the sound quality are reduced.

  A main object of the present invention is to provide an encoding method and apparatus capable of solving the problem of pseudo-synchronization and loss of synchronization due to erroneous detection of a synchronization code.

  In order to solve the above-mentioned problem, the encoding method according to the present invention inserts a synchronization code into any one of a plurality of synchronization code insertion positions that are predetermined periodically in an output code string including a variable length code. And inserting a stuffing bit immediately before any of the plurality of synchronization code insertion positions in the output code string.

  The encoding apparatus according to the present invention inserts a synchronization code into any one of a plurality of synchronization code insertion positions predetermined in a periodic manner in an output code string including a variable-length code, and includes the synchronization code in the output code string. A code string assembling means for inserting stuffing bits immediately before any of the plurality of synchronization code insertion positions is provided.

  Note that, in the present invention, a synchronization code is a code that can be uniquely decoded and inserted into a code sequence for synchronization recovery. For example, a code sequence for inserting a synchronization code compresses an image signal input in frame units. In the case of a multiplexed code string in which a plurality of types of encoded variable length codes are multiplexed, it is a code indicating a break of an encoded frame, a break of a plurality of types of variable length codes, and other breaks.

  According to the present invention, in order to insert a synchronization code only at a predetermined synchronization code insertion position in a multiplexed code string obtained by multiplexing a plurality of types of variable length codes in the encoding device, the decoding device Need only perform synchronization detection at this synchronization code insertion position, and the number of times of synchronization code detection is reduced as compared with the conventional method in which a synchronization code is inserted at an arbitrary position in a code string.

  In addition, the probability of occurrence of pseudo-synchronization due to the fact that the bit string input to the decoding device changes to the same bit pattern as the synchronization code due to a bit error decreases with the reduction in the number of synchronization code detections. According to the present invention, the occurrence of pseudo-synchronization can be reduced, and the amount of arithmetic processing involved in detecting a synchronization code is also reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(1st Embodiment)
FIG. 1 shows a combination of a high-efficiency compression coding device using discrete cosine transform coding, which is a type of motion compensation adaptive prediction and orthogonal transform coding, with a coding device having an error correction / detection code switching function according to the present invention. 1 is a block diagram illustrating an embodiment of a moving picture encoding device. The encoding method combining motion-compensated adaptive prediction and discrete cosine transform encoding is described in, for example, Reference 1: edited by Hiroshi Yasuda, “International Standards for Multimedia Encoding”, Maruzen, (June 1991). Only the outline of the operation will be described. The error correction / detection code used in the present embodiment is assumed to have information bits and check bits separated like a BCH code.

  In FIG. 1, an input moving image signal 131 to be encoded which is input in units of frames is subjected to motion compensation adaptive prediction in units of small regions such as macroblocks. That is, the motion-compensated adaptive predictor 101 detects a motion vector between the input video signal 131 and the already encoded / locally decoded video signal stored in the frame memory 102, and this motion vector is detected. A prediction signal 132 is created by motion compensation prediction based on the vector. In the motion compensation predictor 101, of the motion compensation prediction coding and the intra-frame coding (prediction signal = 0) for directly coding the input video signal 131, the prediction mode which is more suitable for coding is used. Is selected, and the corresponding prediction signal 132 is output.

  The prediction signal 132 is input to the subtractor 103, and the prediction signal 132 is subtracted from the input moving image signal 131 to output a prediction residual signal 133. The prediction residual signal 133 is subjected to discrete cosine transform (DCT) by the discrete cosine transformer 104 in units of blocks of a fixed size, and DCT coefficients are generated. This DCT coefficient is quantized by the quantizer 105. The quantized DCT coefficient data from the quantizer 105 is split into two, one of which is variable-length coded by a first variable-length encoder 106 and the other is dequantized by an inverse quantizer 107. , And an inverse discrete cosine transform (inverse DCT). The output from the inverse discrete cosine transformer 108 is added to the prediction signal 132 in an adder 109 to generate a local decoded signal. This locally decoded signal is stored in the frame memory 102.

  On the other hand, the information on the prediction mode and the motion vector determined by the motion compensation adaptive predictor 101 is subjected to variable-length encoding by the second variable-length encoder 110. The variable-length codes (compression codes) output from the first and second variable-length encoders 106 and 110 are multiplexed by the multiplexer 111 to become a multiplexed code sequence 201.

  Multiplexer 111 outputs multiplexed code string 201, FEC type identification signal 202 indicating the type of error correction / detection code corresponding thereto, and synchronization code insertion request signal 203 requesting insertion of a synchronization code. .

  An output coding apparatus 200 that switches the code string 202 to a plurality of types of error correction / detection codes having different error correction / detection capacities and codes the code string 202, the FEC type identification signal 202, and the synchronization code insertion request signal 203. And a final output code string 205 is generated. In the present embodiment, the output encoding device 200 corresponds to the encoding device according to the present invention.

  FIG. 2 is a diagram showing a flow of multiplexing in the multiplexer 111. Multiplexing is performed in units of encoded frames. First, the synchronization code 301 is multiplexed. When the synchronization code 301 is multiplexed, a synchronization code insertion request signal 203 is output from the multiplexer 111 to notify the encoding device 200 that the multiplexed codeword is a synchronization code. Next, a picture header 302 indicating various encoding modes of the encoded frame is multiplexed on the multiplexed code string 201. Next, the prediction mode information 303 indicating the prediction mode in the motion compensation adaptive predictor MC in each region is multiplexed, and further, the motion vector information 304 and the DCT coefficient of the prediction residual signal (hereinafter, referred to as a residual DCT coefficient). 305 are multiplexed. When multiplexing the picture header 302, the prediction mode information 303, the motion vector information 304, and the residual DCT coefficient 305, an FEC type identification signal 202 indicating the type of the corresponding error correction / detection code is output.

  An error correction / detection code having high correction / detection capability is used for the picture header 302, the prediction mode information 303, and the motion vector information 304, which greatly degrade image quality when errors are mixed. On the other hand, the residual DCT coefficient 305 can prevent large image quality degradation by detecting an error even if it is mixed and setting the residual to 0, so that the error correction capability does not need to be so high. It may only be possible to perform error detection.

  FIG. 3 is a block diagram showing a configuration of the output encoding device 200 in FIG. The output encoding device 200 includes a bit inserter 211, an error correction / detection switching encoder 212, and a code string assembler 213. FIG. 4 is a diagram illustrating an example of an output code string 205 generated by the output encoding device 200. In FIG. 4, PSC is a synchronization code, PH is a picture header, MODE is prediction mode information, MV is motion vector information, CHK is a check bit of an error correction / detection code, COEF is a residual DCT coefficient, and STUFF is a stuffing bit (insertion). Bit). This output code string 205 has the following features.

  (1) The synchronization code PSC is inserted only at any of the synchronization code insertion positions indicated by arrows arranged at regular intervals (every sync_period bits). The length of sync_period is larger than the length of the synchronization code PSC and the maximum length of the check bit CHK. The position of the check bit CHK is shifted so as to be immediately before the position where the synchronization code is inserted.

  (2) The error correction / detection code of one frame, that is, the last part of one synchronization period sandwiched between the synchronization code PSC and the next PSC is a degenerate code for encoding only the last remaining information bits, and The bit insertion of the stuffing bit STUFF is performed by the number of bits necessary for shifting the position of the bit CHK (CHK6 in the example of FIG. 4).

  (3) The FEC type identification signal indicating the type and number of error correction / detection codes does not exist in the output code string 205 of FIG.

  In this output code string 205, since the position of the check bit CHK is shifted as in (1) above, the check bit CHK does not enter the synchronization code insertion position indicated by the arrow. There is no possibility that pseudo-synchronization will occur. In addition, when performing error correction / detection coding at the end of a frame as in the above (2), it is necessary to insert a large number of insertion bits (dummy bits) in the related art, but in the present embodiment, Since the end of the frame is a degenerate code, the number of inserted bits is small. Further, since the header information indicating the type and number of the error correction / detection codes is not included in the output code string 205 as in the above (3), the code amount does not increase due to this.

  Hereinafter, regarding the configuration and operation of the output encoding apparatus 200 of FIG. 3 that generates such an output code string 205, the multiplexed code string 201 of FIG. 2 output from the multiplexer 111 and the output code string 205 of FIG. This will be described in detail with reference to FIG.

  When the synchronization code 301 is multiplexed by the multiplexer 111, the synchronization code insertion request signal 203 is output as described above. The synchronization code 301 includes, for example, “0” of sync_0_len bits, “1” of 1 bit, and “xxxxxx” of sync_nb_len bits indicating the type of the synchronization code 301 as shown in FIG. Upon receiving the synchronization code 301 and the synchronization code insertion request signal 203 from the multiplexer 111, the output encoding device 200 outputs a synchronization code (PSC) as an output code sequence 205 from the code sequence assembler 213.

  Here, as shown in FIG. 4, the synchronization code 301 can be inserted only into the synchronization code insertion position arranged at every sync_period bit in the output code string 205, so that the synchronization code 301 has not been generated until then. If the end of the output code string 205 is not at the synchronization code insertion position, a stuffing bit STUFF is inserted as described later so that the synchronization code 301 comes to the synchronization code insertion position.

  When the synchronization code 301 is output to the output code string 205, the picture header 302, the prediction mode information 303, the motion vector information 304, and the residual DCT coefficient 305 are encoded as follows. First, in the multiplexed code string 201 output from the multiplexer 111, bit insertion is performed in the bit inserter 211 to prevent occurrence of pseudo synchronization. That is, if the same bit pattern as the code word of the synchronization code 301 is present in the output code string 205, bit insertion is performed as necessary to prevent the synchronization code 301 from being uniquely decoded. For example, if the synchronization code 301 is a code word in which “0” s of sync_0_len bits are continuous as shown in FIG. 5, “1” is inserted into a code string other than the synchronization code 301 so that “0” does not continue more than sync_0_len bits. This can prevent the occurrence of pseudo synchronization.

As described above, since the synchronization code 301 is inserted only at the synchronization code insertion position, the bit insertion operation for preventing the occurrence of the pseudo synchronization need only be performed at the synchronization code insertion position. Therefore, a count value 221 indicating the total number of bits of the output code string 205 generated so far is output from the code string assembler 213, and whether or not bit insertion is necessary based on the count value 221 in the bit inserter 211 is determined. Is determined. Assuming that the count value 221, that is, the total number of bits of the already generated output code string 205 is total_len,
0 <total_len mod sync_period ≦ sync_0_len
The number of “1” s in the multiplexed code string 201 is counted in the section where .times., And if there is no “1” in this section, 1 bit “1” is inserted. Here, Amod B represents the remainder when A is divided by B.

  Further, in order to reduce the probability of erroneous detection of the synchronization code 301 due to an error, bits may be inserted as follows.

  Even when an n-bit error is mixed in the synchronization code 301, in order to detect the synchronization code 301, a code word whose Hamming distance is n or less in the input decoding device of the video decoding device described below is used. Must be determined as a synchronization code. However, if such a determination is made while leaving the code sequence other than the synchronization code 301 as it is, there may be a bit pattern whose Hamming distance from the synchronization code is n or less even in the code sequence other than the synchronization code 301. If it is at the position where the synchronization code is inserted, the synchronization code 301 is erroneously determined.

Therefore, by inserting bits into the multiplexed code sequence 201 by the bit inserter 211 as follows, a code sequence other than the synchronization code at the synchronization code insertion position in the multiplexed code sequence 201 is hammed with the synchronization code 301. Conversion is performed so that the distance becomes a value separated by 2 * n + 1 or more. In particular,
0 <total_len mod sync_period ≦ sync_0_len− (2 * N + 1)
Then, the number of “1” (= n0) is counted in the section where .times..times..times..times..times..times..times..times..times..times..tim- es..times..times..times.

  The coded sequence 222 after bit insertion by the bit inserter 211 is input to the error correction / detection code switching coding unit 212 together with the FEC type identification signal 202 indicating the type of the error correction / detection code. .

  FIG. 6 is a block diagram showing a configuration of the error correction / detection code switching encoding unit 212 in FIG. The latch circuit 603 is a circuit that latches the FEC type identification signal 202. When the output of the synchronization code from the multiplexer 111 to the multiplexed code string 201 ends and the synchronization code insertion request signal 203 stops, the FEC type identification signal 202 is latched. The signal 202 is latched, and the latched signal 623 is supplied to the error correction / detection encoder 604.

  The error correction / detection encoder 604 performs error correction / detection encoding on the code sequence 222 from the bit inserter 211 according to the latched signal 623, and generates and outputs information bits 631 and check bits 632. When the error correction / detection encoding of one block is completed, the error correction / detection encoder 604 outputs a latch instruction signal 625 instructing the latch circuit 603 to latch the next FEC type identification signal 202. The latch circuit 603 performs latching according to the latch instruction signal 625, and supplies the latched signal 623 to the error correction / detection encoder 604.

  The above operation is repeated in the output encoding device 200, and the code sequence 222 after the bit insertion from the bit inserter 211 is converted by the error correction / detection switching encoder 212 into the FEC type identification signal indicated by the multiplexer 111. The error correction / detection coding is performed while the error correction / detection code is switched according to 202. Since the FEC type identification signal 202 is latched by the latch circuit 603 only at the end of the encoding of the error correction / detection code of one block, the same error correction / detection code is applied up to this switching point. For example, when an error correction / detection code called FEC1 is used for the picture header 302 and FEC2 is used for the prediction mode information 303, when the number of bits of the picture header 302 is shorter than the number of information bits of one block of the FEC1, the following prediction mode information 303 is used. FEC1 is used until the number of information bits of FEC1 is reached.

  FIG. 7 is a block diagram showing a configuration of the code sequence assembler 213 in FIG. The code string assembler 213 includes a counter 701 for counting the number of bits of the output code string 205, a buffer 702 for temporarily storing the check bits 632 and the number of bits, a switch 703 for switching the output code string 205, and a switch 703 is configured by a switching controller 704 for controlling 703.

  When the synchronization code insertion request signal 203 is input, the counter 701 is reset to the value of the synchronization code length sync_len, and counts up from the next bit of the synchronization code until the next synchronization code is input. After the input of the synchronization code, the switch 703 operates so that the information bit 631 is output until the first check bit 632 is input. When the check bit 632 is input, it is stored in the buffer 702 and the number of bits (the number of check bits) 711 is output from the buffer 702 to the switching controller 704.

The switching controller 704 performs the switching of the check bit based on the check bit number 711 and the count value 221 of the counter 701 so as to prevent the check bit 632 from being output to the synchronization code insertion position as described above. 703 is controlled. For example, if the count value 221 is bit_count and the check bit number 711 is check_len,
bit_count mod sync_period <sync_period- check_len
In the case of, information bit 631 is output,
sync_period- check_len ≤ total_bits mod sync_period <sync_period
At the time of, the check bit 713 stored in the buffer 702 is output. Thereafter, the above process is repeated while inputting the information bit 631 and the check bit 632.

  As described above, the output encoding apparatus 200 uses the degenerate code as the error correction / detection code in the last part of one frame, and performs bit insertion to shift the position of the check bit. Behaves differently than usual. That is, when the output of the multiplexed code string 201 of one frame is completed, the multiplexer 111 outputs the synchronization code insertion request signal 203 of the next frame. Correspondingly, the error correction / detection encoder 604 in the error correction / detection switching encoder 212 in FIG. 6 outputs the shortage of the information bits 631 of the error correction / detection code from the insertion bit generator 705. Assuming that the bit pattern is a predetermined bit pattern, error correction / detection coding using a degenerate code is performed. In this bit pattern, all bits may be set to “1”, “0”, or a repetition of a specific pattern such as “0101...”. This supplemented insertion bit is not output as the information bit 631.

In the code sequence assembler 213 of FIG. 7, after outputting the information bits 631 to the end, the switch 703 is switched from the bit generator 705 to the input, and the check bits 713 stored in the buffer 702 are set immediately before the next synchronization code. Insert the insertion bit so that The number stuffing_len of the inserted bits is as follows: the count value 221 of the counter 701 when the last information bit 631 of one frame is output is defined as total_len, and the number of check bits 632 output last is defined as last_check_len.
stuffing_len = sync_period-last_check_len-(total_len mod sync_period)
It becomes. When the degenerate code is not used, a bit is inserted by a bit (into_len−last_into_len) which is a shortage of the last information bit last_into_len from the normal information bit into_len, and a bit is inserted to shift the position of the check bit. There is a need to do. For this reason, compared with the case where the degenerate code is used, more insertion bits are required for into_len−last_into_len + (into_len−last_into_len) mod sync_period bits.

  The code string assembler 213 outputs the information bits 631 and the insertion bits to the output code string 205 via the switch 703 in this way, and finally switches to the check bits 713 to output to the output code string 205.

Next, the video decoding device according to the present embodiment will be described.
FIG. 8 is a block diagram showing a configuration of a video decoding device corresponding to the video encoding device of FIG. The output code string 205 output from the video coding apparatus of FIG. 1 is input to the input decoding apparatus 800 as an input code string 205 'after passing through a transmission / storage system. In the present embodiment, the input decoding device 800 corresponds to the decoding device according to the present invention.

  The input decoding apparatus 800 performs error correction / detection decoding while switching the error correction / detection code based on the FEC type identification signal 802 indicating the type of the error correction / detection code from the subsequent demultiplexer 811. A code sequence 801, a synchronization code detection signal 803, and an error detection signal 804 are output. The demultiplexer 811 receives the code sequence 801, the synchronization code detection signal 803, and the error detection signal 804, and separates and outputs a prediction residual code 841 and a motion compensation adaptive prediction information code 842.

  The prediction residual code 841 and the motion compensation adaptive prediction information code 842 are input to first and second variable length decoders 806 and 810, respectively. The residual DCT coefficient 831 decoded by the first variable length decoder 806 is subjected to a series of processes such as inverse quantization by an inverse quantizer 807 and inverse discrete cosine transform by an inverse DCT unit 808, and then an adder At 809, the output is added to the motion-compensated adaptive prediction signal 832 output from the motion-compensated adaptive predictor 801 to become a reproduced image signal 850. The reproduced image signal 850 is output outside the apparatus and is recorded in the frame memory 820. The motion-compensated adaptive prediction information decoded by the second variable-length decoder 810 is input to the motion-compensated adaptive predictor 801 to generate a motion-compensated predicted signal 832.

  The above process is a process of reproducing a moving image corresponding to the moving image encoding device of FIG. 1. The processes performed by the inverse quantizer 807, the inverse DCT unit 808, the adder 809, and the frame memory 820 are respectively Although the realizing means may be different from those of the inverse quantizer 107, the inverse DCT unit 108, the adder 109 and the frame memory 102 in FIG. 1, they are basically the same. The processing of the first and second variable length decoders 806 and 810, the demultiplexer 811 and the input decoding device 800 is performed in the variable length code shown in FIG. The processing is the reverse of that of the encoders 106 and 110, the multiplexer 111, and the output encoder 200.

  FIG. 9 is a block diagram showing a configuration of the input decoding device 800. The input decoding apparatus 800 includes a synchronization detector 901 for detecting a synchronization code in the input code string 205 ′, a counter 902 for counting the number of bits of the input code string 205 ′, and checking the input code string 205 ′ with information bits 912. It comprises a code string decomposer 903 for decomposing and outputting bits 913, an error correction / detection decoder 904, and an insertion bit remover 905.

The synchronization detector 901 detects the synchronization code only at the synchronization code insertion position based on the count value 911 of the counter 902. For example, if the interval of the synchronization code insertion position is sync_period, the count value 911 is bit_count, and the length of the synchronization code is sync_len,
0 <bit_count% sync_period ≤ sync_len
Synchronization detection is performed only when.
Here, the synchronization code may be detected in consideration of the synchronization code error.

  If the bit inserter 211 in the output encoding device 200 in FIG. 3 performs code string conversion by bit insertion so that the Hamming distance from the synchronization code is 2 * n + 1 in consideration of an error of n bits or less. Even if a code having a Hamming distance from a true synchronization code of n or less is determined to be a synchronization code, erroneous synchronization detection does not occur if an error of n bits or less is mixed.

  FIG. 10 is a block diagram illustrating a configuration of the code sequence decomposer 903. The input code string 205 'is switched between an information bit 1021 and a check bit 913 by a first switch 1002 controlled by a controller 1001 described below. When the information bit 1021 is output from the first switch 1002, the information bit 1021 is stored in the buffer 1004 via the second switch 1003 by the information bit length. The counter 1005 counts the number of output bits from the second switch 1003. The count value 1023 of the counter 1005 is compared with the information bit length 1024 output from the error correction / detection code information output unit 1007 by the comparator 1006, and when both match, the counter 1005 is reset and the error correction is performed. The FEC type identification signal 802 indicating the type of the / detection code is latched by the latch circuit 1008, and the information bit 912 is output from the buffer 1004. The output 914 of the latch circuit 1008 is input to the error correction / detection code information output circuit 1007 and is also output to the error correction / detection decoder 904 shown in FIG.

As described above, the check bits of the error correction / detection code are shifted in position, and are included in the code string 205 between the information bits of the error correction / detection code at the rear. The controller 1001 performs control so that the inspection bits and the information bits subjected to the position shift are separated. When the input of the information bits of the error correction / detection code of one block is completed, the count value 1023 and the information bit length 1024 in the comparator 1006 match. The controller 1001 receives the coincidence signal, takes in the check bit length 1025 from the error correction / detection information output unit 1007, and calculates the position of the check bit included between the next information bits. Assuming that the count value 911 of the number of input bits of the code string 205 'when the comparator 1006 determines that they match is bit_count and the check bit length is check_len, the check bit start position check_start is
check_start = (bit_count / sync_period + 1) * sync_period-check_len
And the check bit end position check_end is
check_end = (bit_count / sync_period + 1) * sync_period
It becomes. The controller 1001 controls the switch 1002 so that the check bit 913 is output while the count value 911 is from check_start to check_end.

Since error correction / detection coding is performed at the end of one frame using degenerate codes, special processing is performed. When the end of one frame is reached, the synchronization detector 901 outputs a signal 803 indicating that the synchronization code of the next frame has been detected. Controller 1001 receives signal 803 and calculates the position of the check bit of the last error correction / detection code of the frame and the number of missing bits of the information bit. Pre_last_count is the count value of the number of bits of the input code string 205 'when inputting the last error correction / detection code of one frame is pre_last_count, and the count value at the end of input of the code string 205' of one frame. 911 is total_count, the count value 911 at the time of processing is bit_count, the check bit length of the error correction / detection code at the end of one frame is last_check_len, and the check bit length of the error correction / detection code immediately before that is pre_last_check_len. And First, the excess or deficiency of information bits due to the fact that the error correction code is a degenerate code and that bit insertion has been performed is calculated. Among the information bits of the error correction / detection code at the end of one frame, the number of bits last_info_len included in the output code string 205 is:
last_inf0_len = total_count -last_check_len -pre _last_count -pre _last_check _len
It is. When the last_info_len is shorter than the information length of the error correction code, info_len, it is determined that the code is a degenerate code. Make up for the lack of information bits. The output bit pattern from the insertion bit generator 1015 generates the same bit pattern as that of the insertion bit generator 705 in FIG. 7 of the encoder.

On the other hand, when the last_info_len is longer than the info_len, it is determined that the bit is inserted, and the information bit 912 is not output for a portion where the count value 1023 is equal to or more than the info_len. For check bits,
total _count −check _len <bit _count ≦ total _count
The switch 1002 is controlled so as to output the output code string 205 at the time of (1) as a check bit.

  The error correction / detection decoder 904 receives the information bits 912 and the check bits 913 output from the code string decomposer 903 and receives the FEC indicating the type of the error correction / detection code latched by the latch circuit 1008 in FIG. An error correction / detection code is decoded based on the type identification signal 914, and an error corrected code string 915 and an error detection signal 804 are output.

  The error-corrected code string 915 is input to the insertion bit remover 905. The insertion bit remover 905 performs a process of removing an insertion bit for preventing a pseudo synchronization signal inserted by the bit insertion unit 211 of the output encoding device 200. As described above, since the bit insertion is performed only at the synchronous insertion position, the synchronous insertion position is determined based on the count value 911 of the counter 902.

  For example, it is assumed that the synchronization code word is as shown in FIG. 5, and the bit insertion unit 211 inserts a bit into the first sync_len bit “0000... If so, the number of sync_0_len- (2 * n + 1) bits of "1" (= n0) is counted from the synchronization code insertion position, and if n0 is 2 * n + 1 or less, 2 * n + 1- Delete n0 bits. However, since the insertion bit is determined to be “1”, if the bit determined to be an insertion bit by the insertion bit remover 905 is “0”, an error is mixed in the synchronization code insertion section. In this case, an error detection signal 804 is output.

  The code sequence 801 decoded by the input decoding device 800 as described above is demultiplexed by the demultiplexer 811. This is an operation of separating and outputting a multiplexed codeword as shown in FIG. This demultiplexer 811 operates in conjunction with the first and second variable length decoders 806 and 810.

  First, when the synchronization code detection signal 803 is input from the output decoding device 800, the demultiplexer 811 shifts to an initial state of frame processing. Next, the type of the error correction / detection code for the picture header is output as the FEC type identification signal 802 indicating the type of the error correction / detection code, the code sequence 801 is input, and the picture header 302 is decoded. Determine if there is. If there is no error, the type of the error correction / detection code for the prediction mode information 303 is output as the FEC type identification signal 802, the code string 801 is input to demultiplex the prediction mode information, and the second variable length Output to the decoder 810.

  When decoding all prediction mode information, the second variable length decoder 810 outputs a signal indicating this to the demultiplexer 811. In response, the demultiplexer 811 outputs an FEC type identification signal indicating the type of the error correction / detection code for the motion vector information 304, and starts demultiplexing the motion vector information 304. The demultiplexed motion vector information is output to the second variable length decoder 810 and decoded. When decoding of all the motion vector information is completed, a signal indicating that fact is output from the second variable length decoder 810 to the demultiplexer 811, and the demultiplexer 811 receives the signal, and the residual DCT coefficient 305 is received. And outputs a FEC type identification signal indicating the type of the error correction / detection code for, and demultiplexes the residual DCT coefficient 305 to the first variable length decoder 806. The residual DCT coefficient 305 is decoded by the first variable length decoder 806.

  As described above, the type of the error correction / detection code is determined in the demultiplexer 811 based on the multiplexing rule determined in the same manner as in the output encoding device 200. Therefore, it is not necessary to include header information indicating the type of error correction / detection code in the output code string 205.

  The error correction / detection decoder 904 may detect that an error is mixed in the input code string 205 'by the error detection code. Further, as described above, the inserted bit remover 905 may detect an error in the inserted bit. In these cases, the error detection code 804 is output from the input decoding device 800. Furthermore, when a codeword that is not in the variable-length codeword table is detected in the variable-length decoding process, it is determined that an error has been mixed. Also, when it is determined in the demultiplexing process in the demultiplexer 811 that there is a part that violates the multiplexing rule, it is also determined that an error has been mixed. In these cases, the input decoding device 800 and the demultiplexer 811 perform the following processing so that the reproduced image does not significantly deteriorate.

  (1) If an error is detected in the residual DCT coefficient, the residual of the relevant part is set to 0. When the intra-encoding mode is selected as the prediction mode, a reproduced image signal of the area may be predicted from a reproduced frame or a reproduced image signal of a surrounding area.

  (2) When an error is detected in the prediction mode information or the motion vector, when the prediction mode information or the motion vector information of the surrounding area can be estimated from the prediction mode information or the motion vector information of the surrounding area, it is used. If it is impossible, the reproduced image signal of the area is predicted from the reproduced frame and the reproduced image signal of the surrounding area.

  (3) If an error is detected in the picture header, decoding it as it is may cause a very large deterioration in image quality. Therefore, the reproduced image of the previous frame is used as it is as the reproduced image of the current frame.

  In the above processes (1), (2), and (3), if the error has spread to the subsequent code up to the next synchronization code due to the use of variable-length coding, the same applies to that part. Is performed.

  In the above description, an example in which the synchronization code detector 901 detects the synchronization code only at the synchronization code insertion position (every sync_period bits) has been described. However, depending on the transmission / storage medium, loss of bits or insertion of erroneous bits may occur. In some cases. In such a case, the synchronization code may be detected at a position other than the synchronization code insertion position, and the position where the synchronization code is detected may be determined as the synchronization code insertion position.

(Second embodiment)
Next, a second embodiment according to the present invention will be described with reference to FIGS. The moving picture encoding apparatus and the moving picture decoding apparatus according to the present embodiment provide a transmission line / storage in which a part of a bit string is lost and the number of bits is reduced, or an extra bit is added to increase the number of bits. Even when a code string is transmitted / stored in a medium, synchronization detection can be reliably performed.

  FIG. 12 is a block diagram showing the principle of the process of synchronization detection when such bit addition / loss occurs. Here, it is assumed that the correct synchronization code is composed of “0” of sync_0_len bits and “1” of 1 bit as shown in FIG. Note that “x” in FIG. 12 is a bit other than the synchronization code.

  FIGS. 12B to 12E show how the synchronization code changes due to bit addition / erasure. Here, the number of bits (Nid) to be added / erased is 1 bit at maximum. (B) shows a case where one bit is deleted in a bit string before the synchronization code, and the entire synchronization code is shifted one bit before. (C) is a case where one bit is added in the bit sequence before the synchronization code, and the entire synchronization code is shifted one bit later. (D) shows a case where a bit is deleted in the synchronous code, and the bit is shifted forward by one bit from the bit missing position indicated by the arrow in the figure. Further, (e) is a case where one bit is added in the synchronization code, and one bit is added at the bit addition position indicated by the arrow in the figure, and the bit after that is shifted by one bit.

In order to correctly detect synchronization even if bit addition / erasure occurs, the bit strings shown in FIGS. 12B to 12D also need to be determined as a synchronization code. As can be seen from FIG. 12, the number of “1” included in the range of ± Nid bits at the correct synchronization code insertion position is the maximum.
sync_0_len -3 * Nid
Is a bit. Therefore, on the decoding side, synchronization detection is performed within the range of ± Nid bits of the synchronization code insertion position, and if the number of “1” s included in this section is equal to or less than the above value, it may be determined that the synchronization code is used. Further, the encoding apparatus converts the code string so that the bit patterns of FIGS. 12B to 12D do not occur.

  Hereinafter, such an encoding device / decoding device will be described focusing on differences from the first embodiment.

  The moving picture coding apparatus according to the second embodiment has the same overall configuration as the moving picture coding apparatus according to the first embodiment, but differs in the operation of the bit inserter 211 in FIG. FIG. 13 shows the operation of the bit inserter 211. That is, in the bit inserter 211 of the first embodiment, the bit insertion operation is performed only in the synchronization code insertion section. However, in the bit inserter 211 of the second embodiment, bit addition / erasure of the maximum Nid bit is not performed. In order to prevent the occurrence of the same bit pattern as the synchronization code even if it occurs, the bit insertion is performed in the synchronization code insertion section ± Nid bit section.

Assuming that the count value 221 in FIG. 3 is total_len and the interval between the synchronization code insertion positions is sync_preriod, the bit inserter 211
total _len mod sync_period = sync_period-Nid
(Mod: remainder operation)
From
total_len mod sync_period = sync_0_len -1-3 * Nid
, The number of “1” (= n0) in the section is counted, and if n0 is less than 3 * Nid + 1, 3 * Nid + 1−n0 bit “1” is inserted.

  FIG. 13 shows an operation example of the bit inserter 211 when sync_period = 12, sync_0_len = 9, and Nid = 1. Since n0 = 2 in this example, 3 * Nid + 1−n0 = 2 bits “1” is inserted.

  By performing the bit insertion in this way, it is guaranteed that the number of “0” in the synchronization code insertion section ± Nid bit is 3 * Nid bits or more, and it is possible to uniquely identify the synchronization code.

  On the other hand, the moving picture decoding apparatus according to the second embodiment has the same overall configuration as that of the first embodiment, but differs in the operation of the synchronization detector 901 and the inserted bit remover 905 in FIG. . FIG. 14 shows the operation of the insertion bit remover 905.

  That is, the synchronization detector 901 detects the synchronization code within a range of ± Nid bits before and after the synchronization code insertion position in order to detect the synchronization even if the maximum Nid bit addition / erasure occurs.

First, it is determined whether or not a synchronization code exists for each synchronization code insertion position. That is, when the count value 911 of the counter 902 is set to bit_count,
bit_count mod sync_period = sync_period-Nid
From
bit_count mod sync_period = sync_0_len -1 + Nid
Is counted (= ns0), and if n0 is not more than 3 * Nid, it is determined that a synchronization code exists in this section.

  The operation example of FIG. 14 shows an example in which sync_period = 12, sync_0_len = 9, and Nid = 1. In this example, (bit_count mod sync_period) counts the number of “0” between “11” and “8”. In the example of FIG. 14, since ns0 = 2, it is determined to be a synchronization code.

Next, it is determined how many bits of the code string are shifted due to bit addition / erasure in the synchronization code insertion section where it is determined that there is a synchronization code. In the case of sync_0_len bits as shown in FIG. 14, the shift amount is determined from the last “1” position. More specifically, the first “1” is searched from the sync_0_len + 1 bit from the beginning of the synchronization code determination section, and the bit number from the beginning of this synchronization code determination section (= first_1_pos bits) Based on
Number of shift bits = first_1_pos-(sync_0_len +1 + Nid)
(Shift forward if negative, shift backward if positive)
Asking. In the example of FIG. 14, since first_1_pos = 10,
Number of shift bits = 10− (9 + 1 + 1) = − 1
It can be seen that the data is shifted forward by one bit.

Unlike the first embodiment, the insertion bit removal unit 905 performs insertion bit removal processing in the section of the synchronization code insertion position ± Nid bits. That is,
bit_count mod sync_period = sync_period-Nid
From
bit_count mod sync_period = sync_0_len -1-3 * Nid
, The number of “1” (= n0) is counted, and if n0 is 3 * Nid + 1 or less, “1” of 3 * Nid + 1−n0 bits is removed.

  In the second embodiment, when it is possible to determine in some form a section where bit addition / loss has occurred in a transmission path or a storage medium, a synchronization detection process, a bit insertion process, and a bit removal process in consideration of the bit addition / loss are: It may be performed only in that section.

  In the moving picture decoding apparatus according to the first embodiment, the synchronization detector 901 uses the second embodiment in order to perform synchronization detection corresponding to bit addition / loss in a transmission path or a storage medium. Similarly to the above, the synchronization detection may be performed in a synchronization code insertion section ± Nid bit section. In this case, there is a possibility that pseudo-synchronization in which a portion other than the synchronization code is erroneously determined as the synchronization code may occur. However, in a transmission line / storage medium in which bit addition / erasure is likely to occur, deterioration of the quality of a decoded image due to synchronization detection error is suppressed. Image quality can be improved.

  If it is possible to determine in some form the section where bit addition / loss has occurred in the transmission path or storage medium, this processing is performed only in that section, and normal synchronization detection is performed in other sections. Good.

  Further, in the above-described first and second embodiments, synchronization may be further protected by using information indicating a frame length (hereinafter, referred to as frame length information). FIGS. 15, 16 and 17 show examples of code strings when the frame length information POINTER is used.

  In the example of FIG. 15, immediately after the synchronization code PSC, frame length information POINTER and a check bit CHKP of an error correction / detection code for protecting the frame length information POINTER follow. In the frame length information POINTER, information indicating the number of bits of the previous frame, that is, information indicating the number of bits from the synchronization code of the previous frame to the synchronization code of the current frame is recorded.

  The encoding device counts the number of code string bits in one frame, converts this into frame length information POINTER, and performs error correction / detection encoding to generate check bits CHKP. Then, as shown in FIG. 15, a code string is generated immediately after the synchronization code of the next frame.

  On the other hand, in the decoding device, after detecting the synchronization code in the same manner as described in the first and second embodiments, the subsequent frame length information POINTER and check bit CHKP are extracted from the code string, and The frame length information POINTER is decoded by performing correction / detection decoding. Then, the decoded frame length information POINTER is compared with a value (frame length count value) obtained by counting the number of bits from the synchronization code detected immediately before to the position of the current synchronization code (frame length count value). Check for false detection of.

  If the frame length count value is different from the code length of the previous frame indicated in the frame length information POINTER, there is a possibility that an erroneous detection of the synchronization code has occurred. The synchronization code is re-detected. That is, it is assumed that there is a synchronization code that could not be detected ahead of the current synchronization code by the number of bits indicated by the frame length information POINTER. In this case, the section from the previously detected synchronization code to the current synchronization code includes a section from the previous synchronization code to the position indicated by the frame length information POINTER, and a section from the preceding synchronization code to the current synchronization code. The decoding process is performed by dividing the frame into two frames.

  However, if the number of bits indicated by the frame length information POINTER is larger than the number of bits from the previously detected synchronization code to the position of the current synchronization code, it is determined that the frame length information POINTER is incorrect. Regarding this, the above-mentioned re-detection processing is not performed.

  When the number of bits of the frame length information POINTER and the check bit CHKP is large, the synchronization code PSC, the frame length information POINTER, and the check bit CHKP may extend over a plurality of synchronization sections as shown in FIG. In this case, the bit insertion process in the encoding device and the bit deletion process in the decoding device for maintaining the code string other than the synchronization code at a constant Hamming distance from the synchronization code include frame length information POINTER and check bit. It may not be performed in a section where CHKP exists.

  In the examples of FIGS. 15 and 16, when information indicating the type of the synchronization code (such as the distinction between the frame synchronization code and the GOB synchronization code) is included in the latter half of the synchronization code PSC, not only the frame length information POINTER but also The latter bit of the synchronization code PSC may be protected by an error correction code. As a result, not only the position of the synchronization code but also its type can be accurately detected, so that the resistance to errors is further improved.

  In the example of FIG. 17, the frame length information POINTER and the check bit CHKP are placed at the end of the frame (immediately before the synchronization code of the next frame). In this case, after detecting the synchronization code of the next frame, the decoding apparatus extracts the immediately preceding frame length information POINTER and check bit CHKP to perform error correction / detection decoding, and performs the same processing as in FIGS. The synchronization code is detected again.

  In the example of FIG. 15, since the synchronization code exists only at the synchronization code insertion position, the frame length information POINTER may record a value obtained by dividing the number of bits of the frame by the synchronization code insertion interval (= sync_period bits). . Thereby, the frame length can be represented by a small number of bits.

  In the first and second embodiments, an example has been described in which hierarchical coding is performed in which an error correction / detection code is changed in accordance with the importance of information to be encoded. However, the same error correction / detection is performed within a frame. A code may be used, or an error correction / detection code may not be used. Even in such a case, bit insertion processing for maintaining a hamming distance of a code string other than the synchronization code as described in the present embodiment with the synchronization code and a predetermined value or more, and synchronization code detection processing corresponding thereto Accordingly, the ability to detect synchronization is improved over the conventional method.

  In the description of each of the above embodiments, an example has been described in which a moving image signal is transmitted / stored with high-efficiency compression coding, but the present invention can also be applied to transmission / storage of still images, audio, data, and the like. It is possible. For example, when a still image signal is subjected to high-efficiency compression encoding using orthogonal transform, the error correction / detection code may be switched and used so as to more strongly protect the low-frequency component of the transform coefficient from error protection. In a method of coding a speech by modeling it into a driving source and a vocal tract filter, the error correction / detection code may be switched so as to strongly protect a pitch period, a vocal tract parameter, and the like.

(Third embodiment)
Next, a third embodiment according to the present invention will be described. This embodiment is different from the first and second embodiments in that no error correction / detection code is used.

  FIG. 18 is a block diagram of the video encoding device according to the present embodiment. The same reference numerals are given to portions corresponding to those in FIG. 1 to explain mainly the differences from the first embodiment. In this embodiment, the configuration and operation of the output encoding device 200 are different. Also, the multiplexer 111 has the same basic operation as the multiplexer 111 of FIG. 1, but with no error correction / detection code, only the multiplexed code sequence 201 and the synchronization code insertion request signal 203 are provided. Is output.

  FIG. 19 is a block diagram showing a configuration of the output encoding device 200 in FIG. The output encoding apparatus 200 includes a counter 1701 for counting the number of bits of the output code string 205, a switch 1703 for switching the output code string 205, a switch controller 1704 for controlling the switch 1703, and a stuffing bit for generating a stuffing bit. It comprises a generator 1705.

  FIG. 20 is a diagram illustrating an example of the output code string 205 generated by the output encoding device 200 in FIG. The code words corresponding to the output code string in FIG. 4 are denoted by the same symbols. Similar to FIG. 4, the synchronization code PSC is inserted periodically, that is, only at one of the synchronization code insertion positions indicated by arrows arranged at regular intervals (sync_period bits). FIG. 20 differs from FIG. 4 in that the check bit CHK of the error correction / detection code is not included. A stuffing bit STUFF is inserted into the last part of one frame of the output code string 205 so that the synchronization code PSC is inserted at the synchronization code insertion position. The number of bits of the stuffing bit STUFF is equal to or less than sync_period bits.

  Hereinafter, the configuration and operation of the output encoding device 200 of FIG. 19 that generates such an output code string 205 will be described in detail.

  The counter 1701 is set to “1” when the synchronization code insertion request signal 203 is input from the multiplexer 111 and the first bit of the synchronization code 301 is input as the multiplexed code string 201, and all bits of the synchronization code 301 are set. Is set to the sync code length sync_len. Thereafter, the counter 1701 counts up from the next bit of the synchronization code 301 until the bit immediately before the next synchronization code is output.

  The switching controller 1704 switches the switch 1703 to the side of the multiplexed code string 201 when the bits from the first bit of the synchronization code to the bit before the next synchronization code are input as the multiplexed code string 201, Control is performed so that the multiplexed code string 201 is output as the output code string 205.

  Then, in the last part of one frame, bit insertion (bit stuffing) is performed so that the next synchronization code is inserted at the synchronization code insertion position. When the output of the multiplexed code string 201 for one frame is completed, the multiplexer 111 outputs a synchronization code insertion request signal 203 for the next frame. In response to this, the switching controller 1704 switches the switch 1703 to the stuffing bit generator 1705 and outputs the stuffing bit 1223 as the output code string 205. All of the stuffing bits 1223 may be “1”, “0”, or a specific pattern such as “0101...”.

Next, the video decoding device according to the present embodiment will be described.
FIG. 21 is a block diagram showing a configuration of a video decoding device corresponding to the video encoding device of FIG. The parts corresponding to those in FIG. 8 are denoted by the same reference numerals, and a description will be given focusing on differences from the first embodiment. In this embodiment, the configuration and operation of the input encoding device 800 are different. The signals input from the input decoding device 800 to the demultiplexer 811 are only the code string 801 and the synchronization code detection signal 803, and there are no signals input from the demultiplexer 811 to the input decoding device 800.

  FIG. 22 is a block diagram showing a configuration of the input decoding device 800. The input decoding device 800 includes a synchronization detector 1901 for detecting a synchronization code in the input code string 205 ', and a counter 1902 for counting the number of bits of the input code string 205'.

  The counter 1902 is reset to "0" at the initial stage of decoding, and counts up the count value 1911 by "1" every time one bit of the input code string 205 'is input.

The synchronization detector 1901 detects the synchronization code only at the synchronization code insertion position based on the count value 1911 of the counter 1902. For example, if the synchronization code insertion interval is sync_period, the count value 1911 is bit_count, and the length of the synchronization code is sync_len,
0 <bit_count mod sync_period ≦ sync_len
Synchronization detection is performed only when. Here, A mod B represents a remainder when A is divided by B. When detecting the synchronization code, the synchronization detector 1901 outputs a synchronization code detection signal 803.

  As the code sequence 801 from the input decoding device, the input code sequence 205 ′ is output as it is and input to the demultiplexer 811. Thereafter, demultiplexing and decoding are performed in the same manner as in the moving picture decoding apparatus of FIG.

  When the last stuffing bit STUFF of the frame is a predetermined bit pattern, the demultiplexer 811 determines whether the stuffing bit STUFF matches the predetermined pattern. It may be determined that there is an error in the column 205 ', and a process for preventing the image quality degradation from increasing as described in the moving picture coding apparatus shown in the first embodiment may be performed.

(Fourth embodiment)
Next, a fourth embodiment according to the present invention will be described.
The overall configuration of the video encoding device according to the present embodiment is the same as that of the video encoding device in FIG. 18, and the operation of the output encoding device differs from that of the third embodiment.

  FIG. 23 is a block diagram showing a configuration of the output encoding device 200 in FIG. The parts corresponding to those of the output encoding apparatus of FIG. 19 are given the same reference numerals and the differences will be mainly described. A bit inserter 1211 for performing a bit stuffing process for preventing a pseudo-synchronous code is added. .

  In the bit inserter 1211, bit insertion is performed on the multiplexed code string 201 to prevent occurrence of pseudo synchronization. This is a process for preventing the synchronization code from being uniquely decoded if the same bit pattern as the synchronization code exists in the output code string 205. For example, when the synchronization code is composed of “0” of sync_0_len bits, “1” of 1 bit, and “xxxxxx” of sync_nb_len bits indicating the type of synchronization code as shown in FIG. If "1" is inserted in the column so that "0" does not continue for more than sync_0_len bits, occurrence of pseudo synchronization can be prevented.

The synchronization code is inserted only into the synchronization code insertion device. Therefore, the bit insertion operation for preventing the occurrence of the pseudo-synchronization may be performed only at the synchronization code insertion position. Therefore, it is determined whether bit insertion is necessary based on the count value 1221 indicating the total number of bits of the output code string 205. Assuming that the count value 1221 is total_len,
0 <total_len_mod_sync_period ≦ sync_0_len
Then, the number of “1” in the multiplexed code string 201 is counted in the section where .times., And if there is no “1” in this section, 1 bit “1” is inserted. Here, A mod B represents a remainder when A is divided by B.

  Further, in order to reduce the probability of erroneous detection of the synchronization code due to an error, bit insertion may be performed as follows.

  In order to detect a synchronization code even when an n-bit error is mixed in the synchronization code, a code word whose Hamming distance is n or less than a true synchronization code in an input coding device of a moving image coding device described later is a synchronization code. It is necessary to judge. However, if such a determination is made while leaving the code sequence other than the synchronization code as it is, a bit pattern whose Hamming distance from the synchronization code is n or less may exist in the code sequence other than the synchronization code. If it is at the insertion position, it is erroneously determined to be a synchronization code.

Therefore, by inserting bits into the multiplexed code sequence 201 by the bit inserter 211 as described below, a code sequence other than the synchronization code at the synchronization code insertion position in the multiplexed code sequence 201 is inserted into the hamming distance with the synchronization code. Are converted so as to be separated by 2 × n + 1 or more. In particular,
0 <total_len_mod_sync_period ≦ sync_0_len− (2 × n + 1)
Then, the number of “1” (= n0) in the section where is calculated is counted. If n0 is less than 2 × n + 1, “1” of 2 × n + 1−n0 bits is inserted into the multiplexed code sequence 201.

  The code sequence 1222 after the bit insertion has been performed is subjected to bit insertion (STUFF in FIG. 20) in the last section of the frame, as in the output encoding device of FIG. 19, and is output as an output code sequence 205. .

  Next, the video decoding device according to the present embodiment will be described. The overall configuration of the video decoding device is the same as that of the video decoding device of FIG. 21, and the operation of the input encoding device 800 is different from that of the third embodiment.

  FIG. 24 is a block diagram showing the configuration of the input decoding device 800. A part corresponding to that of the input decoding device of FIG. 22 is denoted by the same reference numeral, and a bit remover 1905 is added to mainly describe differences from the third embodiment.

  The input code string 205 'is input to an insertion bit remover 1905, and performs a process of removing an insertion bit for preventing a pseudo-synchronous code inserted by a bit insertion unit 1211 of the output encoding apparatus of FIG. As described above, since the bit insertion is performed only at the synchronization code insertion position, the synchronization code insertion position is determined based on the count value 1911 of the counter 1902.

  For example, it is assumed that the synchronization code is the code word shown in FIG. 5, and bit insertion is performed in the first “0000...” Portion of the synchronization code in the bit inserter 1211 so that the Hamming distance from the synchronization code is at least 2 × n + 1. If so, the number of sync_0_len− (2 × n + 1) bits “1” is counted from the synchronization code insertion position, and if n0 is less than 2 × n + 1, 2 × n + 1−n0 bits are deleted.

  Here, since the insertion bit is defined as “1”, if the bit determined to be an insertion bit is “0”, it is considered that an error has been mixed in the synchronization code insertion section. In this case, an error detection signal (not shown) may be output to the demultiplexer 811 and processing similar to that described in the first embodiment may be performed so that the reproduced image does not significantly deteriorate.

  In the bit insertion process in the bit inserter 1211 in FIG. 23, a predetermined number of bits may be inserted into all synchronization code insertion sections other than the synchronization code. 25 shows an example of the output code string 205 when such a bit insertion process is performed. In the figure, SB indicates the inserted bit.

  For example, when the synchronization code is composed of “0” of sync_0_len bits, “1” of 1 bit, and “xxxxxx” of sync_nb_len bits indicating the type of synchronization code as shown in FIG. Is inserted at a predetermined position in the section of the section (1).

  The insertion bit SB may always be “1”. Further, according to the bit pattern of the section of sync_0_len bits from the beginning of the synchronization code insertion section, the insertion bit SB may be adaptively determined so that the number of “1” in the section becomes one or more.

  Further, by setting the insertion bit SB as an odd parity in a section of sync_0_len bits from the beginning of the synchronization code insertion section, the appearance of the same bit pattern as the synchronization code is avoided, and an error mixed in this bit pattern is also detected. It is possible.

  FIG. 25B shows an output code string that has been subjected to such bit insertion processing. In this example, a one-bit insertion bit SB is inserted into the first part from the synchronization code insertion position. The insertion bit SB is determined so that the number of “1” in a section obtained by adding “sync_0_len−1” bits from this and the next bit is always an odd number. For example, in the example on the left side of FIG. 25B, the insertion bit SB is “1”. Further, in the example on the right side of FIG. 25B, even if the section from the bit following the insertion bit SB to sync_0_len -1 bit is all “0”, the insertion bit SB becomes “1”. One or more bits of "1" always enter the section, and the same bit pattern as the synchronization code does not occur. Also, since the insertion bit SB also functions as a parity check bit, it is possible to detect a bit error mixed in this section.

  Further, the insertion bit SB may be an odd parity check bit of all bits up to the next synchronization code insertion position. However, the insertion bit SB is always set to “1” in order to avoid the appearance of the same bit pattern as the synchronization code only when all of the sync_0_len−1 bits from the bit next to the insertion bit SB are “0”. Thereby, it is possible to perform error detection by parity check of all bits.

  In order to lower the probability of erroneous detection of a synchronization code due to an error, it is desirable to insert a larger number of bits. For example, in order to correctly detect synchronization even if an n-bit error occurs, 2 × n + 1-bit “1” is inserted at a predetermined position in this section.

  In the present embodiment, the operation of the bit remover 1905 in FIG. 24 is different from the operation of the bit inserter 1211 described above. That is, the bit remover 1905 performs a process of deleting the insertion bit SB at a predetermined position where the bit insertion has been performed by the bit inserter 1211.

  Here, if the insertion bit SB is always “1”, if the bit at the bit insertion position in the input code string 205 ′ is “0”, it is determined that a bit error has occurred and an error detection signal (shown in FIG. No) may be output to the demultiplexer 811 to perform processing for preventing the decoded image from being significantly degraded.

  In the first to fourth embodiments, the multiplexing in the multiplexer 111 is performed by combining the prediction mode information 303, the motion vector information 304, and the residual DCT count 305 in units of encoded frames as shown in FIG. Although an example of multiplexing has been described, as shown in FIG. 26, even if multiplexing is performed such that the prediction mode information 303, the motion vector information 304, and the residual DCT count 305 are grouped in units of coding regions (for example, macroblocks, GOBs, etc.). Good. In this case, different error correction / detection codes may be used for the picture header 302 and other information, or the same error correction / detection code may be used. Alternatively, an error correction / detection code may be used only for a picture header, an error correction / detection code may be used for a part of a predetermined number of bits in each frame, or an error correction / detection code may be used. The sign need not be used at all.

  Also, multiplexing is performed not only on a frame (picture) basis but also on a partial area in a frame or on a layer basis in which a plurality of frames are put together, and a synchronization code is inserted for each of these multiplexing units (layer units). Good.

  FIG. 28 shows an example of such multiplexing. In the example of FIG. 28, multiplexing is performed for each of four layers: a macroblock in which a plurality of encoded blocks are combined, a GOB in which a plurality of macroblocks are combined, a picture (frame), and a session in which a plurality of pictures are combined. Of these, each layer of session, picture, and GOB uses respective synchronization codes (SSC, SEC, PSC, GSC in the figure). Different codes are used for SSC, SEC, PSC, and GSC, respectively, so that it is possible to distinguish which layer's synchronization code has been detected. In the case of using the synchronization codes as shown in FIG. 5, the synchronization codes may be distinguished from each other by the sync_nb_len bits indicating the types of the synchronization codes.

  Even when such multiplexing is performed, the same processing as the frame synchronization code in the above-described embodiment may be performed on some or all of the synchronization codes of the session, picture, and GOB. FIG. 29 shows an example of an output code string that has undergone such processing. As shown in the figure, a stuffing bit STUFF is inserted before PSC and GSC, and SSC, PSC and GSC are inserted at the synchronization code insertion positions indicated by arrows in the figure. For this reason, the detection accuracy of each synchronization code is improved as in the case of the frame synchronization code PSC described in the above embodiment.

  It is also possible to add the same length information as the frame length information POINTER in FIGS. 15, 16 and 17 to each synchronization code of session, picture and GOB. As shown in FIGS. 15 and 16, when the frame length information POINTER is protected by the error correction / detection code, not only the frame length information POINTER but also the sync_nb_len bit portion indicating the type of the synchronization code is used. In addition, by using the error correction / detection code, the probability that not only the position of the synchronization code but also its type can be correctly detected is improved. Further, a part or all of the header information (SH, PH, GF in the figure) of the session, the picture, and the GOB may be protected by using an error correction / detection code. Also improve.

  When stuffing processing for preventing a pseudo-synchronous code is performed as in the present embodiment, the following processing may be performed to make the synchronous code insertion interval sync_period less than or equal to the length of the synchronous code.

First, the processing in the output coding amount of the moving picture coding apparatus will be described. Here, as shown in FIG. 5, the synchronization code is a code word composed of “0” of sync_0_len bits and “1” of 1 bit. In the output coding apparatus of FIG. 23, if the count value 1221 indicating the number of bits output from the bit inserter 1211 is defined as total_len, the remainder obtained by dividing total_len by the synchronization code insertion interval sync_period is the first “0” of the synchronization code. When the value obtained by subtracting 1 from the number of bits of sync_0_len of 1 matches the remainder obtained by dividing by sync_period, that is,
total_len mod sync_period
= (Sync_0_len -1) mod sync_period (1)
, The number of “1” s in the output bits from the current output bit to (sync_0_len−1) bits before (n1) is counted, and if there is no “1” at all (that is, n1 = If it is 0) 1-bit "1" is inserted.

  FIG. 33A shows an example of an output code string that has undergone such processing. In the figure, the downward arrow indicates the position where the synchronization code is inserted, and the synchronization code is composed of 23-bit “0” (that is, sync_0_len = 23) and 1-bit “1”. In the example of the figure, the synchronization code insertion interval sync_perod is 8, which is shorter than the length of the synchronization code (= 24 bits).

  In the figure, sections 1 to 4 indicate sections for counting the above-mentioned n1. The number n1 of "1" is sequentially counted in each section, and if n1 = 0, a stuffing bit is inserted into the next bit of the section. Since n1> 0 in section 1, there is no need for stuffing. Since n1 = 0 in section 2, one stuffing bit 3301 is inserted after this section. In section 3, since stuffing 3301 has been inserted, n1 = 1, so there is no need to insert a stuffing bit.

  By performing the bit stuffing process as described above, since the same bit pattern as the synchronization code in the portion other than the synchronization code in the output code string disappears, pseudo synchronization does not occur.

  On the other hand, in order to reduce the probability of erroneous detection of a synchronization code due to a transmission path error, bits may be inserted as follows.

  Even if an n-bit error is mixed in the synchronization code, in order to correctly detect the synchronization code, in the bit insertion 1211, the Hamming distance between the portion other than the synchronization code in the output code sequence and the synchronization code is 2 × n + 1 or more. The bit insertion processing may be performed so that

This is because the remainder obtained by dividing the count value 1221 total_len indicating the total number of bits of the output code string 205 in FIG. 23 by the synchronization code insertion interval sync_period subtracts 2 × n + 1 from the first synchronization bit number “0” of the synchronization code, sync_0_len. Value equal to the remainder obtained by dividing the value by sync_period, that is,
total_len mod sync_period
= (Sync_0_len- (2 × n + 1)) mod sync_period (2)
, The number of “1” s (referred to as n1) in the output bits up to (sync_0_len− (2 × n + 1)) bits before the output bit at that time is counted, and the number of “1” s becomes (2 × n + 1), that is,
n1 <2 × n + 1
Then, (2 × n + 1−n1) bits “1” are inserted.

  When a synchronization code starting from a plurality of bits “0” as shown in FIG. 5 is used, if the number of “1” s in the bit string immediately before the synchronization code is small, an erroneous synchronization detection may occur in this part. In order to prevent this, the bit insertion in the last section of the frame (FIG. 20) is performed so that the number of “1” bits in the section of the sync_period bit from the synchronization code to the immediately preceding synchronization code insertion position is 2 × n + 1 bits or more. (Medium, STUFF) may be output.

  For this, a STUFF that always includes “1” of 2 × n + 1 bits or more may be used, or the STUFF may be determined according to an output code string. That is, the STUFF may be determined such that the number of “1” bits of the sync_period bit immediately before the synchronization code in the output signal sequence including the STUFF is 2 × n + 1 bits or more.

  FIG. 33B shows an example of an output code string that has undergone such processing. In the figure, sections 1 to 4 indicate sections for counting the above-mentioned n1. In each section, the number of "1" s is counted as n1, and if n1 <2 × n + 1, a stuffing bit is inserted into the next bit in the section. Since n1 = 1 in section 2, a stuffing bit 3311 of (2 × n + 1) -1 = 2 bits is inserted after this section. In section 3, since stuffing 3311 has been inserted, n1 = 3, so there is no need to insert a stuffing bit.

  Further, in order to prevent the erroneous detection of the synchronization code in the portion immediately before the synchronization code, STUFF is determined as follows. The bit immediately before STUFF is set to 3312. Since there is only one bit of “1” between sync_period bits (section 5) from the synchronization code insertion position immediately before this bit 3312 to the synchronization code insertion position immediately after this bit 3312, a plurality of “0” as shown in FIG. When a continuous synchronization code is used, there is a possibility that a synchronization error is detected in this portion. Therefore, the position where the synchronization code is inserted is shifted to the next synchronization code insertion position, and STUFF 3313 including many “1” s is output. As a result, the sync_period bit section (section 6) immediately before the synchronization code includes “1” of 2 × n + 1 bits or more, so that erroneous detection of synchronization can be prevented.

  By performing the above-described bit stuffing processing, the hamming distance from the synchronization code in a portion other than the synchronization code in the output code string can be set to 2 × n + 1 or more, and the probability of false synchronization detection is reduced.

  Next, processing in the input decoding device of the video decoding device will be described. In the bit remover 1905 in FIG. 24, if the count value 1905 indicating the number of bits of the input code string is defined as total_len, when the total_len becomes a value satisfying the condition of 1, from the input bits at that time, (sync_0_len − 1) Count the number of "1" (n1) in the input bits up to the bit before, and if there is no "1", that is, if n1 = 0, delete one bit.

In order to detect a synchronization code even when an n-bit error is mixed in the synchronization code, the bit inserter 1211 controls the Hamming distance between the portion other than the synchronization code in the output code sequence and the synchronization code to be 2 × n + 1 or more. When the bit insertion processing is performed on the first bit, the following processing may be performed. When the total_len becomes a value satisfying the expression (2), the number of “1” s (referred to as n1) in the output bits from the input bit at that time to (sync_0_len− (2 × n + 1)) bits before is counted. And the number of “1” is less than (2 × n + 1), that is,
n1 <(2 × n + 1)
Then, (2 × n + 1−n1) bits are deleted.

  By performing the above processing in the output encoding device and the input decoding device, and by setting the synchronization code insertion interval sync_period to a short number of bits equal to or less than the length of the synchronization code, the number of bits of the stuffing bit STUFF is reduced, Encoding efficiency is improved. In particular, when the length of the synchronization code is long or when many synchronization codes are inserted, the degree of improvement in coding efficiency by reducing the number of stuffing bits STUFF is large. For example, in a system in which a screen is divided into one or a plurality of macroblocks or macroblock lines and a synchronization code is inserted for each unit, such as GOB / slice in video coding, many synchronization codes are inserted. Therefore, the degree of coding efficiency by reducing the number of bits of STUFF is further increased.

  When multiplexing a plurality of layer structures as shown in FIG. 28, synchronization codes having different lengths may be used depending on the layers.

  FIG. 34 (a) shows an example of such a synchronization code. Of the four types of synchronization codes, SSC, SEC, and PSC each consist of a total of 32 bits of 23 bits “0”, 1 bit “1”, and 8 bits indicating the type of synchronization code. On the other hand, the synchronization code GSC of the GOB layer is a 17-bit synchronization code composed of 16-bit "0" and 1-bit "1", and is a shorter codeword than other synchronization codes.

  The reason why only the GSC is a short codeword is that the GOB is a coding unit which is composed of one or a plurality of macroblocks (MB) and is divided into small areas in the screen. This is because the number is larger than other synchronization codes, and the code amount of the output code string can be reduced by shortening the synchronization code word length. Further, in this case, if the same code amount is used, more GSCs can be output, and it becomes possible to divide the screen into finer GOB areas and perform coding, so that a transmission path error occurs. The quality of the reproduced image at the time is improved.

  The processing for preventing the pseudo synchronization as described in the fourth embodiment, that is, the bit stuffing processing for preventing the same bit pattern as the synchronization code from being generated in a code string other than the synchronization code is performed. You may. Bit stuffing processing to reduce the probability of erroneous detection of a synchronization code due to a transmission line error, for example, the same bit pattern as a synchronization code having a long bit length (SSC, SEC, PSC in the example of FIG. 34A) occurs. Even for a bit string that is guaranteed only to be non-existent, if bit stuffing processing is performed so that the same pattern as the shortest synchronization code (GSC in the example of FIG. 34A) does not occur, all synchronization codes can be used. The same bit pattern can be prevented from occurring. This process may be performed on the code sequence of all layers, or may be performed on the code sequence of a layer lower than the layer using the shortest code (GOB layer, macro block layer in the example in the figure). However, the processing may be performed on a code string of a layer (a picture layer, a GOB layer, a macroblock layer) below the layer one layer above the layer. Further, this processing may be performed only on a code sequence of a predetermined layer.

  In order to make it easy to identify synchronous codes having different lengths even if a transmission line error occurs, the synchronous codeword and the processing before and after the synchronous codeword may be performed as follows.

  (i) When using a synchronization code consisting of a plurality of bits “0” followed by a “1”, the relative position of the long code word and the short code word as viewed from the synchronization code insertion position of the “1” is It may be different. In the example of FIG. 34B, the “1” 3411 of the PSC and the “1” 3412 of the GSC are at different positions, and the bits of the same amount (3413 for 3411 and 3414 for 3412) in another synchronization code are Both are "0". By doing so, the Hamming distance between the re-synchronization code and the partial sequence thereof increases, so that even when a transmission line error occurs, different synchronization codes can be easily distinguished from each other.

  (ii) A stuffing bit may be inserted before the short synchronization code. For example, by inserting a stuffing bit 3401 consisting of one or a plurality of "1s" before a GSC having a short length as shown in FIG. 3401, the hamming distance between the OSC and the sub-sequence of another synchronization code is increased. be able to.

  (iii) A stuffing bit may be inserted after the short-length synchronization code. For example, the bit insertion 3402 may be performed after the GSC so that the Hamming distance from the part for identifying the type of the synchronization code in the long synchronization code is increased.

(Fifth embodiment)
Next, a fifth embodiment according to the present invention will be described.
The overall configuration of the moving picture coding apparatus and the moving picture decoding apparatus according to the present embodiment is the same as that of the first embodiment, and the first and last of one synchronization section of the output coding apparatus 200 and the input decoding apparatus 800. The processing in the part is different from the previous embodiments.

  FIGS. 27A, 27B, and 27C are diagrams illustrating an example of an output code string 205 from the video encoding device according to the present embodiment. The output code string 205 includes a part 2701 of the code string of the previous frame (frame n-1) after the synchronization code PSC, and a boundary 2703 between the code string 2701 and the code string of the current frame (n frame). There is (start point of the code string of the current frame), in other words, pointer information 2702 (SA) indicating the boundary of the multiplexed code string, and accordingly, the last stuffing bit of one frame (STUFF in FIG. 4) is lost. This is different from the output code string of FIG.

  In the output encoding device 200 in the video encoding device, the number of bits resid_bit of the remaining code sequence of the frame is checked at each synchronization code insertion position. If the sum of the resid_bit, the synchronization code PSC, and the bit number of the pointer information SA is smaller than the synchronization code insertion interval sync_period bits, the synchronization code PSC is output before the remaining code sequence of the frame is output to the output code sequence 205. Is output. Next, pointer information SA (in this case, representing resid_bit) is output, and thereafter, the remaining code string 2701 is output. After that, the code sequence of the next frame is output.

  In the input encoding device 800 in the video decoding device, the synchronization code is detected at each synchronization code insertion position, and when the synchronization code is detected, the pointer information SA and the remaining information of the frame are placed behind the synchronization code. The processing is performed assuming that it is continued.

  Taking the boundary part between frame n-1 and frame n in FIG. 27 as an example, after the decoding processing up to 2704 immediately before the synchronization code PSC is completed, the synchronization code is detected in the synchronization code insertion section after that, If a code is detected, the pointer information 2702 is decoded next to determine how many more bits are left in the code string of frame n-1. Based on this, the number of bits indicated by the pointer information is extracted from the code sequence immediately after the pointer information (up to 2703 in FIG. 27), and the code sequence 801 is output assuming that this follows 2704. The subsequent code string (from 2703 in FIG. 27) is processed as the next frame, that is, frame n.

  In the present embodiment, as shown in FIG. 27A, error correction / detection coding may be performed on part or all of the output code string. In this case, the types of error correction / detection codes may be the same, or different types may be used.

  Also, as shown in FIG. 27B, error correction / detection coding may not be performed.

  Further, as shown in FIG. 27C, frame length information POINTER indicating the number of code string bits of one frame as shown in FIGS. 15 and 16 may be inserted. In this case, the frame length information POINTER may indicate the number of bits from the synchronization code PSC of the frame to the synchronization code PSC of the next frame.

  When error correction / detection coding is performed as shown in FIG. 27A, error correction / detection coding of a portion from the synchronization code PSC to the next check bit CHK is performed by the pointer information SA and the remaining of the frame n-1. The error correction / detection code is performed by combining the code strings 2701 and the code strings of frame n after 2703 as one information bit.

  The pointer information SA may be information obtained by performing error correction / detection coding. In this case, error correction / detection coding may be performed by combining the synchronization code PSC (or a part thereof), the frame length information POINTER, and the pointer information.

  Next, a specific example of the stuffing bit STUFF will be described.

  FIGS. 30A and 30B are diagrams showing an example of a stuffing bit STUFF code table as a specific example of the above-described stuffing bit STUFF. Each of FIGS. 30 (a) and 30 (b) is characterized in that it can be uniquely decoded from the reverse direction of the output code string, whereby the start position of the stuffing bit STUFF can be uniquely specified. Therefore, by comparing the decoding end position of the code string immediately before the stuffing bit STUFF with the start position of the stuffing bit STUFF, it is possible to detect an error mixed in the code string and to perform decoding in the reverse direction from the synchronization code. In this case, it is possible to specify the starting point of the backward decoding when used in the decoding scheme.

  Furthermore, the first bit of the stuffing bit STUFF shown in the code table of FIGS. 30A and 30B is always “0”, and error detection can be performed by simple decoding as described later.

  FIG. 31 shows an example of a decoding process of a code string including the stuffing bits STUFF shown in the code tables of FIGS. FIG. 31 shows an example of the stuffing bits immediately before the synchronization code insertion position. However, similar processing can be performed by inserting stuffing bit bits immediately before any other synchronization code insertion position. . In FIG. 31, arrows 3101 to 3103 are examples of the decoding end position of the code string (indicated by “xxx ...”) immediately before the stuffing bit STUFF when decoding is performed in the forward direction. Indicates the decoding end position. If no error is mixed in the code string and decoding is performed normally, the decoding end position of the code string immediately before the stuffing bit STUFF matches the start position of the stuffing bit STUFF as indicated by an arrow 3101. .

  On the other hand, when an error is mixed in the code string, the decoding end position of the code string immediately before the stuffing bit STUFF is shifted from the start position of the stuffing bit STUFF as shown by arrows 3102 and 3103. In such a case, it is determined that there is an error in the code string.

  When the decoding apparatus finishes decoding the code string immediately before the stuffing bit STUFF, the decoding apparatus reads the stuffing bit STUFF up to the next synchronization code insertion position, and reads the stuffing bit STUFF from the code table shown in FIGS. Determine if the code matches. If the stuffing bit STUFF does not match any of the codes in the code table, it is determined that an error has occurred.

  When judging a match between the stuffing bit STUFF and the code table, a small number of bit errors may be allowed. By doing so, it is possible to reduce erroneous detection of an error when an error enters the stuffing bit STUFF itself.

  The code table in FIG. 30A always starts with “0” and the subsequent bits are “1”. Therefore, error detection may be performed only by determining whether the bit next to the decoding end position of the code string immediately before the stuffing bit STUFF is “0”, or the first “0” and the subsequent Error detection may be performed from only some of the "1" s. By doing so, the amount of processing required for decoding is reduced, although the accuracy of error detection is slightly reduced. As described above, when all the stuffing bits STUFF use a code table starting from a specific bit or a specific bit pattern including a plurality of bits, the decoding process can be simplified.

  Further, the stuffing bits STUFF shown in the code tables of FIGS. 30 (a) and 30 (b) contain many bits of “1”, and as shown in FIG. Since the hamming distances are long, there is an advantage that the probability of occurrence of pseudo synchronization is low. Specifically, in the code table of FIG. 30A, only the first bit of the stuffing bit STUFF is all “0” and all other bits are “1”, so that the synchronization code of all “0” is used. And a hamming distance to a part thereof is (length of stuffing bit STUFF-1). Also, in the code table of FIG. 30B, only the first and last bits of the stuffing bit STUFF are “0”, and all other bits are “1”. Is (length of stuffing bit STUFF−2). As described above, by selecting the Hamming distance between the stuffing bit STUFF and the synchronization code and a part thereof to a predetermined value or more, for example, (length of the stuffing bit STUFF-2) or more, even if an error is mixed in the code string, the pseudo synchronization code Is less likely to occur.

  This effect will be described with reference to FIG. FIGS. 32 (a-0) and (b-0) respectively show a normal stuffing bit (all bits are "0") and a stuffing bit STUFF shown in the code table of FIG. 30 (a). (A-1) and (b-1) show examples in which one bit error is mixed in (a-0) and (b-0), respectively. As can be seen from FIG. 32 (a-1), in the normal stuffing bit in which all bits are "0", only one bit error is mixed, and as shown by the broken line in FIG. Since the same bit pattern is generated, pseudo synchronization occurs. On the other hand, the stuffing bit STUFF shown in the code table of FIG. 30A does not have the same pattern as the synchronization code even if an error is mixed as shown in FIG. do not do.

  As described above, the stuffing bit according to the present embodiment has an advantage that an error in a code string can be easily detected, a pseudo-synchronous code hardly occurs even if an error is mixed in the code string, and the stuffing bit has a strong error resistance.

  In addition, the stuffing bit according to the present embodiment can be uniquely decoded from the reverse direction, and its start position, that is, the end position of the code string immediately before the stuffing bit bit STUFF can be specified. In the case of a code word that can be decoded also from the direction, the code string immediately before STUFF can be decoded from the reverse direction as shown by an arrow 3104 in FIG.

  In the above embodiment, the stuffing bit STUFF may be determined as follows.

  (1) When the sync code includes “0” of the sync_0_len bits as shown in FIG. 5, all of the stuffing bits STUFF or at least all bits at the sync code insertion position are set to “1”, whereby the sync code The hamming distance between the “0” portion and the stuffing bit STUFF can be increased. Therefore, by doing so, it is possible to reduce the probability that pseudo-synchronization occurs due to an error mixed in the stuffing bit STUFF.

  (2) The stuffing bit STUFF may be a codeword indicating its length. The decoding apparatus determines the length of the STUFF from the point where decoding of the code string other than the stuffing bit STUFF is completed, and decodes the STUFF to decode the STUFF length information. In this case, if they do not match, it can be determined that an error has been mixed in the code string.

  Further, the code word of the stuffing bit STUFF may be a value in which the length is expressed in a binary number. For example, when the STUFF has 5 bits, “00101” may be represented by expressing “5” in a binary number. Alternatively, a value obtained by taking the complement of “1” or the complement of “2” in a binary number may be used as the code word of the stuffing bit STUFF, and the number of “0” bits in STUFF is reduced. As described in (1), the occurrence of pseudo synchronization can be suppressed.

  (3) When encoding is performed using a codeword that can be decoded not only in the forward direction but also in the backward direction, the stuffing bit STUFF is decoded in the decoding device in the backward direction from the end point of the frame, and the start point is decoded. (A boundary point between STUFF and another codeword). In such a case, for example, STUFF may be defined as a code word starting with one or a plurality of bits “0” such as “01111111” and remaining as “1”. As a result, if STUFF is decoded in the reverse direction and a position where “0” is located is searched for, that point can be uniquely determined as the start point of STUFF. In this example, bits other than the first part of the stuffing bit STUFF are "1", and the probability of occurrence of pseudo synchronization is reduced as described in (1).

  (4) The stuffing bit STUFF may be an error correction / detection code check bit for some or all bits of the output code string, a parity check bit, or the like. This makes it possible to correct / detect a bit error mixed in the output code string.

  By generating the stuffing bit STUFF according to a predetermined rule as in the above example, the decoding apparatus checks the stuffing error STUFF in the input code string against the generation rule, and if the generation rule is violated. When it is determined, it is possible to determine that an error has been mixed in the input code string. As a result, it is possible to improve the quality of the reproduced image when an error is mixed in the input code string by performing processing in the moving image decoding apparatus such that the reproduced image does not significantly deteriorate.

  Further, in the above embodiment, the synchronization code insertion interval sync_period may be determined as follows.

  (1) When an error correction / detection code is used, the synchronization code insertion interval sync_period is the minimum number of bits for performing synchronization detection in the decoding device, that is, the sum of the length of the synchronization code and the maximum value of check bits of the error correction / detection code. That is enough. Since the average value of the number of bits of the stuffing bit STUFF at the end of the frame is sync_period / 2, the number of stuffing bit STUFF bits is reduced by taking sync_period as the minimum bit that can be synchronously detected, thereby improving coding efficiency. I do.

  (2) When no error correction / detection code is used, it is sufficient that the synchronization code insertion interval sync_period is equal to or greater than the minimum number of bits for performing synchronization detection in the decoding device, that is, the length of the synchronization code. Since the average number of bits of the last stuffing bit STUFF of the frame is sync_period / 2, the number of stuffing bit STUFF bits is reduced by taking sync_period as the minimum bit that can be synchronously detected, thereby improving coding efficiency. .

  (3) As shown in FIGS. 15, 16, 17 and 27, when the frame length information POINTER is used, the synchronization code insertion interval sync_period may be shorter than the length of the synchronization code. As a result, the number of stuffing bits STUFF is reduced, and coding efficiency is improved.

  (4) When transmission / storage is performed by dividing into packets or cells at a predetermined interval in a transmission path or a storage medium, the synchronization code insertion interval sync_period is adjusted to the interval between packets or cells, or is set to a divisor of the interval. It may be. As a result, the beginning of the packet or cell is always at the position where the synchronization code is inserted. Therefore, even when a packet or cell occurs due to packet loss or cell loss, the synchronization code can be detected.

  (5) The sync code insertion interval sync_period is preferably shorter than the minimum required number of bits in one frame. As a result, the number of stuffing bits STUFF is reduced, and coding efficiency is improved.

(Sixth embodiment)
Next, a sixth embodiment according to the present invention will be described.
FIG. 35 is a diagram illustrating an example of an output code string of the video encoding device according to the present embodiment. In this output code string, the bit insertion processing as described in the above-described actual travel example is performed in order to reduce the probability of false detection of a synchronization code due to an error. Further, information such as header information is stored at a predetermined position or a predetermined position relative to the synchronization code.

  FIG. 35A shows a code string before the bit insertion processing is performed, and FIG. 35B shows an output code string after the bit insertion processing is performed. In the figure, hatched portions 3201, 3202, 3261, and 3262 are information to be put in a predetermined amount (a position relatively viewed from the synchronization code), and white arrows 3211 and 3212 indicate the information. It is the position to put. The code sequence information 3261 and 3262 in FIG. 35B correspond to the code sequence information 3201 and 3202 in FIG. 35A, respectively. In some cases, when converting the code sequence (a) into the code sequence (b), Conversion may be performed on these pieces of information (that is, conversion of information 3201 into information 3261 and conversion of information 3202 into information 3262).

  Reference numeral 3203 in FIG. 35B indicates bits inserted by the bit insertion processing. Due to this bit insertion process, the bit sequence following the insertion bit is shifted backward, so that the process of moving a part of the code sequence immediately before the information to the rear is performed so that the information to be inserted into the predetermined position is in the fixed position. Do. For example, assuming that the total number of insertion bits from the synchronization code 3205 immediately before the information 3201 is Ns1, the Ns1 bit indicated by the symbol 3221 in FIG. What is necessary is just to move to the part of the symbol 3231 in FIG.35 (b).

  When the information 3201 and 3202 include information such as a pointer indicating a specific position in a code string, a process of converting the information may be performed. Specifically, for example, when the information 3201 includes information indicating the position indicated by the arrow 3241, the information 3261 in the information 3261 is pointed to the position indicated by the arrow 3251 behind the position by the number Ns1 of insertion bits. The information indicating the position of is converted.

FIG. 1 is a block diagram illustrating a configuration of a moving image encoding device according to first and second embodiments of the present invention. FIG. 2 is a diagram showing a multiplexing rule in a multiplexer in the moving picture coding apparatus of FIG. FIG. 2 is a block diagram showing a configuration of an output encoding device in the video encoding device of FIG. FIG. 2 is a diagram illustrating an example of an output code string from the video encoding device in FIG. 1. Diagram showing examples of synchronization codes FIG. 3 is a block diagram showing a configuration of an error correction / detection switching encoder in the output encoder of FIG. FIG. 3 is a block diagram showing a configuration of a code sequence assembler in the output encoding device of FIG. FIG. 1 is a block diagram illustrating a configuration of a video decoding device according to first and second embodiments of the present invention. 8 is a block diagram showing a configuration of an input decoding device in the video decoding device of FIG. FIG. 9 is a block diagram showing a configuration of a code string decomposer in the input decoding device of FIG. FIG. 3 is a diagram showing an example of a code string obtained by a conventional error correction / detection code switching coding apparatus. FIG. 7 is a diagram illustrating an example of a synchronization code in which an error occurs due to bit addition / erasure of a transmission line for describing a second embodiment of the present invention FIG. 10 is a diagram for explaining the operation of the bit inserter in FIG. 3 according to the second embodiment. FIG. 9 is a diagram for explaining the operation of the synchronization detector and the insertion bit remover in FIG. 9 according to the second embodiment. FIG. 6 is a diagram illustrating an example of a code string in which synchronization protection is performed using frame length information in the first and second embodiments. FIG. 10 is a diagram illustrating another example of a code string in which synchronization protection is performed using frame length information in the first and second embodiments. FIG. 11 is a diagram showing still another example of a code string in which synchronization protection is performed using frame length information in the first and second embodiments. FIG. 9 is a block diagram illustrating a configuration of a moving image encoding device according to third and fourth embodiments of the present invention. FIG. 13 is a block diagram illustrating a configuration of an output encoding device of a video encoding device according to a third embodiment of the present invention. FIG. 14 is a block diagram illustrating an example of an output code string from a video encoding device according to a third embodiment of the present invention. FIG. 14 is a block diagram showing a configuration of a moving picture decoding apparatus according to the third and fourth embodiments of the present invention. FIG. 14 is a block diagram showing a configuration of an input decoding device of a video decoding device according to a third embodiment of the present invention. FIG. 14 is a block diagram illustrating a configuration of an output encoding device of a video encoding device according to a fourth embodiment of the present invention. FIG. 14 is a block diagram illustrating a configuration of an input decoding device of a video decoding device according to a fourth embodiment of the present invention. FIG. 14 is a block diagram illustrating an example of an output code string from a video encoding device according to a fourth embodiment of the present invention. The figure which shows the rule of the multiplexing in the multiplexer in the moving image coding apparatus FIG. 16 is a block diagram illustrating an example of an output code string from a video encoding device according to a fifth embodiment of the present invention. The figure which shows the other example of the multiplexing in the multiplexer in the moving image coding apparatus. FIG. 28 is a diagram illustrating an output code string processed for each synchronization code when the multiplexing illustrated in FIG. 28 is performed. FIG. 4 is a diagram showing a code table for explaining an example of a stuffing bit used in the present invention. 30 is a view for explaining the processing of the decoding apparatus when the stuffing bits of FIG. 30 are used. The figure for demonstrating the characteristic of the stuffing bit of FIG. The figure which shows the example of the output code string when the synchronous code insertion interval is shorter than the synchronous code Diagram showing an example of using synchronization codes of different lengths The figure which shows the output code string from the moving image coding apparatus which concerns on the 6th Embodiment of this invention.

Explanation of reference numerals

101: Motion Compensation Adaptive Predictor 102: Frame Memory 104: Discrete Cosine Transformer 105: Quantizer 107: Inverse Quantizer 108: Inverse Discrete Cosine Transformer 111: Multiplexer 131 ... Input Video Signal 200: Output Code Device 201 multiplexed code sequence 205 output code sequence 301 synchronization code 302 picture header 303 prediction mode information 304 motion vector information 305 DCT coefficient of prediction residual signal 402 synchronization code insertion position 212 bit insertion Device 211 code string assembler 603 latch circuit 604 error correction / detection encoder 701 counter 702 buffer 705 inserted bit generator 801 motion adaptive adaptive predictor 820 frame memory 807 inverse quantizer 808 ... Inverse discrete cosine transformer 811 ... Demultiplexer 800 ... Input decoding Device 850: Reproduced image signal 901, 1901: Synchronous code detector 902, 1902: Counter 903: Code string decomposer 904: Error correction / detection code decoder 905, 1905: Inserted bit remover 1005: Counter 1006: Comparator 1015: insertion bit generator 1101-1104: header information 1211: bit insertion device

Claims (8)

  Inserting a synchronization code into any one of a plurality of synchronization code insertion positions predetermined in advance in an output code string including a variable length code, and inserting any one of the plurality of synchronization code insertion positions in the output code string A stuffing bit is inserted immediately before the encoding method.   Inserting a synchronization code into any one of a plurality of synchronization code insertion positions predetermined in advance in an output code string including a variable length code, and inserting any one of the plurality of synchronization code insertion positions in the output code string A code string assembling means for inserting a stuffing bit immediately before the encoding apparatus.   The variable-length code is generated by compression-coding an image signal, and the output code string includes a multiplexed code string in which the variable-length code is multiplexed in frame units of the image signal. Item 3. The encoding device according to Item 2.   The variable-length code is generated by compression-coding an image signal, and the output code string includes a multiplexed code string in which the variable-length code is multiplexed in partial area units of a frame of the image signal. The encoding device according to claim 2, wherein:   The variable-length code is generated by compression-coding an image signal, the output code string includes a multiplexed code string in which the variable-length code is multiplexed in frame units of the image signal, and the code string assembling means. 3. Inserting a synchronization code at a synchronization code insertion position located immediately before or immediately after an end portion of each multiplex unit multiplexed in the frame unit of the multiplex code sequence. An encoding device according to claim 1.   The variable-length code is generated by compression-coding an image signal, and the output code sequence includes a multiplexed code sequence in which the variable-length code is multiplexed in partial area units of a frame of the image signal. The column assembling means inserts a synchronization code into a synchronization code insertion position located immediately before or immediately after the end of each multiplex unit multiplexed in units of the partial areas of the multiplex code sequence. The encoding device according to claim 2.   It further comprises code string conversion means for converting a code string other than the synchronization code at the synchronization code insertion position in the output code string so that the Hamming distance with the synchronization code becomes a predetermined value or more. The encoding device according to any one of claims 2 to 6, wherein:   The encoding apparatus according to claim 2, wherein the stuffing bit has a Hamming distance between the synchronization code and a part thereof that is equal to or greater than a predetermined value.

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