JP3654505B2 - Nonvolatile semiconductor memory device and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device and a method for controlling the same, and includes a plurality of banks each including a plurality of memory array blocks, and another is performed while writing or erasing a memory array in one bank. The present invention relates to a nonvolatile semiconductor memory device that can read a memory array in a bank and a control method thereof.
[0002]
[Prior art]
Flash EEPROM (block batch erasure type 1-chip flash memory) is rewritable and erasable, and has the feature of non-volatility where data is not lost even if power is not applied. And not. For this reason, flash EEPROMs are applied in a wide range of fields including portable information communication devices.
[0003]
However, in the conventional flash EEPROM, when a certain memory array block is written or erased, no other memory array block is accessed. Usually, it takes a long time of several μs to 10 μs for writing and several 100 ms to 1 s for erasing. For this reason, in recent years, as the speed of microprocessors has been increased, it has been a problem that the time required for writing or erasing data in the flash EEPROM is long.
[0004]
In order to solve such a problem, for example, Japanese Patent Laid-Open No. Hei 6-180999 discloses a technique capable of reading data from another memory array block when writing or erasing to a certain memory array block is performed. JP-A-7-281952, JP-A-5-54682, JP-A-10-144086, and the like.
[0005]
The prior art will be described below with reference to Japanese Patent Laid-Open No. 6-180999.
[0006]
FIG. 13 is a block diagram showing a schematic configuration of a conventional nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device includes banks 15 and 16 each including a plurality of memory array blocks, and a power supply voltage line 19 capable of supplying a write power supply voltage to each of the banks 15 and 16 via row decoders 35 and 36. A power supply voltage line 27 capable of supplying a power supply voltage for erasure, and a power supply voltage line 20 supplying a power supply voltage for reading. Which of the power supply voltage lines 19, 20 and 27 is connected to the banks 15 and 16 is switched by the power switches 17 and 18, and the switching is controlled by the bank switching control unit 21.
[0007]
The nonvolatile semiconductor memory device also includes a latch circuit 24 that latches the bank determination signal 23 as one address line, and a write / erase command identification unit 25 that controls the operation of the latch circuit 24. ing. For example, when the address is expressed by 17 bits of A0 to A16, A16 can be used as the bank determination signal 23. When the write / erase command identification unit 25 receives a VPPH signal and a WE (Write Enable) bar signal that are in a logic high state when the program / erase control voltage VPP is applied, the VPPH signal is in a logic high state. The signal 26 is output so that the latch circuit 24 latches the bank determination signal A16 at the falling edge of the WE bar signal. The bank determination signal stored in the latch circuit 24 is transmitted as a signal 28 to the bank switching control unit 21.
[0008]
Further, the nonvolatile semiconductor memory device is input with an output buffer 31, an output multiplexer 30 that switches from which bank read data is transmitted to the output buffer 31, and a path logic circuit 29 that controls switching of the multiplexer 30. A command decoder 32 for decoding the received command is provided.
[0009]
In the non-volatile semiconductor memory device, of the addresses to be written or erased input together with the write or erase command, for example, A16 is the bank determination signal 23, and the command is issued to either bank 15 or bank 16 Can be determined. The bank determination signal 23 is latched by the latch circuit 24 in response to a signal 26 from the write or erase command identification unit 25, and is transmitted to the bank switching control unit 21 as a signal 28.
[0010]
The bank switching control unit 21 switches the power switches 17 and 18 to connect the writing power supply voltage line 19 or the erasing power supply voltage line 27 to the bank (for example, the bank 15) for writing or erasing, and the remaining bank (for example, the bank). The read power supply voltage line 20 is connected to 16).
[0011]
Then, writing or erasing is performed by applying a power supply voltage for writing or erasing to the bank (for example, bank 15). At this time, when the memory array is read from the remaining bank (for example, bank 16), the pass logic circuit 29 outputs the output multiplexer 31 so that the data in the read side bank (for example, bank 16) is transmitted to the output buffer 31. 30 is switched, and the data in the memory array is read out.
[0012]
[Problems to be solved by the invention]
Writing or erasing the nonvolatile semiconductor memory device is performed by giving a writing or erasing command from an external CPU (Central Processing Unit).
[0013]
However, in the conventional nonvolatile semiconductor memory device described above, when a write or erase command is given once, the CPU monitors whether the write or erase has been completed and confirms that the write or erase has been completed. Then, the next write or erase command is input. For this reason, when writing a large amount of data or erasing a large number of memory array blocks, the CPU frequently checks the execution status of each writing or erasing to complete the processing quickly. The next write or erase command must be issued. As a result, the time for the CPU to perform other tasks is restricted.
[0014]
In order to solve this problem as much as possible, a method is considered in which several write or erase commands are collectively given to the nonvolatile semiconductor memory device. For example, when a next write command is issued during execution of the first write, the nonvolatile semiconductor memory device accepts the second write command and waits in the chip, and the first write command being executed It is conceivable to execute the second writing when the writing is completed.
[0015]
However, with respect to the conventional nonvolatile semiconductor memory device, during execution of the first write or erase, the second write command is received and waited in the chip, and the first write is completed when the first write is completed. If an attempt is made to add a function for executing the second writing, normal writing or erasing cannot be performed. In the above-described conventional nonvolatile semiconductor memory device, when the second write or erase command is for a bank different from the bank where the first write or erase is performed, the second write or erase command is used. Banks change when is entered. Then, the power supply voltage for writing or erasing applied to the bank currently being written or erased is switched to the power supply voltage for reading the memory (array) block. For this reason, the first writing or erasing operation is interrupted, and normal writing or erasing cannot be performed.
[0016]
Moreover, in the conventional nonvolatile semiconductor memory device, even when such a function for taking in the second write or erase command is not added, normal writing or erasure may not be performed. In the conventional nonvolatile semiconductor memory device described above, when the WE bar signal is mistakenly lowered during writing / erasing and the address at that time is different from the address of the bank during writing / erasing, the bank is switched. Then, the power supply voltage for writing or erasing applied to the bank currently being written or erased is switched to the power supply voltage for reading the memory (array) block. For this reason, the writing or erasing operation is interrupted and normal writing or erasing cannot be performed.
[0017]
Further, in the nonvolatile semiconductor memory device, for example, when it is desired to erase all the memory array blocks before shipment from the factory, if all the memory array blocks in the chip can be erased by issuing a single command, the memory array block can be erased. The required time can be shortened. When an erase command is to be issued for each memory array block, the next erase command is issued when the erase status is checked and the erase completion is confirmed as described above. This is because the time for boosting or stepping down the internal power supply voltage for erasing inside the chip is required each time, and the overall erasing time becomes long.
[0018]
However, even if an attempt is made to add a command (hereinafter referred to as a full chip erase command) function capable of erasing all the memory array blocks in the chip by issuing a command once, to the conventional nonvolatile semiconductor memory device. Is difficult. In the non-volatile semiconductor memory device, an address input together with an erase command and given to an address pin including a memory array block to be erased becomes a bank determination signal. This is because the erasing power supply voltage is applied only to the bank including the address.
[0019]
The present invention has been made to solve the above-described problems of the prior art. Data can be read from different banks during writing or erasing, and the next writing or erasing can be performed during execution of writing or erasing. In a nonvolatile semiconductor memory device having a function of waiting for a command in the chip, the next write or erase command issued during write or erase is for a bank different from the bank that is executing the write or erase operation. However, an object of the present invention is to provide a nonvolatile semiconductor memory device that can perform normal writing or erasing. The present invention also provides a non-volatile semiconductor memory device in which all memory array blocks can be erased with a single command input in a non-volatile semiconductor memory device having a structure in which an erasing power supply voltage is not simultaneously applied to a plurality of banks. The purpose is to provide.
[0020]
[Means for Solving the Problems]
The nonvolatile semiconductor memory device of the present invention has a plurality of banks each consisting of a plurality of memory array blocks that can be erased at once, and a first write or erase command is input to any one bank for writing or erasing And a second write or erase command is input while the other bank is being read, and the second write or erase is performed after the first write or erase operation is completed. In a non-volatile semiconductor memory device having a function, a bank determination signal for determining which bank is selected is input, an identification means for identifying whether the bank determination signal has changed, and the bank determination signal are input The bank determination signal is stored and updated by the output signal from the identification means, and the output signal from the latch means is input. And a bank switching control means for switching the selected bank through the signal, the object is achieved.
[0021]
A method for controlling a nonvolatile semiconductor memory device according to the present invention is a method for controlling a nonvolatile semiconductor memory device according to the present invention, wherein the second write or erase command is executed while the first write or erase is being executed. The bank determination signal is updated when it is input, and the identification means causes a bank determination signal when the first write or erase command is input, and a bank determination signal when the second write or erase command is input, If the comparison results match, after the first write or erase operation is completed, the second write or erase is performed while the write or erase power supply voltage is generated internally, If the comparison results do not match, after the first write or erase operation is finished, the internal generation of the write or erase power supply voltage is stopped and the read power supply is stopped. After the voltage is changed, the latch means is updated by the output signal from the identification means, and the read power supply voltage is applied to the bank that has completed the first write or erase operation by the output signal from the bank switching control means. A power supply voltage line for writing or erasing is connected to a bank specified by the second write or erase command, and then a power supply voltage for writing or erasing is generated internally to generate the second write or erase Erasing is performed, thereby achieving the above objective.
[0022]
The nonvolatile semiconductor memory device of the present invention has a plurality of banks each consisting of a plurality of memory array blocks that can be collectively erased, and is capable of collectively erasing only one memory array block included in any one bank, and In a nonvolatile semiconductor memory device having a full chip erase function capable of erasing all memory array blocks by one command input, an internal address register for storing an address generated internally, an address input from the outside, An output signal from the internal address register is input, a multiplexer that outputs a bank determination signal that determines which bank is selected, a bank determination signal that determines which bank is selected, and a bank determination signal Identification means for identifying whether or not the bank has changed, and the bank determination signal is input to And a bank switching control unit that receives the output signal from the latch unit and switches the selected bank according to the signal. This achieves the above object.
[0023]
The non-volatile semiconductor memory device control method of the present invention is a method of controlling the non-volatile semiconductor memory device of the present invention, and after a full chip erase command is input and an internally generated address is initialized, from the multiplexer, An internally generated address is output as the bank determination signal, and an erasing power supply voltage line is connected to the first bank by an output signal from the bank switching control means. The memory array blocks in the first bank are sequentially erased by incrementing and the second bank is designated by the next internally generated address after the last memory array block in the first bank is erased To update the bank determination signal,
The identification means compares the bank determination signal before the update with the bank determination signal after the update to detect the change of the bank, stops the internal generation of the erasing power supply voltage, and sets the read power supply voltage. The latch means is updated by the output signal from the identification means, the read power supply voltage line is connected to the first bank by the output signal from the bank switching control means, and the write power supply voltage to the second bank Then, the control is repeatedly performed to internally erase the memory array blocks in the second bank by sequentially generating the erase power supply voltage, sequentially increasing the internally generated addresses, and sequentially erasing the memory array blocks in the second bank. The memory array block is sequentially erased, thereby achieving the above object.
[0024]
The nonvolatile semiconductor memory device of the present invention stores a first address register that stores an address that is input when the first write or erase command is input, and an address that is input when the second write or erase command is input. A second address register, and the latch means may be configured to receive a bank determination signal output from the first address register or the second address register.
[0025]
A method for controlling a nonvolatile semiconductor memory device according to the present invention is a method for controlling a nonvolatile semiconductor memory device according to the present invention, wherein the second write or erase command is executed while the first write or erase is being executed. When input, the bank determination signal is updated, and the identification unit compares the bank determination signal output from the first address register with the bank determination signal output from the second address register, If the comparison results match, the second writing or erasing is performed while the writing or erasing power supply voltage is internally generated after the first writing or erasing operation is completed. In some cases, after the first write or erase operation is completed, the internal generation of the write or erase power supply voltage is stopped and the read power supply voltage is After that, the latch means is updated by the output signal from the identification means, and the read power supply voltage line is connected to the bank that has completed the first write or erase operation by the output signal from the bank switching control means. And connecting a writing or erasing power supply voltage line to a bank designated by the second writing or erasing command, and then internally generating a writing or erasing power supply voltage to perform the second writing or erasing. To achieve the above objective.
[0026]
The nonvolatile semiconductor memory device according to the present invention further includes a status register for storing an internal state, and the identification unit specifies a bank designated by the first write or erase command and a second write or erase command. When it is identified that the designated bank has changed, the status register may be stored as command input error information, and the information may be output to the outside from the status register.
[0027]
The operation of the present invention will be described below.
[0028]
In the present invention, as shown in the first embodiment to be described later, when writing or erasing is executed, when the next writing or erasing command is input, the bank that is executing writing or erasing, Whether or not the bank to be written or erased is the same is identified by the identifying means. For this identification, a bank determination signal that determines which bank is supplied with the write or erase power supply voltage is used.
[0029]
If the bank in which writing or erasing is being executed is the same as the bank in which the next writing or erasing is performed, there is no need to switch the power switch. Alternatively, the next writing or erasing is performed while the erasing power supply voltage is generated internally.
[0030]
If both banks are different, after the current write or erase operation is completed, the internal generation of the write or erase power supply voltage is stopped and the read power supply voltage is set. Then, the latch means for storing the bank determination signal is updated by the output signal from the identification means, and the power switch is switched by the bank switching control means. When the power switch is switched, the read power supply voltage line is connected to the bank where the write or erase operation is completed, and the write or erase power supply voltage line is connected to the bank specified by the next write or erase command. Thereafter, the power supply voltage for writing or erasing is generated internally, and the next writing or erasing is performed.
[0031]
According to the above configuration, normal writing or erasing can be performed even if the next writing or erasing command issued during writing or erasing is for a bank different from the bank that is executing the writing or erasing operation. Is possible.
[0032]
In the present invention, as shown in the second embodiment described later, when a full chip erase command is input, the internally generated address is initialized, and the internally generated address is output from the multiplexer as a bank determination signal. Then, after the erasing power supply voltage line is connected to the first bank by the output signal from the bank switching control means, the erasing power supply voltage is internally generated, and the internally generated addresses are sequentially increased to increase the memory in the first bank. The array blocks are erased sequentially.
[0033]
When the last memory array block of the first bank is erased, the bank needs to be switched. Therefore, the second bank is designated by the next internally generated address and the bank determination signal is updated.
[0034]
Then, the identification unit compares the bank determination signal before the update with the bank determination signal after the update to detect the change of the bank, stops the internal generation of the erasing power supply voltage, and sets the read power supply voltage. Thereafter, the latch means for storing the bank determination signal is updated by the output signal from the identification means, and the power switch is switched by the bank switching control means. When the power switch is switched, the read power supply voltage line is connected to the first bank, and the write power supply voltage line is connected to the second bank. Thereafter, an erasing power supply voltage is internally generated, and the internally generated addresses are sequentially increased to sequentially erase the memory array blocks in the second bank.
[0035]
When the last memory array block in the second bank is erased, the bank needs to be switched. Therefore, the third bank is designated by the next internally generated address and the bank determination signal is updated. By repeating such control, erasing is sequentially performed up to the last memory array block in the last bank.
[0036]
According to the above configuration, all memory array blocks can be erased by a single command input even in a structure in which an erasing power supply voltage is not simultaneously applied to a plurality of banks.
[0037]
In the present invention, as shown in the third embodiment described later, when the next write or erase command is input during execution of write or erase, the bank determination signal is updated by the identification means. The bank determination signal output from the first address register is compared with the bank determination signal output from the second address register.
[0038]
According to the above configuration, by increasing the number of address registers, it is possible to increase the number of write or erase commands that can be input continuously and processed.
[0039]
Furthermore, in the present invention, as shown in the fourth embodiment to be described later, the identification means identifies that the bank that is executing the writing or erasing and the bank specified by the next writing or erasing command have changed. If it is, the command input error information is stored in the status register, and the information is output from the status register to the outside.
[0040]
According to the above configuration, if the specification prohibits a write or erase command to be issued to a different bank during a write or erase operation, a write or erase command to a different bank is erroneously issued. However, it is possible to notify the outside that the input command is incorrect without switching the power source.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0042]
(Embodiment 1)
In the present embodiment, a nonvolatile semiconductor memory device that can continuously input a write or erase command and a control method thereof will be described.
[0043]
FIG. 1 is a block diagram illustrating a schematic configuration of the nonvolatile semiconductor memory device according to the first embodiment.
[0044]
This nonvolatile semiconductor memory device includes banks 1 and 2 each having a plurality of memory array blocks, and a power supply voltage line 5 capable of supplying a write power supply voltage to each of banks 1 and 2 via row decoders 135 and 136. And a power supply voltage line 8 capable of supplying an erasing power supply voltage, and a power supply voltage line 6 for supplying a read power supply voltage. Which of the power supply voltage lines 5, 6 and 8 is connected to the banks 1 and 2 is switched by the power switches 3 and 4, and the switching is controlled by the bank switching control unit 7.
[0045]
The nonvolatile semiconductor memory device also includes a latch circuit 11 that latches the bank determination signal 10 and an identification unit 12 that determines whether or not the bank determination signal has changed. The identification unit 12 is a part of an automatic write / erase controller 104 described later. The identification unit 12 stores a bank determination signal when a write or erase command is input, and compares it with the next bank determination signal to identify whether the bank determination signal has changed. Based on the identification result, a signal 13 for updating the contents of the latch circuit 11 to a new bank determination signal is output. The bank determination signal stored in the latch circuit 11 is transmitted to the bank switching control unit 7 as a signal 14.
[0046]
Further, this nonvolatile semiconductor memory device is inputted with an output buffer 102, an output multiplexer 101 that switches from which bank read data is transmitted to the output buffer 102, and a path logic circuit 100 that controls switching of the multiplexer 101. A command decoder 103 for decoding the received command.
[0047]
As the bank determination signal 10, for example, the address is expressed by 17 bits of A0 to A16, and when there are two banks 1 and 2 having the same capacity as shown in FIG. A16 can be used. Thereby, for example, when the number of bits (word length) of data that can be accessed simultaneously is 16 bits, in the configuration of FIG. 2, two banks of 64 k words × 16 bits size of bank 1 and bank 2 can be determined. it can.
[0048]
Alternatively, as shown in FIG. 3, for example, a configuration in which the capacity of the banks is different is possible, for example, the area of A16 = 1 and A15 = 1 is one bank and the remaining area is another bank. Further, as shown in FIG. 4, for example, an area of A16 = 0 and A15 = 0 is one bank, an area of A16 = 0 and A15 = 1 is one bank, A16 = 1, and A configuration having four banks is also possible, for example, the area of A15 = 0 is one bank, the area of A16 = 1 and the area of A15 = 1 is one bank. In the configuration of FIG. 3, it is possible to determine the bank 1 having a size of 64k words × 16 bits + 32k words × 16 bits and the bank 2 having a size of 32k words × 16 bits. Similarly, in the configuration of FIG. 4, it is possible to determine four banks of bank A to bank D each having a size of 32k words × 16 bits.
[0049]
The bank determination signal 10 in these cases can be output from, for example, a bank decoder (not shown) that decodes several address bits. For example, in the configuration of FIG. 3, as a bank decoder for creating a bank determination signal, a circuit that decodes two address bits A16 and A15 can be used, for example, as shown in FIG.
[0050]
In the configuration of FIG. 4, a circuit including a bank decoder and a latch circuit 11 can be used to create a bank determination signal, for example, as shown in FIG. 6. The circuit shown in FIG. 6 outputs 4-bit bank judgment signals 10a, 10b, 10c, and 10d by a combination of two address bits A16 and A15, and only one of the bank judgment signals is in a logic high state. become. Only one 4-bit output from the latch circuit 11 that latches the bank determination signal is in a logic high state. For example, if only 14 of the signals 14a, 14b, 14c, and 14d are in a logic high state, the bank switching control unit 7 connects the power supply voltage line 5 for writing or erasing to the bank of A16 and A15 = 1, Read power supply voltage lines 6 are connected to the other banks.
[0051]
Next, a method for controlling the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIG. Here, the bank configuration shown in FIG. 2 will be described, but the configuration shown in FIGS. 3 and 4 can be similarly controlled by the bank determination signal as described above.
[0052]
In the non-volatile semiconductor memory device, one address bit (for example, A16) of the addresses to be written or erased input together with the write or erase command is used as the bank determination signal 10, and either the bank 1 or the bank 2 is used. It can be determined whether a command has been input to the other bank. The bank determination signal 10 is latched by the latch circuit 24 and transmitted to the bank switching control unit 7 as a signal 14.
[0053]
The bank switching control unit 7 switches the power switch (for example, power switch 3) on the bank (for example, bank 1) side where writing or erasing is performed, and supplies the selected power source voltage line 5 or erasing to the selected bank (for example, bank 1). A power supply voltage line 8 is connected. In the remaining bank (for example, bank 2), the power supply voltage line 6 for reading is connected to the power switch (for example, power switch 4).
[0054]
Thereafter, a power supply voltage for writing or erasing is internally generated by an internally generated voltage generator (not shown) or the like (step S11), and writing or erasing is performed on the bank (for example, bank 1) (step S12). When the next write or erase command is input during the execution of the write or erase operation, the bank determination signal 10 is updated with the address.
[0055]
In the present embodiment, when the second write or erase command is input (step S13), the bank determination signal is identified by the identification unit 12 that identifies whether or not the bank determination signal has changed without immediately updating the latch circuit 11. Capture the signal. Then, it is compared with the bank determination signal when the first write or erase command is input (step S14). Note that the PROG and ERAS signals input to the identification unit 12 are output signals from the command decoder, and PROG is in a logic high state at the time of a write command, and ERAS is in a logic high state at the time of an erase command.
[0056]
As a result, if the bank determination signal has not changed, after the write or erase operation by the first command is completed, the next write or erase is performed while the write or erase power supply voltage is generated internally (step (Return to S11).
[0057]
On the other hand, when the bank determination signal changes, after the write or erase operation by the first command is completed, the internal generation of the write or erase power supply voltage is stopped and the read power supply voltage is set (step S15). Here, the read power supply voltage is used to suppress the generation of noise when the power switch is switched. Thereafter, the latch circuit 11 is updated by the signal 13, the output of the bank switching control unit 7 is changed, and the write power supply voltage line 5 or the erase power supply voltage line 8 is connected to the bank selected by the second command. Further, the read power supply voltage line 6 is connected to the bank selected by the first command (step S16). Then, the power supply voltage for writing or erasing is internally generated, the power supply voltage for writing or erasing is supplied to the bank selected by the second command, and the writing or erasing is executed (return to step S11).
[0058]
Next, when there is no continuous writing or erasing command, the power source voltage for writing or erasing is stopped (step S17).
[0059]
In the present embodiment, the identification unit 12 for identifying whether or not the bank determination signal has changed can be realized by providing the automatic write / erase controller 104 with an identification function, for example. The automatic write / erase controller 104 stores an algorithm for application of a write pulse and an erase pulse, and a write inspection and an erase inspection, and controls writing and erasing according to the algorithm.
[0060]
In the algorithm of the automatic write / erase controller 104,
(1) Compare the bank (bank determination signal) in which the second writing or erasing is performed with the bank (bank determination signal) in which the first writing or erasing is performed at the end of the first writing or erasing;
(2) If they match, the bank has not changed, so the power supply voltage for writing or erasing is left internally generated, the power switch is not switched,
(3) If there is a mismatch, stop the internal generation of the power supply voltage for writing or erasing, control the signal 13 and update the latch circuit 11, thereby switching the power switch by the bank switching control unit 7,
(4) Thereafter, the power supply voltage for writing or erasing is internally generated again.
The above identification function can be realized by adding the algorithm.
[0061]
(Embodiment 2)
In the present embodiment, a non-volatile semiconductor memory device capable of realizing full chip erase for a plurality of banks and a control method thereof will be described.
[0062]
FIG. 8 is a block diagram illustrating a main part of the nonvolatile semiconductor memory device according to the second embodiment.
[0063]
This nonvolatile semiconductor memory device includes a multiplexer 105 that switches whether the bank determination signal 10 shown in FIG. 1 is generated from an externally input address or an address generated by the automatic write / erase controller 104, and an automatic And an internally generated address register 106 for storing addresses generated internally by the write / erase controller 104. Other than that, the configuration can be the same as that of the nonvolatile semiconductor memory device of Embodiment 1 shown in FIG.
[0064]
Next, a method for controlling the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIG.
[0065]
When a full chip erase command is input to the nonvolatile semiconductor memory device, the automatic write / erase controller 104 initializes an internally generated address (step S21). For example, the initial value is 0 and the address indicates the first block of the memory array. Then, the automatic write / erase controller 104 switches the multiplexer 105 to transmit the internally generated address as the bank determination signal 10. The bank determination signal 10 (for example, indicating bank 1) is taken into the latch circuit 11, and the first bank (for example, bank 1) is first connected to the erasing power supply voltage line 8 by the bank switching control unit 7 (step S22). ). Thereafter, an erasing power supply voltage is generated internally (step S23), and data in a certain memory array block (selected block) in the first bank (bank 1) is erased (step S24).
[0066]
Next, the block address is incremented by 1 (step S25), and it is identified whether or not the erasure of all the memory array blocks in the chip is completed (step S26). When all the memory array blocks in the chip are not erased, it is identified whether or not the bank to be erased next matches the bank that has been erased this time, that is, whether or not the bank judgment signal has changed. (Step S27). If the bank determination signal has not changed, the next selected block is erased while the erasing power supply voltage is internally generated (return to step S24). By repeating this, the internally generated addresses are sequentially increased, and when the last memory array block of the first bank (bank 1) is erased, the next internally generated address indicates the second bank (bank 2).
[0067]
At this time, the bank determination signal 10 changes, but the latch circuit 11 is not immediately updated, and the bank determination signal is taken into the identification unit 12 for identifying whether or not the bank determination signal has changed. Then, it is compared with the bank determination signal at the time of erasing the previous memory array block (step S27). When it is detected that the bank has changed, the generation of the erasing power supply voltage is stopped and the read power supply voltage is set (step S27). S28). Then, the latch circuit 11 is updated by the signal 13 (step S29), the power source switches 3 and 4 are switched by the bank switching control unit 7, the read power source voltage line 6 is connected to the bank 1, and the erasing is performed on the bank 2. A power supply voltage line 8 is connected. Thereafter, an erasing power supply voltage is generated internally (returning to step S23), and the memory array blocks in the second bank (bank 2) are sequentially erased. Such control is repeated until the last memory array block in the last bank is sequentially erased. When all the blocks are erased, the generation of the erasing power supply voltage is stopped and the power supply voltage for reading is restored ( Step S30).
[0068]
(Embodiment 3)
In the present embodiment, a nonvolatile semiconductor memory device provided with an address register for storing an address input at the time of writing or command input and a control method thereof will be described. Here, for the sake of simplification of explanation, a case where the number of address registers is two will be described. However, by increasing the number of registers, the number of write / erase commands that can be continuously input and processed can be increased. It becomes possible. .
[0069]
FIG. 10 is a block diagram illustrating a main part of the nonvolatile semiconductor memory device according to the third embodiment.
[0070]
This nonvolatile semiconductor memory device includes an address register 108 for storing an address input at the time of inputting a command for the first write or erase command, and an address register 109 for the next write or erase command. The outputs of the address registers 108 and 109 become the bank determination signal 10 via the multiplexer 107. The address registers 108 and 109 are input together with a command input, and an address to be written or erased is transmitted via the multiplexer 110. The multiplexer 110 is connected to the address register switch 111, and the address register switch 111 is connected to the command decoder 103. The command decoder 103 is connected to the automatic write / erase controller 104, and the automatic write controller 104 is connected to the multiplexer 107. Other than that, the configuration can be the same as that of the nonvolatile semiconductor memory device of Embodiment 1 shown in FIG.
[0071]
When the first write or erase command is input, the command decoder 103 sends a signal to the address register switch 111. Then, the address register switch 111 switches the multiplexer 110 so that the address at the time of command input is transmitted to the first address register (for example, the address register 108).
[0072]
When the second write or erase command is input, the command decoder 103 sends a signal to the address register switch 111 again. Then, the address register switch 111 switches the multiplexer 110 so that the address at the time of command input is transmitted to the second address register (for example, the address register 109).
[0073]
The multiplexer 107 is switched so that the output of the first address register (for example, the address 108) becomes the bank determination signal 10 when the first write or erase command is input.
[0074]
Next, a method for controlling the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIG.
[0075]
When a first write or erase command is input to the nonvolatile semiconductor memory device, the command decoder 103 starts the automatic write / erase controller 104. Then, a power supply voltage for writing or erasing is generated internally (step S31), and a writing or erasing operation is executed (step S32).
[0076]
When the writing or erasing is completed, it is identified whether or not the next writing or erasing command has been issued (step S33). If the next write or erase command has not been issued, generation of the power supply voltage for writing or erasing is stopped and the power supply voltage for reading is set (step S41).
[0077]
On the other hand, when the next write or erase command has been issued, the current bank judgment signal (* 1) is used to identify whether or not the bank judgment signal has changed. (Included in 104) (step S34). In the first embodiment, the address register may be shared between the input of the first command and the input of the second command, so that the first register is not overwritten when the next command is input. The bank determination signal is stored in the identification unit 12 when a command is input. On the other hand, in the third embodiment, different address registers are prepared when the first command is input and when the second command is input, so that the bank determination signal is stored in the identification unit 12 simultaneously with the command input. It does not have to be. Further, by storing the bank determination signal in the identification unit 12 immediately before the determination, for example, the register that stores the bank determination information in the identification unit 12 can be temporarily used for other purposes.
[0078]
Next, the multiplexer 107 is switched, and the signal (bank determination signal 10) input to the latch circuit 7 is used for the next writing or erasing from the bank determination signal output by the current address register (first address register). The bank determination signal output from the address register (second address register) is set (step S35). Then, the bank determination signal (* 2) for the next writing or erasing currently input to the latch circuit 7 is stored in the identification unit 12 for identifying whether or not the bank determination signal has changed (step S36). ).
[0079]
Thereafter, the discriminator 12 discriminates whether or not the first bank judgment signal (* 1) matches the second bank judgment signal (* 2) (step S37). As a result, if the two bank determination signals match, the bank has not changed, and the next writing or erasing is executed as it is without stopping the generation of the writing or erasing power supply voltage (returning to step S32).
[0080]
On the other hand, if the bank determination signals do not match, the bank changes, so that the internal generation of the write or erase power supply voltage is stopped and the read power supply voltage is set (step S39). Thereafter, the latch circuit 11 is updated by the signal 13. As a result, the output of the bank switching control unit 7 is changed, and the write power supply voltage line 5 or the erase power supply voltage line 8 is connected to the bank to be written or erased next. Then, the power supply voltage for writing or erasing is generated internally, and the next writing or erasing is executed (return to step S31).
[0081]
In the above description, as in FIG. 1, the number of banks having the same capacity is two and the bank determination signal 10 can be switched by 1 bit. However, as shown in FIGS. This embodiment can also be applied to a configuration having two or more banks having different capacities as shown in FIGS. 2 and 3 by adding a bank decoder after the multiplexer 107 in FIG.
[0082]
(Embodiment 4)
In the present embodiment, a nonvolatile semiconductor memory device having a specification in which issuing of a write or erase command to a different bank is prohibited during execution of write or erase and a control method thereof will be described. This is effective when, for example, data that should not be rewritten is stored in a certain bank, such as a system program.
[0083]
FIG. 12 is a block diagram illustrating a main part of the nonvolatile semiconductor memory device according to the fourth embodiment.
[0084]
This nonvolatile semiconductor memory device includes a status register 200 and a multiplexer 201 that switches whether to transmit the output of the status register 200 or the data of the memory array to the output buffer 102. Other than that, the configuration can be the same as that of the nonvolatile semiconductor memory device of Embodiment 1 shown in FIG. 1 or Embodiment 3 shown in FIG.
[0085]
First, a control method will be described for a configuration in which a status register 200 and a multiplexer 201 are added to the nonvolatile semiconductor memory device of Embodiment 1 shown in FIG.
[0086]
In the nonvolatile semiconductor memory device, it is determined to which bank of the bank 1 or the bank 2 the command is input based on the address of the first input write or erase command. The bank determination signal 10 is latched by the latch circuit 24 and transmitted to the bank switching control unit 7 as a signal 14.
[0087]
The bank switching control unit 7 switches the power switch (for example, power switch 3) on the bank (for example, bank 1) side where writing or erasing is performed, and supplies the selected power source voltage line 5 or erasing to the selected bank (for example, bank 1). A power supply voltage line 8 is connected. Then, the remaining bank (for example, bank 2) switches the power switch (for example, power switch 4) to connect the read power voltage line 6.
[0088]
Thereafter, a power supply voltage for writing or erasing is internally generated by an internally generated voltage device (not shown) or the like, and writing or erasing is performed on the bank (for example, bank 1). When the next write or erase command is input during the execution of the write or erase operation, the bank determination signal 10 is updated with the address.
[0089]
When the second write or erase command is input, the bank determination signal is taken into the identification unit 12 for identifying whether or not the bank determination signal has been changed without immediately updating the latch circuit 11. Then, it is compared with the bank determination signal stored when the first write or erase command is input.
[0090]
As a result, if the bank determination signal has not changed, after the write or erase operation by the first command is completed, the next write or erase is performed while the write or erase power supply voltage is generated internally.
[0091]
On the other hand, when the bank determination signal changes, a code indicating that the second command is a prohibited control is stored in the status register 200. Then, the information stored in the status register 200 is notified to the outside through the multiplexer 201 and the output buffer 102.
[0092]
Next, a control method will be described for the configuration in which the status register 200 and the multiplexer 201 are added to the nonvolatile semiconductor memory device according to the third embodiment illustrated in FIG.
[0093]
This nonvolatile semiconductor memory device includes an address register 108 for storing an address input at the time of inputting a command for the first write or erase command, and an address register 109 for the next write or erase command. The outputs of the address registers 108 and 109 become the bank determination signal 10 via the multiplexer 107.
[0094]
Then, when the first writing or erasing is completed, the identification unit 12 (in this case, included in the automatic writing / erasing controller 104) for identifying whether or not the bank determination signal included in the automatic writing / erasing controller 104 has changed. To store. Thereafter, the address registers 108 and 109 are switched for the next writing or erasing. As a result, the bank determination signal 10 is switched to the next writing or erasing. The bank determination signal is stored again in the identification unit 12 to identify whether the bank determination signal has changed.
[0095]
As a result, if both bank determination signals match, the bank has not changed, and the next write or erase is executed without stopping the internal power supply voltage generator (not shown) for writing or erasing. .
[0096]
On the other hand, if the bank determination signals do not match, the internal generation of the write or erase power supply voltage is stopped, and a code indicating that the second command is a prohibited control is stored in the status register 200. Then, the information stored in the status register 200 is notified to the outside through the multiplexer 201 and the output buffer 102.
[0097]
【The invention's effect】
As described above in detail, according to the present invention, it is possible to read data from different banks during writing or erasing, and to wait for the next writing or erasing command in the chip during execution of writing or erasing. A nonvolatile semiconductor memory device having the above can be realized. Therefore, even when a large amount of data is written or a large number of memory array blocks are erased, these processes can be completed quickly, and the time for the CPU to perform other tasks is not limited. Furthermore, even if the next write or erase command issued during writing or erasing is for a bank different from the bank that is executing the writing or erasing operation, normal writing or erasing can be performed.
[0098]
Further, according to the present invention, the power supply voltage for erasure is not simultaneously applied to the row decoders and column decoders of a plurality of banks, and only one memory array block in any one of the plurality of banks is collectively erased In a possible non-volatile semiconductor memory device, full-chip erase can be performed so that all memory array blocks can be erased by a single command input. Therefore, for example, when it is desired to erase all the memory array blocks before factory shipment, the time required for the erasure can be shortened.
[0099]
Furthermore, according to the present invention, in a nonvolatile semiconductor memory device having a specification that prohibits a write or erase command to be issued to a different bank during execution of a write or erase operation, When an erase command is issued, the fact that the input command is incorrect can be notified to the outside. Therefore, for example, when data that must not be rewritten, such as a system program, is stored in a certain bank, it is very effective.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a first embodiment.
FIG. 2 is a diagram illustrating a configuration example in which two banks having the same capacity are provided.
FIG. 3 is a diagram illustrating a configuration example in which two banks having different capacities are provided.
FIG. 4 is a diagram illustrating a configuration example in which four banks having the same capacity are provided.
5 is a diagram illustrating an example of a bank decoder that generates a bank determination signal for the bank configuration of FIG. 3;
6 is a diagram illustrating an example of a bank decoder and a latch circuit that generate a bank determination signal for the bank configuration of FIG. 4;
FIG. 7 is a flowchart for explaining a control method of the nonvolatile semiconductor memory device according to the first embodiment;
FIG. 8 is a block diagram showing a configuration of an important part of the nonvolatile semiconductor memory device according to the second embodiment.
FIG. 9 is a flowchart for explaining a control method of the nonvolatile semiconductor memory device according to the second embodiment;
FIG. 10 is a block diagram illustrating a configuration of an important part of the nonvolatile semiconductor memory device according to the third embodiment.
FIG. 11 is a flowchart for explaining a control method of the nonvolatile semiconductor memory device according to the third embodiment;
12 is a block diagram showing a configuration of an important part of the nonvolatile semiconductor memory device according to Embodiment 4. FIG.
FIG. 13 is a block diagram showing a configuration of a conventional nonvolatile semiconductor memory device.
[Explanation of symbols]
1, 2, 15, 16 Bank composed of multiple memory array blocks
3, 4, 17, 18 Power switch
5, 19 Power supply voltage line capable of supplying power supply voltage for writing
6, 20 Power supply voltage line for supplying read power supply voltage
7, 21 Bank switching control unit
8, 27 Power supply voltage line capable of supplying power supply voltage for erasure
10, 10a, 10b, 10c, 10d, 23 Bank judgment signal
11, 24 Latch circuit
12 Identification part of whether or not the bank judgment signal has changed
13, 26 Latch update control signal
14, 14a, 14b, 14c, 14d, 28 Latch output
25 Write or erase command identification part
29, 100 path logic circuit
30, 101 output multiplexer
31, 102 Output buffer
32, 103 Command decoder
35, 36, 135, 136 row decoder
104 Automatic programming / erasing controller
105, 107, 110, 201 Multiplexer
106 Internally generated address register
108, 109 Address register
111 Address register switcher
200 Status register

Claims (7)

It has a plurality of banks each consisting of a plurality of memory array blocks that can be collectively erased,
A first write or erase command is input to any one bank to perform write or erase, while a second bank is being read while a second write or erase command is input, In a nonvolatile semiconductor memory device having a function of performing the second writing or erasing after the first writing or erasing operation is completed,
A bank determination signal for determining which bank to select, and an identification means for identifying whether or not the bank determination signal has changed;
Latch means for receiving the bank judgment signal and storing the bank judgment signal and being updated by an output signal from the identification means;
A non-volatile semiconductor memory device comprising: bank switching control means for receiving an output signal from the latch means and switching a selected bank according to the signal. A method for controlling the nonvolatile semiconductor memory device according to claim 1, comprising:
The bank determination signal is updated when the second write or erase command is input during execution of the first write or erase,
The identification means compares the bank determination signal when the first write or erase command is input with the bank determination signal when the second write or erase command is input,
If the comparison results match,
After the first writing or erasing operation is completed, the second writing or erasing is performed while the writing or erasing power supply voltage is generated internally,
If the comparison results do not match,
After the first write or erase operation is finished, the internal generation of the write or erase power supply voltage is stopped to make it a read power supply voltage, and then the latch means is updated by an output signal from the identification means, In response to an output signal from the bank switching control means, a read power supply voltage line is connected to the bank that has completed the first write or erase operation, and the bank specified by the second write or erase command is written or erased. A method for controlling a nonvolatile semiconductor memory device, in which a second power supply voltage line is connected, and then a power supply voltage for writing or erasing is internally generated to perform the second writing or erasing. It has a plurality of banks each consisting of a plurality of memory array blocks that can be collectively erased,
In a non-volatile semiconductor memory device having a full chip erase function in which only one memory array block included in an arbitrary bank can be erased at once and all memory array blocks can be erased by one command input,
An internal address register for storing internally generated addresses;
A multiplexer that receives an address input from the outside and an output signal from the internal address register and outputs a bank determination signal for determining which bank to select;
A bank determination signal for determining which bank to select, and an identification means for identifying whether or not the bank determination signal has changed;
Latch means for receiving the bank judgment signal and storing the bank judgment signal and being updated by an output signal from the identification means;
A non-volatile semiconductor memory device comprising: bank switching control means for receiving an output signal from the latch means and switching a selected bank according to the signal. A method for controlling the nonvolatile semiconductor memory device according to claim 3, comprising:
After the full chip erase command is input and the internally generated address is initialized, the internally generated address is output as the bank determination signal from the multiplexer.
After connecting an erasing power supply voltage line to the first bank by an output signal from the bank switching control means,
An internal power supply voltage for erasing is generated internally, and internal generated addresses are sequentially increased to sequentially erase the memory array blocks in the first bank,
After erasing the last memory array block of the first bank, the second bank is designated by the next internally generated address and the bank determination signal is updated,
The identification means detects the change of the bank by comparing the bank determination signal before update with the bank determination signal after update,
After stopping the internal generation of the erasing power supply voltage to the read power supply voltage, the latch means is updated by the output signal from the identification means,
In accordance with an output signal from the bank switching control means, a read power supply voltage line is connected to the first bank, a write power supply voltage line is connected to the second bank,
Thereafter, the control of repeatedly generating the power supply voltage for erasing, sequentially increasing the internally generated addresses, and sequentially erasing the memory array blocks in the second bank is performed.
A method for controlling a nonvolatile semiconductor memory device, wherein erasing is sequentially performed up to the last memory array block in the last bank. A first address register for storing an address input when the first write or erase command is input;
A second address register for storing an address input when the second write or erase command is input,
The nonvolatile semiconductor memory device according to claim 1, wherein a bank determination signal output from the first address register or the second address register is input to the latch unit. A method for controlling the nonvolatile semiconductor memory device according to claim 5, comprising:
The bank determination signal is updated when the second write or erase command is input during execution of the first write or erase,
The identification unit compares the bank determination signal output from the first address register with the bank determination signal output from the second address register,
If the comparison results match,
After the first writing or erasing operation is completed, the second writing or erasing is performed while the writing or erasing power supply voltage is internally generated,
If the comparison results do not match,
After the first writing or erasing operation is finished, the internal generation of the writing or erasing power supply voltage is stopped to make it a reading power supply voltage, and then the latch means is updated by an output signal from the identification means, A power supply voltage line for reading is connected to the bank that has completed the first writing or erasing operation according to an output signal from the bank switching control means, and writing or erasing is performed on the bank specified by the second writing or erasing command. A method for controlling a nonvolatile semiconductor memory device, in which a second power supply voltage line is connected, and then a power supply voltage for writing or erasing is internally generated to perform the second writing or erasing. It further includes a status register for storing the internal state,
When the identification means identifies that the bank designated by the first write or erase command and the bank designated by the second write or erase command have changed, the command input error information is used as the command input error information. 6. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device stores the information in a status register and outputs the information to the outside from the status register.

Images