JP3653150B2 - Semiconductor laser chip and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides a semiconductor laser chip that can be incorporated with high accuracy into an optical communication module. Pou And its manufacturing method.
[0002]
[Prior art]
As a method for incorporating a semiconductor laser chip into an optical communication module, there are an “active alignment method” and a “passive alignment method”. In the active alignment method, the optical axis is aligned with the optical fiber while the semiconductor laser chip is emitting light, and the semiconductor laser chip is fixed to the submount at a position where a predetermined light output can be obtained.
[0003]
On the other hand, the passive alignment method performs positioning by superimposing an alignment mark formed in advance on the semiconductor laser chip and an alignment mark formed on the submount without causing the semiconductor laser chip to emit light. Fix the chip to the submount.
[0004]
In general, the alignment of the optical axis takes a long time, so the passive alignment method that does not require alignment of the optical axis has better throughput than the active alignment method that requires alignment of the optical axis. it can.
[0005]
However, in the passive alignment method, since the positional accuracy of the alignment mark formed on the semiconductor laser chip with respect to the waveguide (light emitting point) greatly affects the coupling efficiency of the laser emitted light to the optical fiber, the positional accuracy must be improved. Therefore, an optical communication module having a good coupling efficiency cannot be realized.
[0006]
A conventional optical semiconductor device and a passive alignment method using the same will be described with reference to FIGS. FIG. 26 is a diagram showing a conventional semiconductor laser chip, in which (a) is a plan view of the conventional semiconductor laser chip and (b) is a diagram of the conventional semiconductor laser chip viewed from the line AA ′ in FIG. Each cross section is shown. FIG. 27 is a diagram showing a passive alignment method using a conventional semiconductor laser chip.
[0007]
26A and 26B, a conventional semiconductor laser chip 1 includes a substrate 2, an active layer 3 (optical waveguide 3a), a block layer 6, a contact layer 7, an insulating film 8, and a surface electrode. 9, a pair of alignment marks 10 formed simultaneously with the front surface electrode 9, and a back surface electrode 11. The alignment mark 10 is made of the same material as the surface electrode 9.
[0008]
In FIG. 27, the submount 20 includes a substrate 21, an optical fiber 22 placed on the substrate 21, a metal pattern 24 formed on the substrate 21 and having a pair of alignment marks 23, and a metal pattern 24. And a solder material 25 formed. The pair of alignment marks 23 are holes of the metal pattern 24 and are provided at positions symmetrical with respect to the center line of the optical fiber 22.
[0009]
Next, the conventional passive alignment method described above will be described. The semiconductor laser chip 1 of FIG. 27A is die-bonded to the submount 20 of FIG. 7B while being aligned with infrared rays as shown in FIG.
[0010]
First, the semiconductor laser chip 1 is transferred onto the submount 20 by, for example, a vacuum suction device as rough alignment. The rough alignment is performed by pattern recognition using the metal pattern 24 indicating the mounting position of the semiconductor laser chip 1 on the submount 20 and the infrared transmitted light of the front electrode 9 or the back electrode 11 of the semiconductor laser chip 1. For example, the semiconductor laser chip 1 is irradiated with infrared rays, and the transmitted light is detected by a CCD (Charge Coupled Device) installed on the back side of the submount 20.
[0011]
At this time, as shown in FIG. 27C, the alignment mark 10 of the semiconductor laser chip 1 that does not transmit infrared rays and the alignment mark 23 on the side of the submount 20 that transmits infrared rays are infrared rays. When seen through, they appear to overlap.
[0012]
Here, alignment is performed so that the center of gravity of the alignment marks 10 and 23 coincide with each other while transmitting infrared rays. Then, the metal pattern 24 and the back electrode 11 are bonded using the solder material 25. Thereafter, an electrode for driving the semiconductor laser chip 1 and a photodiode for monitoring the output laser light are mounted on the submount 20 to produce an optical communication module.
[0013]
[Problems to be solved by the invention]
In the conventional semiconductor laser chip as described above, the optical waveguide 3a and the alignment mark 10 are separately formed, that is, the alignment mark 10 is formed together with the surface electrode 9 in a step after the step of forming the active layer 3. Therefore, reflecting the limit of the overlay accuracy of the mask aligner, as shown in FIG. 26A between the center line of the optical waveguide 3a and the center line (bisector) of the pair of alignment marks 10. There is a problem that the deviation B is inevitably generated.
[0014]
In addition, since this deviation amount B usually occurs on the order of several micrometers (μm), it is very difficult to realize the submicron order accuracy required for the assembly of the passive alignment method. FIG. As shown in FIG. 5, when the semiconductor laser chip 1 having the deviation B is used, the coupling efficiency between the optical waveguide 3a and the optical fiber 22 is deteriorated, and it is difficult to obtain an optical communication module having a good coupling efficiency with a high yield. There was a problem.
[0015]
The present invention has been made to solve the above-described problems, and can improve the positional accuracy of the alignment mark with respect to the optical waveguide. As a result, an optical communication module having high coupling efficiency and high yield can be obtained. Semiconductor laser chip And it aims at obtaining the manufacturing method.
[0016]
[Means for Solving the Problems]
According to this invention Semiconductor laser chip A substrate, an optical waveguide formed on the substrate, and the optical waveguide At the same time, a pair of circular shapes that are formed on the substrate and formed at positions symmetrical to the optical waveguide and do not transmit infrared rays With alignment mark A conductive layer formed on the substrate so as to cover the alignment mark, an insulating film formed on the conductive layer except directly above the optical waveguide, and formed on the insulating film and the conductive layer. A front electrode formed on the back surface of the substrate, It is equipped with.
[0018]
Further, according to the present invention Semiconductor laser chip The conductive layer is composed of a block layer formed on the substrate, and a contact layer formed on the optical waveguide and the block layer.
[0019]
Further, according to the present invention Semiconductor laser chip The conductive layer includes a first cladding layer formed on the optical waveguide and the alignment mark, and a second cladding layer formed on the substrate.
[0020]
Further, according to the present invention Semiconductor laser chip Is an active layer formed simultaneously with the optical waveguide and the alignment mark.
[0021]
Further, according to the present invention Semiconductor laser chip Is formed on the first active layer and the first active layer formed simultaneously with the optical waveguide, and has an energy band gap narrower than that of the first active layer or a layer thickness of the first active layer. A second active layer thicker than the first active layer, and the alignment mark is the second active layer.
[0022]
Further, according to the present invention Semiconductor laser chip Is formed under the first active layer and the first active layer formed simultaneously with the optical waveguide, and has an energy band gap narrower than that of the first active layer or a layer thickness of the first active layer. A second active layer thicker than the first active layer, and the alignment mark is the second active layer.
[0023]
Further, according to the present invention Semiconductor laser chip Is an active layer in which the optical waveguide and the alignment mark are formed at the same time, and the active layer serving as the alignment mark is thicker than the active layer serving as the optical waveguide.
[0024]
Further, according to the present invention Semiconductor laser chip Is an active layer in which the optical waveguide and the alignment mark are formed at the same time, and an electrical separation groove is provided between them.
[0025]
Further, according to the present invention Semiconductor laser chip The alignment mark is made of a material whose energy band gap is narrower than the surrounding material.
[0026]
Further, according to the present invention Semiconductor laser chip The alignment mark is made of InGaAsP or InGaAs, and the periphery of the alignment mark is made of InP.
[0027]
Further, according to the present invention Semiconductor laser chip The alignment mark is made of InGaAs, and the periphery of the alignment mark is made of GaAs or AlGaAs.
[0028]
Further, according to the present invention Semiconductor laser chip The manufacturing method includes the steps of forming an optical waveguide on a substrate, and the optical waveguide At the same time on the substrate Forming alignment marks; and After forming the optical waveguide and the alignment mark, forming a conductive layer on the substrate so as to cover the alignment mark, and forming an insulating film on the conductive layer except directly above the optical waveguide A step of forming a surface electrode on the insulating film and the conductive layer; a step of forming a back electrode on the back surface of the substrate; Is included.
[0030]
Further, according to the present invention Semiconductor laser chip In the manufacturing method, the step of forming the conductive layer includes the step of forming a block layer on the substrate after forming the optical waveguide, and the step of forming a contact layer on the optical waveguide and the block layer. Is included.
[0031]
Further, according to the present invention Semiconductor laser chip In the manufacturing method, the step of forming the conductive layer includes a step of forming a first cladding layer on the optical waveguide and the alignment mark, and a step of forming a second cladding layer on the substrate.
[0032]
Further, according to the present invention Semiconductor laser chip In this manufacturing method, the optical waveguide and the alignment mark are active layers, and both are formed simultaneously.
[0033]
Further, according to the present invention Semiconductor laser chip The manufacturing method further includes a step of forming a first active layer on the substrate simultaneously with the optical waveguide, and an energy band gap on the first active layer is narrower than that of the first active layer. Or a step of forming a second active layer that is thicker than the first active layer and serves as the alignment mark.
[0034]
Further, according to the present invention Semiconductor laser chip The manufacturing method further includes a step of forming a first active layer on the substrate simultaneously with the optical waveguide, and an energy band gap below the first active layer below the first active layer. Or a step of forming a second active layer that is thicker than the first active layer and serves as the alignment mark.
[0035]
Further, according to the present invention Semiconductor laser chip In this manufacturing method, the optical waveguide and the alignment mark are active layers, and the active layer serving as the alignment mark is thicker than the active layer serving as the optical waveguide, and both are formed simultaneously. .
[0036]
Further, according to the present invention Semiconductor laser chip In this manufacturing method, the optical waveguide and the alignment mark are active layers, and both are formed at the same time, and further, an electrical separation groove is formed between the two.
[0037]
Furthermore, according to the present invention Semiconductor laser chip The manufacturing method further includes a step of cleaving the wafer based on the alignment mark.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
Embodiment 1 of the present invention will be described with reference to FIGS. 1A and 1B are diagrams showing a semiconductor laser chip according to Embodiment 1 of the present invention, in which FIG. 1A is a plan view of the semiconductor laser chip, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. Sections of the semiconductor laser chip as seen from the line are respectively shown. 2 to 4 are views showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the first embodiment. Further, FIG. 5 is a diagram showing a passive alignment method using the semiconductor laser chip. In addition, in each figure, the same code | symbol shows the same or equivalent part.
[0039]
1A and 1B, a semiconductor laser chip 1A according to Embodiment 1 of the present invention includes a p-type InP substrate 2, an InGaAsP active layer 3 (optical waveguide 3a) formed on the substrate 2, and The pn-pInP blocking layer 6 formed on the substrate 2, the contact layer 7 formed thereon, the insulating film 8 formed on the contact layer 7, and the insulating film 8 The surface electrode 9 formed, a pair of alignment marks 10A formed simultaneously with the optical waveguide 3a, and the back electrode 11 formed on the substrate 2 are provided. The alignment mark 10A is made of the same material as the optical waveguide 3a, that is, the same crystal.
[0040]
Next, a method for manufacturing the semiconductor laser chip according to the first embodiment will be described.
[0041]
As shown in FIG. 2A, an InGaAsP active layer 3 and an n-type InP cladding layer 4 are sequentially formed on a p-type InP substrate 2 by, for example, crystal growth by MOCVD (metal organic chemical vapor deposition). To do.
[0042]
Next, as shown in FIG. 5B, by photolithography, that is, the insulating film 5 is patterned, and using this as a mask, a ridge C that becomes the optical waveguide 3a and a ridge D that becomes the alignment mark 10A are obtained. For example, it is formed simultaneously by mesa etching with a Br-based etching solution. The width of the ridge C serving as the optical waveguide 3a is, for example, about 0.5 to 2.5 micrometers (μm), and the length is about 100 to 1200 micrometers (μm). The ridge D to be the alignment mark 10A is, for example, a circle having a diameter of about 0.5 to 100 micrometers (μm), but is not necessarily a circle.
[0043]
Next, as shown in FIG. 3A, the pn-pInP block layer 6 is selectively grown by, for example, MOCVD crystal growth using the insulating film 5 as a mask.
[0044]
Next, as shown in FIG. 2B, the insulating film 5 is removed, and the contact layer 7 is formed by crystal growth by, for example, MOCVD.
[0045]
Next, as shown in FIG. 4, an insulating film 8 is newly formed by vapor deposition by sputtering, for example, but the insulating film 8 is removed in stripes so that current can be injected directly above the optical waveguide 3a. Finally, the n-side surface electrode 9 and the p-side back electrode 11 are formed by vapor deposition, for example, by sputtering.
[0046]
As described above, the InP semiconductor laser chip has been described as an example. However, as long as the energy band gap of the crystal serving as the alignment mark 10A is smaller than the energy band gap of the surrounding crystal, other materials such as GaAs can be realized. .
[0047]
In the first embodiment, when the optical waveguide 3a is formed, the InGaAsP active layer 3 is left in a circular shape and used as an alignment mark 10A made of crystal.
[0048]
Next, a passive alignment method using the semiconductor laser chip 1A described above will be described. The semiconductor laser chip 1A shown in FIG. 5A is die-bonded to the submount 20 shown in FIG. 5B while being aligned with infrared rays as shown in FIG.
[0049]
First, the semiconductor laser chip 1A is transferred onto the submount 20 by, for example, a vacuum suction device as rough alignment. The rough alignment is performed by pattern recognition using the metal pattern 24 indicating the mounting position of the semiconductor laser chip 1A on the submount 20 and the infrared transmitted light of the front electrode 9 or the back electrode 11 of the semiconductor laser chip 1A. For example, an infrared CCD (Charge) in which infrared light is irradiated from above the semiconductor laser chip 1A and the transmitted light is installed on the back side of the submount 20
Detected by a Coupled Device camera.
[0050]
At this time, as shown in FIG. 5C, the alignment mark 10A of the semiconductor laser chip 1A that does not transmit infrared rays and the alignment mark 23 on the side of the submount 20 that transmits infrared rays are infrared rays. When seen through, they appear to overlap. This is because an active layer having an energy band gap narrower than the surroundings remains in the alignment mark 10A made of crystal, and this active layer absorbs infrared rays. On the other hand, the crystal around the alignment mark 10A transmits infrared rays.
[0051]
Here, the alignment is performed so that the center of areas of the alignment marks 10A and 23 coincide with each other while transmitting infrared rays. Then, the metal pattern 24 and the back electrode 11 are bonded using the solder material 25. Thereafter, an electrode for driving the semiconductor laser chip 1A, a photodiode for monitoring the output laser light, and the like are mounted on the submount 20 to produce an optical communication module.
[0052]
In the optical communication module thus manufactured, the optical waveguide 3a of the semiconductor laser chip 1A and the optical fiber 22 of the submount 20 are arranged with high accuracy and die-bonded, and high and uniform coupling efficiency is obtained.
[0053]
Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIGS. 6A and 6B are diagrams showing a semiconductor laser chip according to Embodiment 2 of the present invention, in which FIG. 6A is a plan view of the semiconductor laser chip, and FIG. 6B is a cross-sectional view taken along line AA ′ of FIG. Sections of the semiconductor laser chip as seen from the line are respectively shown. FIGS. 7 to 9 are cross-sectional views showing the manufacturing steps of the semiconductor laser chip according to the second embodiment.
[0054]
6A and 6B, a semiconductor laser chip 1B according to the second embodiment of the present invention includes a p-type InP substrate 2, an InGaAsP active layer 3 (optical waveguide 3a), and a pnpInP block. A layer 6, a contact layer 7, an insulating film 8, a surface electrode 9, a pair of alignment marks 10B formed on the active layer 3 formed simultaneously with the optical waveguide 3a, and a back electrode 11 are provided. The alignment mark 10B is an infrared absorption layer having an energy band gap narrower than that of the active layer 3 or a thick layer.
[0055]
Next, a method for manufacturing the semiconductor laser chip according to the second embodiment will be described.
[0056]
As shown in FIG. 7A, on the p-type InP substrate 2, an InGaAsP active layer 3, an n-type InP clad layer 4, and an infrared absorption layer 12 that is to be an alignment mark 10B made of an InGaAsP active layer, For example, the layers are sequentially formed by crystal growth by MOCVD (metal organic chemical vapor deposition).
[0057]
Next, as shown in FIG. 4B, by photolithography, that is, the insulating film 5 is patterned, and using this as a mask, a ridge C that becomes the optical waveguide 3a and a ridge D that becomes the alignment mark 10B are obtained. For example, it is formed simultaneously by mesa etching with a Br-based etching solution. The width of the ridge C serving as the optical waveguide 3a is, for example, about 0.5 to 2.5 micrometers (μm), and the length is about 100 to 1200 micrometers (μm). In addition, the ridge D to be the alignment mark 10B is, for example, a circle having a diameter of about 0.5 to 100 micrometers (μm), but is not necessarily a circle.
[0058]
Next, as shown in FIG. 8A, selective growth of the pn-pInP block layer 6 is performed by, for example, MOCVD crystal growth using the insulating film 5 as a mask.
[0059]
Next, as shown in FIG. 6B, the insulating film 5 is removed, and the infrared absorption layer 12 immediately above the InGaAsP active layer 3 to be the optical waveguide 3a is removed by etching with nitric acid, for example. The reason for removing the infrared absorption layer 12 immediately above the InGaAsP active layer 3 to be the optical waveguide 3a is to eliminate the disadvantage that the laser beam is absorbed.
[0060]
Next, as shown in FIG. 9A, after the insulating film 5 and the infrared absorption layer 12 are removed, the contact layer 7 is formed by, for example, MOCVD crystal growth.
[0061]
Next, as shown in FIG. 4B, a new insulating film 8 is formed by, for example, vapor deposition by sputtering, but the insulating film 8 is removed in stripes so that current can be injected directly above the optical waveguide 3a. Keep it. Finally, the n-side surface electrode 9 and the p-side back electrode 11 are formed by vapor deposition, for example, by sputtering.
[0062]
In the first embodiment, the InGaAsP active layer 3 is used as the alignment mark 10A made of crystal. However, in this second embodiment, as shown in FIG. Since the energy band gap is narrower than that of the layer 3 or the layer is thicker, the infrared absorption layer 12 having a larger amount of infrared absorption than the active layer 3 is inserted into the semiconductor laser chip 1B.
[0063]
With such a structure, the alignment mark 10B with a clearer contrast can be seen by pattern recognition with infrared transmitted light than when only the active layer 3 of the first embodiment is the alignment mark 10A. Improves die bond accuracy. Since the passive alignment method is the same as that of the first embodiment, description thereof is omitted.
[0064]
Embodiment 3 FIG.
A third embodiment of the present invention will be described with reference to FIGS. 10A and 10B are diagrams showing a semiconductor laser chip according to Embodiment 3 of the present invention, in which FIG. 10A is a plan view of the semiconductor laser chip, and FIG. 10B is a cross-sectional view taken along line AA ′ of FIG. Sections of the semiconductor laser chip as seen from the line are respectively shown. FIGS. 11 to 13 are cross-sectional views showing the manufacturing steps of the semiconductor laser chip according to the third embodiment.
[0065]
10A and 10B, a semiconductor laser chip 1C according to the third embodiment of the present invention includes a p-type InP substrate 2, an InGaAsP active layer 3 (optical waveguide 3a), and a pnpInP block. A layer 6, a contact layer 7, an insulating film 8, a surface electrode 9, a pair of alignment marks 10C formed under the active layer 3 formed simultaneously with the optical waveguide 3a, and a back electrode 11 are provided. The alignment mark 10C is an infrared absorption layer having an energy band gap narrower than that of the active layer 3 or a thick layer.
[0066]
Next, a method for manufacturing the semiconductor laser chip according to the third embodiment will be described.
[0067]
As shown in FIG. 11A, on the p-type InP substrate 2, an infrared absorption layer 12 made of an InGaAsP active layer and serving as an alignment mark 10C, an n-type InP cladding layer 4, an InGaAsP active layer 3, Another n-type InP cladding layer 4 is sequentially formed by, for example, MOCVD (metal organic chemical vapor deposition) crystal growth.
[0068]
Next, as shown in FIG. 4B, by photolithography, that is, the insulating film 5 is patterned, and using this as a mask, a ridge C that becomes the optical waveguide 3a and a ridge D that becomes the alignment mark 10C are obtained. For example, it is formed simultaneously by mesa etching with a Br-based etching solution. The width of the ridge C serving as the optical waveguide 3a is, for example, about 0.5 to 2.5 micrometers (μm), and the length is about 100 to 1200 micrometers (μm). Further, the ridge D to be the alignment mark 10C is, for example, a circle having a diameter of about 0.5 to 100 micrometers (μm), but is not necessarily a circle.
[0069]
Next, as shown in FIG. 12A, selective growth of the pn-pInP block layer 6 is performed by, for example, MOCVD crystal growth using the insulating film 5 as a mask.
[0070]
Next, as shown in FIG. 2B, the insulating film 5 is removed, and the contact layer 7 is formed by crystal growth by, for example, MOCVD.
[0071]
Next, as shown in FIG. 13, an insulating film 8 is newly formed by, for example, vapor deposition by sputtering. The insulating film 8 is removed in stripes so that current can be injected directly above the optical waveguide 3a. Finally, the n-side surface electrode 9 and the p-side back electrode 11 are formed by vapor deposition, for example, by sputtering.
[0072]
In the second embodiment, since the energy band gap is narrower or thicker than that of the active layer 3 directly above the InGaAsP active layer 3, the infrared absorption layer has a larger amount of infrared absorption than the active layer 3. 12 is inserted into the semiconductor laser chip 1B. In the third embodiment, the infrared absorption layer 12 is provided directly under the InGaAsP active layer 3.
[0073]
With such a structure, the alignment mark 10C with a clearer contrast can be seen by pattern recognition with infrared transmitted light than when only the active layer 3 of the first embodiment is the alignment mark 10A. Improves die bond accuracy. Since the passive alignment method is the same as that of the first embodiment, description thereof is omitted.
[0074]
Embodiment 4 FIG.
A fourth embodiment of the present invention will be described with reference to FIGS. 14A and 14B are diagrams showing a semiconductor laser chip according to Embodiment 4 of the present invention, in which FIG. 14A is a plan view of the semiconductor laser chip, and FIG. 14B is a cross-sectional view taken along line AA ′ of FIG. Sections of the semiconductor laser chip as seen from the line are respectively shown. FIGS. 15 to 17 are cross-sectional views showing each manufacturing process of the semiconductor laser chip according to the fourth embodiment.
[0075]
14A and 14B, a semiconductor laser chip 1D according to the fourth embodiment of the present invention includes a p-type InP substrate 2, an InGaAsP active layer 3 (optical waveguide 3a), and a pnpInP block. A layer 6, a contact layer 7, an insulating film 8, a surface electrode 9, a pair of alignment marks 10 </ b> D formed simultaneously with the optical waveguide 3 a, and a back electrode 11 are provided. The alignment mark 10D has an energy band gap equivalently smaller than that of the active layer 3 and a thick layer.
[0076]
Next, a method for manufacturing the semiconductor laser chip according to the fourth embodiment will be described.
[0077]
As shown in FIG. 15 (a), an insulating film 13 is patterned on the p-type InP substrate 2 by sputtering deposition, and the selective growth groove 14 is formed, for example, with a sulfuric acid-based etching solution using this as a selective growth mask for the active layer. It is formed by etching.
[0078]
Next, as shown in FIG. 2B, the InGaAsP active layer 3 and the InP cladding layer 4 are selectively grown in the selective growth groove 14 by, for example, MOCVD crystal growth, and the active layer 3 grows thickly. The infrared absorption layer 15 is to be the alignment mark 10D.
[0079]
Next, as shown in FIG. 16 (a), by photolithography, that is, the insulating film 5 is patterned, and using this as a mask, a ridge C that becomes the optical waveguide 3a and a ridge D that becomes the alignment mark 10D, For example, it is formed simultaneously by mesa etching with a Br-based etching solution. The width of the ridge C serving as the optical waveguide 3a is, for example, about 0.5 to 2.5 micrometers (μm), and the length is about 100 to 1200 micrometers (μm). Further, the ridge D to be the alignment mark 10C is, for example, a circle having a diameter of about 0.5 to 100 micrometers (μm), but is not necessarily a circle.
[0080]
Next, as shown in FIG. 6B, selective growth of the pn-pInP block layer 6 is performed by, for example, MOCVD crystal growth using the insulating film 5 as a mask.
[0081]
Next, as shown in FIG. 17A, the insulating film 5 is removed and the contact layer 7 is formed by, for example, MOCVD crystal growth.
[0082]
Next, as shown in FIG. 4B, a new insulating film 8 is formed by, for example, vapor deposition by sputtering, but the insulating film 8 is removed in stripes so that current can be injected directly above the optical waveguide 3a. Keep it. Finally, the n-side surface electrode 9 and the p-side back electrode 11 are formed by vapor deposition, for example, by sputtering.
[0083]
In the second or third embodiment, since the energy band gap is narrower or thicker than the active layer 3 directly above or directly below the InGaAsP active layer 3, the amount of absorbed infrared rays is higher than that of the active layer 3. Although many infrared absorption layers 12 are provided, in this fourth embodiment, the alignment mark 10D is equivalently smaller in energy band gap and thicker than InGaAsP active layer 3 using selective growth, that is, the infrared absorption amount is larger. Many layers are provided.
[0084]
With such a structure, the alignment mark 10D with a clearer contrast can be seen by pattern recognition with infrared transmitted light than when only the active layer 3 of the first embodiment is the alignment mark 10A. Improves die bond accuracy. Since the passive alignment method is the same as that of the first embodiment, description thereof is omitted.
[0085]
Embodiment 5 FIG.
A fifth embodiment of the present invention will be described with reference to FIGS. 18A and 18B are views showing a semiconductor laser chip according to Embodiment 5 of the present invention, in which FIG. 18A is a plan view of the semiconductor laser chip, and FIG. 18B is a cross-sectional view taken along line AA ′ of FIG. Sections of the semiconductor laser chip as seen from the line are respectively shown. FIGS. 19 to 21 are cross-sectional views showing the manufacturing steps of the semiconductor laser chip according to the fifth embodiment.
[0086]
18A and 18B, a semiconductor laser chip 1E according to the fifth embodiment of the present invention includes a p-type InP substrate 2, an InGaAsP active layer 3 (optical waveguide 3a), and a pnpInP block. A layer 6, a contact layer 7, an insulating film 8, a front surface electrode 9, a pair of alignment marks 10 A formed simultaneously with the optical waveguide 3 a, a back surface electrode 11, and an electrical separation groove 16 are provided.
[0087]
Next, a method for manufacturing the semiconductor laser chip according to the fifth embodiment will be described.
[0088]
As shown in FIG. 19A, an InGaAsP active layer 3 and an n-type InP cladding layer 4 are sequentially formed on a p-type InP substrate 2 by crystal growth of, for example, MOCVD (metal organic chemical vapor deposition). Form.
[0089]
Next, as shown in FIG. 5B, by photolithography, that is, the insulating film 5 is patterned, and using this as a mask, a ridge C that becomes the optical waveguide 3a and a ridge D that becomes the alignment mark 10A are obtained. For example, it is formed simultaneously by mesa etching with a Br-based etching solution. The width of the ridge C serving as the optical waveguide 3a is, for example, about 0.5 to 2.5 micrometers (μm), and the length is about 100 to 1200 micrometers (μm). The ridge D to be the alignment mark 10A is, for example, a circle having a diameter of about 0.5 to 100 micrometers (μm), but is not necessarily a circle.
[0090]
Next, as shown in FIG. 20A, selective growth of the pn-pInP block layer 6 is performed by, for example, MOCVD crystal growth using the insulating film 5 as a mask.
[0091]
Next, as shown in FIG. 2B, the insulating film 5 is removed, and the contact layer 7 is formed by crystal growth by, for example, MOCVD.
[0092]
Next, as shown in FIG. 21A, an electrical isolation groove 16 is formed by etching with a Br-based etching solution using a photoresist as a mask.
[0093]
Next, as shown in FIG. 2B, a new insulating film 8 is formed by, for example, vapor deposition by sputtering, but the insulating film 8 is striped so that current can be injected directly above the optical waveguide 3a. Keep it. Finally, the n-side surface electrode 9 and the p-side back electrode 11 are formed by vapor deposition, for example, by sputtering.
[0094]
If such an electrical separation groove 16 is provided, there is no risk of leakage current flowing to the alignment mark 10A, and deterioration of the characteristics of the semiconductor laser chip 1E can be prevented. In addition, it is applicable also to the said Embodiment 2-4. Further, since the passive alignment method is the same as that of the first embodiment, description thereof is omitted.
[0095]
Embodiment 6 FIG.
A sixth embodiment of the present invention will be described with reference to FIGS. 22A and 22B are diagrams showing a semiconductor laser chip according to the sixth embodiment of the present invention, in which FIG. 22A is a plan view of the semiconductor laser chip, and FIG. 22B is a cross-sectional view along line AA ′ in FIG. Sections of the semiconductor laser chip as seen from the line are respectively shown. 23 and 24 are views showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the sixth embodiment.
[0096]
22A and 22B, a semiconductor laser chip 1F according to the sixth embodiment of the present invention includes an n-type InP substrate 2A, an InGaAsP active layer 3 (optical waveguide 3a), and a p-InP first cladding. A layer 30, a p-InP second cladding layer 32, a current confinement insulating film 33, a P-side electrode (surface electrode) 35, a pair of alignment marks 10D formed simultaneously with the optical waveguide 3a, and a back electrode 11 With. The alignment mark 10D has an energy band gap equivalently smaller than that of the active layer 3 and a thick layer. The clad layers 30 and 32 have lower conductivity than the contact layer.
[0097]
In the fourth embodiment, as shown in FIG. 15A, the final width of the opening width of the insulating film 13 as a selective growth mask in the portion where the active layer 3 is formed is as shown in FIG. Therefore, it is necessary to reduce the width of the active layer to a width that functions as a single transverse mode optical waveguide by the etching process shown in FIG.
[0098]
In the sixth embodiment, as shown in FIG. 23A, the opening width of the insulating film 31 as a selective growth mask is set to be approximately the same as the final active layer width in advance, and selective growth is used. Only by forming the active layer 3, the width of the active layer automatically becomes as wide as a single transverse mode optical waveguide, and the etching step shown in FIG. 16A is not necessary. In this case, since the insulating film 5 for the block layer growth as shown in FIG. 16A of the fourth embodiment is not formed, the current block layer cannot be grown. Therefore, the process after the selective growth of the active layer 3 is as follows.
[0099]
First, as shown in FIG. 23A, the active layer 3 and the p-InP first cladding layer 30 are selectively grown on the n-InP substrate 2A, and the insulating film 31 used for the selective growth is made of hydrofluoric acid or the like. Remove.
[0100]
Next, as shown in FIG. 23B, after the insulating film 31 used for the selective growth is removed with hydrofluoric acid or the like, a p-InP second cladding layer 32 is grown on the entire surface.
[0101]
Next, as shown in FIG. 24A, an insulating film 33 for current confinement is formed on the entire surface, and a current passage window 34 is formed only on the optical waveguide by photolithography and etching with hydrofluoric acid or the like.
[0102]
Finally, as shown in FIG. 24B, a P-side electrode 35 is formed on the current confinement insulating film 33 by vapor deposition.
[0103]
With such a configuration, even if there is no current blocking layer, current can be efficiently injected into the active layer 3 of the optical waveguide by the current confinement insulating film 33 to oscillate. In the case of this structure, the current leaks through the current leak path 36 shown in FIG. 24B and becomes an ineffective component for light emission. However, the substrate is an n-InP substrate, and the upper cladding layer is By configuring the p-InP first clad layer 32 and the p-InP second clad layer 33, it is preferable to reduce the leak current by configuring the current leak path 36 to be p-type InP having a high electric resistance.
[0104]
In the sixth embodiment, an example is shown in which a P-side contact layer is formed. In this case, an AuZn-based P-side electrode 35 may be used to facilitate obtaining an ohmic contact with the electrode. .
[0105]
Further, in the fourth embodiment, as shown in FIG. 15A, the selective growth groove 14 is first formed. However, since it is not always necessary, it is not formed in the sixth embodiment. .
[0106]
Further, the etching process for forming the infrared absorption layer so as to function as an alignment mark also serves as the optical waveguide etching process in FIG. 16A of the fourth embodiment, but this etching is omitted. Therefore, if the opening of the alignment mark portion is made substantially the final alignment mark shape at the stage of patterning of the insulating film 31 which is a selective growth mask, the formation of the alignment mark can be performed as shown in FIG. 3 can be completed at the same time as the optical waveguide 3 at the stage of selective growth.
[0107]
If the embodiment as described above is adopted, as described above, the step of forming the optical waveguide and the alignment mark by the etching shown in FIG. it can.
[0108]
Embodiment 7 FIG.
In each of the first to sixth embodiments, InGaAsP is used as the crystal of the alignment marks 10A to 10D. In the seventh embodiment, InGaAs is used as the crystal of the alignment mark, and InP is used as the surrounding crystal.
[0109]
Embodiment 8 FIG.
In each of the first to sixth embodiments, InGaAsP is used as the alignment marks 10A to 10D. In the eighth embodiment, InGaAs is used as the alignment mark, and GaAs or AlGaAs is used as the surrounding crystal.
[0110]
Embodiment 9 FIG.
In each of the above embodiments, a pair of circular alignment marks is shown, but the shape may be a polygon, an ellipse, a cross, or the like, and the number of alignment marks may be one or any number of three or more.
[0111]
Embodiment 10 FIG.
When the wafer according to the present invention is cleaved by a conventional cleaving method, that is, as shown in FIG. 25, when the wafer is cleaved in a bar shape at the center line 17 of the surface electrodes 9 (P-side electrode 35) in two horizontal rows, The positions of the alignment marks with respect to the cleaved portion 3a are not uniform. Therefore, in the tenth embodiment, as shown in FIG. 25, the semiconductor laser chip is formed from the wafer at the center line 18 of the alignment marks 10A in two horizontal rows while viewing the alignment marks 10A (10B to 10D) with an infrared CCD camera. Is cleaved or diced into a bar shape. The cleavage method according to the tenth embodiment can cut out a semiconductor laser chip in which the position E of the alignment mark 10A (10B to 10D) with respect to the light emitting point is aligned.
[0112]
【The invention's effect】
According to this invention Semiconductor laser chip As described above, the substrate, the optical waveguide formed on the substrate, and the optical waveguide At the same time, a pair of circular shapes that are formed on the substrate and formed at positions symmetrical to the optical waveguide and do not transmit infrared rays With alignment mark A conductive layer formed on the substrate so as to cover the alignment mark, an insulating film formed on the conductive layer except directly above the optical waveguide, and formed on the insulating film and the conductive layer. A front electrode formed on the back surface of the substrate, As a result, the positional accuracy of the optical waveguide and the alignment mark can be improved.
[0114]
Further, according to the present invention Semiconductor laser chip As described above, since the conductive layer is composed of the block layer formed on the substrate, the optical waveguide and the contact layer formed on the block layer, the positional accuracy of the optical waveguide and the alignment mark The effect that can be improved.
[0115]
Further, according to the present invention Semiconductor laser chip As described above, the conductive layer is composed of the first cladding layer formed on the optical waveguide and the alignment mark and the second cladding layer formed on the substrate. There is an effect that the position accuracy of the mark can be improved.
[0116]
Further, according to the present invention Semiconductor laser chip As described above, since the optical waveguide and the alignment mark are active layers formed simultaneously, the positional accuracy of the optical waveguide and the alignment mark can be improved.
[0117]
Further, according to the present invention Semiconductor laser chip As described above, the first active layer formed simultaneously with the optical waveguide, and the first active layer is formed on the first active layer, the energy band gap is narrower than the first active layer, Alternatively, since the second active layer is provided with a second active layer thicker than the first active layer, and the alignment mark is the second active layer, the recognition of the alignment mark can be improved.
[0118]
Further, according to the present invention Semiconductor laser chip As described above, the first active layer formed simultaneously with the optical waveguide, and formed below the first active layer, the energy band gap is narrower than the first active layer, Alternatively, since the second active layer is provided with a second active layer thicker than the first active layer, and the alignment mark is the second active layer, the recognition of the alignment mark can be improved.
[0119]
Further, according to the present invention Semiconductor laser chip As described above, the optical waveguide and the alignment mark are active layers formed at the same time, and the thickness of the active layer serving as the alignment mark is thicker than that of the active layer serving as the optical waveguide. There is an effect that the recognition can be improved.
[0120]
Further, according to the present invention Semiconductor laser chip As described above, the optical waveguide and the alignment mark are active layers formed at the same time, and an electrical separation groove is provided between the active layers, so that it is possible to prevent deterioration of device characteristics. .
[0121]
Further, according to the present invention Semiconductor laser chip As described above, since the alignment mark is made of a material having an energy band gap narrower than the surrounding material, the positional accuracy of the optical waveguide and the alignment mark can be improved.
[0122]
Further, according to the present invention Semiconductor laser chip As described above, since the alignment mark is made of InGaAsP or InGaAs and the periphery of the alignment mark is made of InP, the positional accuracy of the optical waveguide and the alignment mark can be improved.
[0123]
Further, according to the present invention Semiconductor laser chip As described above, since the alignment mark is made of InGaAs and the periphery of the alignment mark is made of GaAs or AlGaAs, the positional accuracy between the optical waveguide and the alignment mark can be improved.
[0124]
Further, according to the present invention Semiconductor laser chip As described above, the manufacturing method of the method includes the step of forming an optical waveguide on a substrate, the optical waveguide, At the same time on the substrate Forming alignment marks; and After forming the optical waveguide and the alignment mark, forming a conductive layer on the substrate so as to cover the alignment mark, and forming an insulating film on the conductive layer except directly above the optical waveguide A step of forming a surface electrode on the insulating film and the conductive layer; a step of forming a back electrode on the back surface of the substrate; As a result, the positional accuracy of the optical waveguide and the alignment mark can be improved.
[0126]
Further, according to the present invention Semiconductor laser chip As described above, in the manufacturing method, the step of forming the conductive layer includes the step of forming a block layer on the substrate after forming the optical waveguide, and the contact layer on the optical waveguide and the block layer. The step of forming the optical waveguide includes an effect that the positional accuracy of the optical waveguide and the alignment mark can be improved.
[0127]
Further, according to the present invention Semiconductor laser chip As described above, in the manufacturing method, the step of forming the conductive layer includes the step of forming the first cladding layer on the optical waveguide and the alignment mark, and the step of forming the second cladding layer on the substrate. Therefore, the positional accuracy of the optical waveguide and the alignment mark can be improved.
[0128]
Further, according to the present invention Semiconductor laser chip As described above, since the optical waveguide and the alignment mark are active layers and both are formed at the same time as described above, the positional accuracy of the optical waveguide and the alignment mark can be improved.
[0129]
Further, according to the present invention Semiconductor laser chip As described above, the manufacturing method further includes the step of forming the first active layer on the substrate simultaneously with the optical waveguide, and the energy band gap on the first active layer is the first active layer. Forming a second active layer serving as the alignment mark, which is narrower than the active layer or thicker than the first active layer, and has the effect of improving the recognition of the alignment mark. .
[0130]
Further, according to the present invention Semiconductor laser chip As described above, the manufacturing method of the method further includes the step of forming a first active layer on the substrate simultaneously with the optical waveguide, and an energy band gap below the first active layer. Forming a second active layer serving as the alignment mark, which is narrower than the active layer or thicker than the first active layer, and has the effect of improving the recognition of the alignment mark. .
[0131]
Further, according to the present invention Semiconductor laser chip As described above, the optical waveguide and the alignment mark are active layers, and the active layer serving as the alignment mark is thicker than the active layer serving as the optical waveguide. As a result, it is possible to improve the recognition of the alignment mark.
[0132]
Further, according to the present invention Semiconductor laser chip As described above, since the optical waveguide and the alignment mark are active layers, and both are formed at the same time, and further includes a step of forming an electrical separation groove between the both, There is an effect that deterioration of characteristics can be prevented.
[0133]
Further, according to the present invention Semiconductor laser chip As described above, since the manufacturing method further includes the step of cleaving the wafer with reference to the alignment mark, the chip cleavage accuracy can be improved.
[Brief description of the drawings]
FIGS. 1A and 1B are views showing a plane and a cross section of a semiconductor laser chip according to a first embodiment of the invention. FIGS.
FIG. 2 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the first embodiment of the present invention.
3 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the first embodiment of the present invention. FIG.
FIG. 4 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the first embodiment of the present invention.
FIG. 5 is a diagram showing a passive alignment method using the semiconductor laser chip according to the first embodiment of the present invention.
FIG. 6 is a view showing a plane and a cross section of a semiconductor laser chip according to a second embodiment of the present invention.
FIG. 7 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the second embodiment of the present invention.
FIG. 8 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the second embodiment of the present invention.
FIG. 9 is a cross-sectional view showing each manufacturing process of the semiconductor laser chip according to the second embodiment of the present invention.
10 is a view showing a plane and a cross section of a semiconductor laser chip according to a third embodiment of the present invention. FIG.
FIG. 11 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the third embodiment of the present invention.
FIG. 12 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the third embodiment of the present invention.
FIG. 13 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the third embodiment of the present invention.
FIGS. 14A and 14B are views showing a plane and a cross section of a semiconductor laser chip according to a fourth embodiment of the invention. FIGS.
FIG. 15 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the fourth embodiment of the present invention.
FIG. 16 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the fourth embodiment of the present invention.
FIG. 17 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the fourth embodiment of the present invention.
FIG. 18 is a view showing a plane and a cross section of a semiconductor laser chip according to a fifth embodiment of the present invention.
FIG. 19 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the fifth embodiment of the present invention.
FIG. 20 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the fifth embodiment of the present invention.
FIG. 21 is a diagram showing cross sections of the respective manufacturing processes of the semiconductor laser chip according to the fifth embodiment of the present invention.
FIG. 22 is a view showing a plane and a cross section of a semiconductor laser chip according to a sixth embodiment of the present invention.
FIG. 23 is a diagram showing cross sections of the manufacturing steps of the semiconductor laser chip according to the sixth embodiment of the present invention.
FIG. 24 is a diagram showing cross sections of the manufacturing steps of the semiconductor laser chip according to the sixth embodiment of the present invention.
FIG. 25 is a diagram showing a method for cleaving a semiconductor laser chip according to a tenth embodiment of the present invention.
FIG. 26 is a view showing a plane and a cross section of a conventional semiconductor laser chip.
FIG. 27 is a diagram showing a passive alignment method using a conventional semiconductor laser chip.
[Explanation of symbols]
1A, 1B, 1C, 1D, 1E, 1F Semiconductor laser chip, 2 p-type InP substrate, 2A n-type InP substrate, 3 InGaAsP active layer, 3a optical waveguide, 6p-n-pInP block layer, 7 contact layer, 8 insulation Film, 9 Front electrode, 10A, 10B, 10C, 10D Alignment mark, 11 Back electrode, 30 First clad layer, 32 Second clad layer, 33 Insulating film for current confinement.

Claims (20)

A substrate,
An optical waveguide formed on the substrate;
A pair of circular alignment marks that are formed on the substrate at the same time as the optical waveguide and that do not transmit infrared rays that are formed at symmetrical positions with respect to the optical waveguide ;
A conductive layer formed on the substrate so as to cover the alignment mark;
An insulating film formed on the conductive layer except directly above the optical waveguide;
A surface electrode formed on the insulating film and the conductive layer;
A semiconductor laser chip comprising a back electrode formed on the back surface of the substrate . The conductive layer is
A block layer formed on the substrate;
A contact layer formed on the optical waveguide and the block layer;
The semiconductor laser chip according to claim 1, wherein it is. The conductive layer is
2. The semiconductor laser chip according to claim 1 , wherein the semiconductor laser chip includes a first clad layer formed on the optical waveguide and the alignment mark, and a second clad layer formed on the substrate . 2. The semiconductor laser chip according to claim 1, wherein the optical waveguide and the alignment mark are active layers formed simultaneously . A first active layer formed simultaneously with the optical waveguide; and formed on the first active layer and having an energy band gap narrower than the first active layer or having a layer thickness of the first active layer. A second active layer thicker than the active layer of
With
The semiconductor laser chip according to claim 2, wherein the alignment mark is the second active layer . A first active layer formed at the same time as the optical waveguide; and an energy band gap that is formed below the first active layer and is narrower than the first active layer or has a layer thickness of the first active layer. A second active layer thicker than the active layer of
The semiconductor laser chip according to claim 2, wherein the alignment mark is the second active layer. 4. The semiconductor laser chip according to claim 2, wherein the optical waveguide and the alignment mark are active layers formed at the same time, and an active layer serving as the alignment mark is thicker than an active layer serving as the optical waveguide . 3. The semiconductor laser chip according to claim 2, wherein the optical waveguide and the alignment mark are active layers formed at the same time, and an electrical separation groove is provided therebetween . 9. The semiconductor laser chip according to claim 1, wherein the alignment mark is made of a material having an energy band gap narrower than a surrounding material . The semiconductor laser chip according to claim 9 , wherein the alignment mark is made of InGaAsP or InGaAs, and the periphery of the alignment mark is made of InP . The alignment mark is made of I nGaAs, around the alignment mark, the semiconductor laser chip according to claim 9, wherein formed of GaAs or AlGaAs. Forming an optical waveguide on a substrate;
Forming an alignment mark on the substrate simultaneously with the optical waveguide;
Forming a conductive layer on the substrate so as to cover the alignment mark after forming the optical waveguide and the alignment mark;
Forming an insulating film on the conductive layer except directly above the optical waveguide; and
Forming a surface electrode on the insulating film and the conductive layer;
Forming a back electrode on the back surface of the substrate;
Of manufacturing a semiconductor laser chip . The step of forming the conductive layer includes
Forming a block layer on the substrate after forming the optical waveguide; and
13. A method of manufacturing a semiconductor laser chip according to claim 12 , further comprising a step of forming a contact layer on the optical waveguide and the block layer . The step of forming the conductive layer includes
Forming a first cladding layer on the optical waveguide and the alignment mark;
The method of manufacturing a semiconductor laser chip according to claim 12 , further comprising: forming a second cladding layer on the substrate . 13. The method of manufacturing a semiconductor laser chip according to claim 12, wherein the optical waveguide and the alignment mark are active layers, and both are formed simultaneously . And forming a first active layer on the substrate simultaneously with the optical waveguide;
On the first active layer, a second active layer serving as the alignment mark having an energy band gap narrower than that of the first active layer or a layer thickness larger than that of the first active layer is formed. 14. A method of manufacturing a semiconductor laser chip according to claim 13 , comprising the step of : And forming a first active layer on the substrate simultaneously with the optical waveguide;
Under the first active layer, a second active layer serving as the alignment mark having an energy band gap narrower than the first active layer or a layer thickness thicker than the first active layer is formed. And the process
A method for manufacturing a semiconductor laser chip according to claim 13 . 15. The semiconductor according to claim 13, wherein the optical waveguide and the alignment mark are active layers, and the active layer serving as the alignment mark is thicker than the active layer serving as the optical waveguide, and both are formed simultaneously. Laser chip manufacturing method. 14. The method of manufacturing a semiconductor laser chip according to claim 13, wherein the optical waveguide and the alignment mark are active layers, both are formed at the same time, and further includes a step of forming an electrical separation groove between the two . Furthermore, the manufacturing method of the semiconductor laser chip in any one of Claim 12-19 including the process of cleaving a wafer on the basis of the said alignment mark .

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