JP3645456B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a circuit configuration that facilitates a failure detection test of a logic circuit using a logic block called a megacell.
[0002]
[Prior art]
Due to recent advances in semiconductor integrated circuit manufacturing technology, particularly advances in miniaturization technology, it has become possible to construct a large-scale and complex system on a single LSI chip.
[0003]
As the circuit becomes larger and more complicated, the number of pins of the LSI chip is also increasing. However, the number of pins that can be installed in one LSI is limited by the external size of the LSI chip. Therefore, at present, a gate circuit is provided for each pin and a plurality of functions are assigned to the pin. As a result, the number of gates per pin tends to increase.
[0004]
Against this background, the preparation work required for testing LSIs, such as the creation and addition of test circuits and the creation of test programs for testing semiconductor integrated circuits, is enormous, and the cost and labor required to do so Reduction has become a major issue.
[0005]
Such a problem is no exception in the case of ASIC.
[0006]
In ASIC development, a user realizes a desired circuit function by combining logic blocks for realizing various functions called megacell and IP.
[0007]
Recently, a system ASIC for constructing a system desired by a user on a one-chip LSI by combining a logic circuit designed by the user with these megacells has been provided.
[0008]
In the case of such a system ASIC, the test method tends to become complicated due to the complexity of the configuration. Therefore, improvement of the failure detection rate at the time of testing has been a major issue.
[0009]
FIG. 5 is a circuit block diagram of a general megacell, and particularly shows the configuration of the output section of the megacell that is designed synchronously.
[0010]
As shown in the figure, the megacell 1 incorporates a megacell output unit 2 for deriving the signal of the megacell 1 to the outside.
[0011]
The megacell output unit 2 is supplied with data D1 to D4 to be output from the megacell 1 and input to the data input terminals D of the flip-flops 81, 82, 83 and 84.
[0012]
A clock signal CP is applied to the clock terminals CLK of the flip-flops 81, 82, 83, and 84, and the data D1 to D4 are data synchronized with the clock signal CP, and the data of the flip-flops 81, 82, 83, and 84 are displayed. Output from the output terminal Q.
[0013]
Output signals of the flip-flops 81, 82, 83, and 84 are output as output signals OUT1 to OUT4 through the output terminals 31, 42, 43, and 44 through the output buffer 31, the gated output buffer 32, the output buffer 33, and the gated output buffer 34, respectively. Is output.
[0014]
Note that gate signals G2 and G4 are given to the gated output buffers 32 and 34, and whether or not signals can be output is controlled.
[0015]
The reset terminals R of the flip-flops 81, 82, 83, and 84 can be cleared when a reset signal RESET is given as necessary.
[0016]
In the megacell shown in FIG. 5, in the megacell output unit 2, the data D1 to D4 to be output from the megacell 1 are synchronized by the clock signal CP in the flip-flops 81, 82, 83, 84, and output buffer 31 The output signals OUT1 to OUT4 are output through the gated output buffer 32, the output buffer 33, and the gated output buffer 34. As described above, whether or not the output signals OUT2 and OUT4 are output is controlled by the gate signals G2 and G4, respectively.
[0017]
Now, consider a system ASIC in which, in the megacell 1 having the above-described configuration, the output signals OUT1 to OUT4 are supplied to an external circuit configured by random logic. In this case, it is desirable that the output signal of the megacell 1 can be arbitrarily controlled from the outside.
[0018]
As described above, the method of operating the megacell itself with an external control signal and controlling the signal output from the megacell can realize a system with a high failure detection rate, but it is not a test of the megacell itself. Regardless, there is a problem that a megacell must be operated by inputting a signal to the megacell from outside the LSI chip. In other words, a test program for operating the megacell is required separately from the test program for the logic circuit outside the megacell. Therefore, in the case of a megacell having a larger scale and a complicated function, there is a problem that a test program for controlling the megacell becomes long and complicated. In particular, in the case of a megacell such as a CPU, it is very difficult to create a test program that arbitrarily controls the output of the megacell.
[0019]
A method that can be considered to solve the above problems is a method in which only the logic circuit outside the megacell is operated and tested by the scanning method. FIG. 7 shows a semiconductor integrated circuit device of Conventional Example 1 for realizing the above-described technique.
[0020]
In FIG. 6, output signals OUT <b> 1 to OUT <b> 4 output from the output terminals 41, 42, 43, 44 of the megacell 1 are output to the logic gate unit 18 of the random logic unit 17 that is an external circuit of the megacell 1. Among the output signals OUT1 to OUT4 from the megacell 1, the output signals OUT1 and OUT2 are given to the decoder circuit 19 of the logic gate unit 18, and the output signals OUT3 and 4 are given to the multiplex circuit 20 of the logic gate unit 18. ing.
[0021]
Data OD1 and OD2 are output from the logic gate unit 18 as outputs of the decoder circuit 19, and are supplied to the data input terminals D of the flip-flops 186 and 187, respectively. On the other hand, as the output of the multiplex circuit 20, data OD3 and OD4 are output and supplied to the data input terminals D of the flip-flops 188 and 189, respectively.
[0022]
The clock signal CP is given to the clock terminals CLK of the flip-flops 186, 187, 188, 189, and the data OD1 to OD4 are data synchronized with the clock signal CP, and the data of the flip-flops 186, 187, 188, 189 are obtained. Output from the output terminal Q as output signals O1 to O4.
[0023]
A reset signal RI is given to the reset terminals R of the flip-flops 186, 187, 188, and 189 so that the state can be cleared.
[0024]
The flip-flops 186, 187, 188, and 189 are provided with a scan input data terminal SI and a scan output data terminal SO, controlled by a clock supplied to the scan clock terminals SC1 and SC2, and scanned input data. It has a function of outputting a signal given to the terminal SI or D terminal to the scan output data terminal SO. A scan clock SC1I is supplied to the scan clock terminal SC1 of each flip-flop, and a scan clock SC2I is supplied to the scan clock terminal SC2.
[0025]
The scan input data SDI is input to the scan input data terminal SI of the flip-flop 186.
[0026]
The scan output data terminal SO of the flip-flop 186 is connected to the scan input data terminal SI of the flip-flop 187. That is, the scan input data SDI input to the scan input data terminal SI of the flip-flop 186 is controlled by the scan clocks SC1I and SC2I and output to the scan output data terminal SO, and the scan input data of the flip-flop 187 at the next stage. Transferred to terminal SI.
[0027]
Similarly, the scan output data terminal SO of the flip-flop 187 is transferred to the scan input data terminal SI of the flip-flop 188 via an intermediate stage flip-flop (not shown). Similarly, the scan output data terminal SO of the flip-flop 188 is sequentially connected to the scan input data terminal SI of the flip-flop 189, and the scan data is controlled by the scan clock terminals SC1I and SC2I. 186, 187, intermediate stage flip-flops, and flip-flops 188, 189 are sequentially scanned.
[0028]
The scan data output from the scan output data terminal SO of the flip-flop 189 is output as scan output data SDO.
[0029]
Through the above configuration, until the scan input data SDI is output as the output data SDO through the flip-flops 186 and 187, the intermediate stage flip-flops and the flip-flops 188 and 189 that are controlled by the scan clocks SC1I and SC2I. The scan path is formed.
[0030]
However, in the case of the circuit configuration as shown in FIG. 6, the logic gate unit 18, which exists between the megacell 1 and the flip-flops 186, 187... 188 and 189 included in the external random logic unit 17. The failure, that is, the failure of the decoder circuit 19 and the multiplex circuit 20 cannot be covered, and a decrease in the failure detection rate of this portion becomes a problem.
[0031]
In order to solve such a problem, it is necessary to arbitrarily activate a signal inside the logic gate unit 18. For this purpose, a signal given from the megacell 1 to the logic gate unit 18 of the random logic unit 17 may be arbitrarily controlled.
[0032]
To this end, the semiconductor integrated circuit device of Conventional Example 2 shown in FIG. 7 has been considered. The configuration of FIG. 7 is different from the configuration of FIG. 6 in that a test circuit 21 is inserted between the megacell 1 and the random logic unit 17 and sent from the megacell 1 to the logic gate unit 18 of the random logic unit 17. The signal can be arbitrarily controlled from the outside.
[0033]
According to the configuration shown in FIG. 7, an arbitrary test signal that can be controlled from the outside can be given to the logic gate unit 18, which is effective only from the viewpoint of detecting a failure in the logic gate unit 18.
[0034]
However, there are problems that the number of gates is increased and the delay characteristics of signals output from the megacell are deteriorated. In addition, the test circuit 21 itself needs to be individually designed every time an LSI chip is designed according to the configuration of the logic gate unit 18 which is an external logic circuit. Further, in the test circuit 21 constituted by a multiplexer, a necessary signal line is newly connected to an external terminal of the LSI chip in order to control an internal signal exchanged between the megacell 1 and the logic gate unit 18. Therefore, there is also a problem that it is very difficult to accommodate this in a limited number of pins.
[0035]
Therefore, the present invention eliminates the problems of the prior art as described above, and in a relatively simple circuit configuration, the system ASIC configuration using megacells and external logic circuits facilitates improved fault detection and test pattern generation. Another object of the present invention is to provide a semiconductor integrated circuit device that is effective in reducing work related to test circuit design.
[0036]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a semiconductor integrated circuit device according to claim 1, wherein each output signal of the megacell has a logic configuration selected from a library prepared in advance. And a plurality of flip-flops that output the megacell output signal to the outside of the megacell in synchronization with the clock signal, and the state of each flip-flop is based on the scan clock or the clock signal. A scan path for sequentially transmitting serially from the flip-flop to another flip-flop is formed, and an arbitrary signal is input from the outside to the first flip-flop of the scan path and the last flip-flop of the scan path In addition to outputting the status of There is provided a semiconductor integrated circuit device comprising the input and output terminals for supplying a clock signal to be supplied to each flip-flop from the outside.
[0037]
In order to achieve the above object, the present invention further provides a semiconductor integrated circuit device according to claim 6, wherein the signal output unit of at least one megacell having a logic configuration selected from a library prepared in advance is used. A mega-cell side scan path for transferring the states of a plurality of flip-flops arranged corresponding to each output signal of the mega cell sequentially from one flip-flop to another flip-flop, and the mega cell are arranged separately. A logic block side scan path for sequentially transferring the states of a plurality of flip-flops arranged inside the logic block from one flip-flop to another flip-flop in series in at least one logic block; Two megacell-side scan paths and the first stage of the integrated scan path Arbitrary signals are externally input to the flip-flop, and the state of the flip-flop at the final stage of the integrated scan path is output to the outside, and each of the integrated scan paths is configured to scan the integrated scan path. There is provided a semiconductor integrated circuit device including an input / output terminal group for supplying a scan clock to be supplied to a flip-flop from the outside.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0039]
Embodiment 1
FIG. 1 is a circuit block diagram of the semiconductor integrated circuit device according to the first embodiment of the present invention. In particular, the megacell itself is provided with a function capable of arbitrarily changing its output, and in addition to the test function of the megacell itself, external This is an example of a configuration in which an arbitrary test signal can be output to the circuit.
[0040]
The configuration of FIG. 1 differs greatly from the general configuration shown in FIG. 5 in that scan flip-flops 181, 182, 183, and 184 are used instead of the flip-flops 81, 82, 83, and 84. is there.
[0041]
As shown in the figure, a megacell output unit 2 is incorporated in the megacell 1. The megacell output unit 2 is supplied with data D1 to D4 to be output from the megacell 1 and input to the data input terminals D of the flip-flops 181, 182, 183, and 184.
[0042]
The clock signal CLK is given to the clock terminals CLK of the flip-flops 181, 182, 183, and 184, and the data D1 to D4 are data synchronized with the clock signal CP, and the data of the flip-flops 181, 182, 183, and 184 are displayed. Output from the output terminal Q.
[0043]
The output signals of the flip-flops 181, 182, 183, and 184 are output as output signals OUT 1 to 4 from the output terminals 41, 42, 43, and 44 through the output buffer 31, the gated output buffer 32, the output buffer 33, and the gated output buffer 34, respectively. Is output.
[0044]
A gate signal is given to the gated output buffers 32 and 34, and the output of the signal is controlled. These gate signals are generated based on the logical conditions of the test control signal TEST given to the test gates 112 and 114 and the gate signals G2 and G4 controlled by the SCAN FIF, respectively.
[0045]
A reset signal RESET is given to the reset terminal R of the flip-flops 181, 182, 183, and 184 so that the state can be cleared.
[0046]
The flip-flops 181, 182, 183, and 184 are provided with a scan input data terminal SI and a scan output data terminal SO, controlled by a clock supplied to the scan clock terminals SC 1 and SC 2, and scanned input data. It has a function of outputting a signal given to the terminal SI to the scan output data terminal SO. A scan clock CPS1 input through the input terminal 142 is supplied to the scan clock terminal SC1 of each flip-flop, and a scan clock CPS2 input through the input terminal 143 is supplied to the scan clock terminal SC2. Yes.
[0047]
An input terminal 141 is connected to the scan input data terminal SI of the flip-flop 181. Scan input data SID is sent to the input terminal 141, and the scan input data SID is input to the scan input data terminal SI of the flip-flop 181.
[0048]
The scan output data terminal SO of the flip-flop 181 is connected to the scan input data terminal SI of the flip-flop 182. That is, the scan input data SID input to the scan input data terminal SI of the flip-flop 181 is controlled by the scan clocks CPS1 and CPS2, output to the scan output data terminal SO, and the scan input of the flip-flop 182 of the next stage. Transferred to the data terminal SI.
[0049]
Similarly, the scan output data terminal SO of the flip-flop 182 is transferred to the scan input data terminal SI of the flip-flop 183 via an intermediate stage flip-flop (not shown). Further, the scan output data terminal SO of the flip-flop 183 is sequentially connected to the scan input data terminal SI of the flip-flop 184, and the scan data is controlled by the scan clocks CPS1 and CPS2, and the flip-flop 181. , 182 and intermediate flip-flops and flip-flops 183 and 184 are sequentially scanned.
[0050]
The scan data output from the scan output data terminal SO of the flip-flop 184 is output as scan output data SOD through the output terminal 45.
[0051]
Through the configuration described above, a scan path is formed until the scan input data SID given to the input terminal 141 is output from the output terminal 45 as the output data SOD.
[0052]
In the semiconductor integrated circuit device as shown in FIG. 1, the scan input data SID to the first-stage flip-flop 181 formed in the megacell output unit 2, and the scan clock to be given to each flip-flop 181, 182, 183, 184 Scan output data SOD from CPS1, CPS2, and final stage flip-flop 184 is connected to the outside by input terminals 141, 142, 143 and output terminal 45 which are external terminals of megacell 1, respectively. Scan output data SOD that can be arbitrarily controlled in response to the input of the scan input data SID and the scan clocks CPS1 and CPS2 can be output to the outside of the megacell 1.
[0053]
OUT1-4 can be arbitrarily controlled using a megacell scan path.
[0054]
That is, when the semiconductor integrated circuit device is configured as in the first embodiment and the output signals OUT1 to OUT4 of the megacell 1 are given to the external circuit of the megacell 1, the megacell can be tested at the time of executing the test of the external circuit connected to the megacell 1. A signal given from 1 to an external logic circuit to be tested can be arbitrarily activated. As a result, the failure detection rate of the logic gate section existing from the output signal of the flip-flops 181, 182, 183, 184 of the megacell output section 2 constituting the megacell 1 to the input of the scan flip-flop of the external logic circuit is improved. It becomes possible to make it.
[0055]
Further, at this time, if ATPG (automatic test program extraction) is used, it is possible to easily realize a test program having a high failure detection rate in creating a test program for an external logic circuit to be tested.
[0056]
Further, by connecting the scan path of the megacell 1 to the scan path outside the megacell 1, a terminal (pin) provided outside the chip for testing when executing an external circuit test connected to the scan path of the megacell 1 It is possible to save.
[0057]
Embodiment 2
FIG. 2 is a circuit block diagram of a semiconductor integrated circuit device according to the second embodiment of the present invention.
As shown in the figure, the data D1 to D4 are given to the megacell 1 and input to the data input terminals D of the flip-flops 181, 182, 183, and 184, respectively.
[0058]
The clock signal CLK is given to the clock terminals CLK of the flip-flops 181, 182, 183, 184, and the data D1 to D4 are data synchronized with the clock signal CP, and the data of the flip-flops 181, 182, 183, 184 are received. Output from the output terminal Q.
[0059]
The output signals of the flip-flops 181, 182, 183, and 184 are output as output signals OUT 1 to 4 from the output terminals 41, 42, 43, and 44 through the output buffer 31, the gated output buffer 32, the output buffer 33, and the gated output buffer 34, respectively. Is output.
[0060]
The gated output buffers 32 and 34 are supplied with gate signals G2 and G4 connected to the Q of the scan FIF.
[0061]
A reset signal RESET is given to the reset terminal R of the flip-flops 181, 182, 183, and 184 so that the state can be cleared.
[0062]
The flip-flops 181, 182, 183, and 184 are provided with a scan input data terminal SI and a scan output data terminal SO, controlled by a clock supplied to the scan clock terminals SC 1 and SC 2, and scanned input data. It has a function of outputting a signal given to the terminal SI to the scan output data terminal SO. A scan clock CPS1 input through the input terminal 143 is supplied to the scan clock terminal SC1 of each flip-flop, and a scan input from the scan clock signal line 162 through the input terminal 142 to the scan clock terminal SC2. A clock CPS2 is provided.
[0063]
An input terminal 141 is connected to the scan input data terminal SI of the flip-flop 181. Scan input data SID is sent from the scan input data line 13 to the input terminal 141, and this scan input data SID becomes an input to the scan input data terminal SI of the flip-flop 181.
[0064]
The scan output data terminal SO of the flip-flop 181 is connected to the scan input data terminal SI of the flip-flop 182. That is, the scan input data SID input to the scan input data terminal SI of the flip-flop 181 is output to the scan output data terminal SO in synchronization with the scan clocks CPS1 and CPS2, and the scan of the flip-flop 182 of the next stage is performed. Transferred to the input data terminal SI.
[0065]
Similarly, the scan output data terminal SO of the flip-flop 182 is transferred to the scan input data terminal SI of the flip-flop 183 via a flip-flop (not shown). Similarly, the scan output data terminal SO of the flip-flop 183 is sequentially connected to the scan input data terminal SI of the flip-flop 184, and the scan data is flip-flops in synchronization with the scan clocks CPS1 and CPS2. 181, 182... 183 and 184 are sequentially scanned.
[0066]
The scan data output from the scan output data terminal SO of the flip-flop 184 is output as scan output data SOD through the output terminal 45.
[0067]
Through the configuration described above, a scan path is formed until the scan input data SID given to the input terminal 141 is output from the output terminal 45 as the output data SOD.
[0068]
On the other hand, output signals OUT1 to OUT4 from the output terminals 41, 42, 43, and 44 of the megacell 1 are supplied to the logic gate unit 18 of the random logic unit 17 that is an external circuit of the megacell 1. Among the output signals OUT1 to OUT4 from the megacell 1, the output signals OUT1 and OUT2 are supplied to the decoder circuit 19 of the logic gate unit 18, and the output signals OUT3 and 4 are supplied to the multiplex circuit 20 of the logic gate unit 18. .
[0069]
Data OD 1, OD 2, and OD 3 are output from the logic gate unit 18 and applied to the data input terminals D of the flip-flops 186, 187, and 189, respectively.
[0070]
A clock signal CPO is supplied from the logic gate unit 18 to the clock terminals CLK of the flip-flops 186, 187, and 189. The data OD1, OD2, and OD4 are synchronized with the clock signal CPO, and the flip-flops 186, 187, 189, The output signals O1, O2, and O4 are output from the data output terminal Q of 189.
[0071]
The reset signal R is supplied from the logic gate unit 18 to the reset terminals R of the flip-flops 186, 187, and 189 so that the state can be cleared.
[0072]
The flip-flops 186, 187, and 189 are provided with a scan input data terminal SI and a scan output data terminal SO. The flip-flops 186, 187, and 189 are controlled by a clock supplied to the scan clock terminals SC1 and SC2, and are scanned. 1 is output to the scan output data terminal SO. Scan clocks CPS1 and CPS2 are supplied to the scan clock terminals SC1 and SC2 of the flip-flops, respectively.
[0073]
The scan output data SOD output from the scan output data terminal SO of the flip-flop 184 of the megacell 1 is applied to the scan input data terminal SI of the flip-flop 189.
[0074]
The scan output data terminal SO of the flip-flop 189 is connected to the scan input data terminal SI of the flip-flop 187 via a flip-flop (not shown). That is, the scan input data SID input to the scan input data terminal SI of the flip-flop 189 is output to the scan output data terminal SO in synchronization with the scan clocks CPS1 and CPS2, and passes through the intermediate stage flip-flop. Further, the data is transferred to the scan input data terminal SI of the flip-flop 187 in the next stage.
[0075]
Similarly, the scan output data terminal SO of the flip-flop 187 is transferred to the scan input data terminal SI of the flip-flop 186.
[0076]
As described above, the scan output data terminal SO and the scan input data terminal SI of the flip-flop having the same configuration are sequentially connected, and the scan data is synchronized with the scan clock terminals CPS1 and CPS2 in the flip-flop. 189... 187 and 186 are sequentially scanned.
[0077]
The scan data output from the scan output data terminal SO of the flip-flop 186 is output as scan output data SODO.
[0078]
Through the above configuration, a scan path is formed until the scan input data SID is output as the output data SOD through the flip-flops 181 to 184 and 189 to 186 that operate in synchronization with the scan clocks CPS1 and CPS2. The
[0079]
As is clear from FIG. 2, the serial configuration for scanning is applied to the flip-flops 181, 182, 183, and 184 at the output of the megacell 1 regardless of the test method of the megacell 1 itself. A scan path is formed internally.
[0080]
The scan input data SID given to the scan input data terminal SI of the first flip-flop 181 of the scan path is given from the outside of the chip through the input terminal 141 defined as the external terminal of the megacell 1.
[0081]
On the other hand, the scan output data SOD generated through the scan path inside the megacell 1 and sent from the scan output data terminal SO of the flip-flop 184 through the output terminal 45 is not only derived outside but also as an external circuit of the megacell 1. ... 189 for scanning provided in the random logic section 17 to be defined is given to the scan input data terminal SI of the flip-flop 189. Since it is not necessary for the scan campuses to be connected, the effect does not change even if the signal from the terminal 45 is output to the outside.
[0082]
The scan clocks CPS1 and CPS2 provided to the scan flip-flops 181, 182, 183 and 184 inside the megacell 1 through the input terminals 143 and 142 are also defined as external signals of the megacell 1 and are supplied from the outside of the megacell 1. Is done.
[0083]
That is, the output signal of the megacell 1 is output from the output clock 31, the gated output buffer 32, or the output buffer 31 provided on the output side of the flip-flops 181, 182, 183, 184 depending on the scan clocks CPS 1, CPS 2 and the scan input data SID. Tri-state control of the output buffer 33 and the gated output buffer 34 allows arbitrary control without operating the megacell 1 itself and without adding an extra test circuit outside the megacell 1. It becomes.
[0084]
In addition, since the flip-flops 186, 187,... 189 of the random logic unit 17 also form a scan path, this can also be controlled so that an arbitrary signal can be output.
[0085]
Through the configuration as described above, in the test of the megacell 1 and the random logic unit 17, it is arranged on the megacell 1 side of the random logic unit 17 in addition to the conventional failure detection target such as the megacell 1 and the random logic unit 17. The failure detection rate of the logic gate unit 18 can be greatly improved.
[0086]
Embodiment 3
FIG. 3 is a circuit block diagram of a semiconductor integrated circuit device according to the third embodiment of the present invention.
As shown in the figure, a megacell output unit 2 is incorporated in the megacell 1. The megacell output unit 2 is supplied with data D1 to D4 to be output from the megacell 1 and input to the data input terminals D of the flip-flops 181, 182, 183, and 184.
[0087]
The clock signal CLK is given to the clock terminals CLK of the flip-flops 181, 182, 183, 184, and the data D1 to D4 are data synchronized with the clock signal CP, and the data of the flip-flops 181, 182, 183, 184 are received. Output from the output terminal Q.
[0088]
The output signals of the flip-flops 181, 182, 183, and 184 are output as output signals OUT 1 to 4 from the output terminals 41, 42, 43, and 44 through the output buffer 31, the gated output buffer 32, the output buffer 33, and the gated output buffer 34, respectively. Is output.
[0089]
A gate signal is given to the gated output buffers 32 and 34, and the output of the signal is controlled. These gate signals are generated based on the logical conditions of the test control signal TEST supplied to the test gates 112 and 114 and the gate signals G2 and G4 controlled by the SCAN path, respectively.
[0090]
A reset signal RESET is given to the reset terminal R of the flip-flops 181, 182, 183, and 184 so that the state can be cleared.
[0091]
The flip-flops 181, 182, 183, and 184 are provided with a scan input data terminal SI and a scan output data terminal SO, controlled by a clock supplied to the scan clock terminals SC 1 and SC 2, and scanned input data. It has a function of outputting a signal given to the terminal SI to the scan output data terminal SO. Scan clocks CPS1 and CPS2 input through input terminals 143 and 142, respectively, are applied to scan clock terminals SC1 and SC2 of each flip-flop.
[0092]
An input terminal 141 is connected to the scan input data terminal SI of the flip-flop 181. Scan input data SID is sent to the input terminal 141, and the scan input data SID is input to the scan input data terminal SI of the flip-flop 181.
[0093]
The scan output data terminal SO of the flip-flop 181 is connected to the scan input data terminal SI of the flip-flop 182. That is, the scan input data SID input to the scan input data terminal SI of the flip-flop 181 is output to the scan output data terminal SO in synchronization with the scan clocks CPS1 and CPS2, and the scan of the flip-flop 182 of the next stage is performed. Transferred to the input data terminal SI.
[0094]
Similarly, the scan output data terminal SO of the flip-flop 182 is connected to the scan input data terminal SI of the flip-flop 183 via a not-shown intermediate stage flip-flop, and the scan output data terminal SO of the flip-flop 183 is flip-flop. The scan data is sequentially connected to the scan input data terminal SI of 184, and the scan data is synchronized with the scan clocks CPS1 and CPS2, and the flip-flops 181 and 182, the flip-flops in the middle stage, and the flip-flops 183 and 184, respectively. Are sequentially scanned.
[0095]
The scan data output from the scan output data terminal SO of the flip-flop 184 is output as scan output data SOD through the output terminal 45.
[0096]
Through the configuration described above, a scan path is formed until the scan input data SID given to the input terminal 141 is output from the output terminal 45 as the output data SOD.
[0097]
On the other hand, the output signals OUT1 to OUT4 from the output terminals 41, 42, 43, and 44 of the megacell 1 are logic gates through the input terminals 22, 23, 24, and 25 of other megacells 171 that are positioned as external circuits of the megacell 1. Connected to the unit 18. Among the output signals OUT1 to OUT4 from the megacell 1, the output signals OUT1 and OUT2 are supplied to the decoder circuit 19 of the logic gate unit 18, and the output signals OUT3 and 4 are supplied to the multiplex circuit 20 of the logic gate unit 18. .
[0098]
Data OD1 and OD2 are output from the logic gate unit 18 as outputs of the decoder circuit 19, and are supplied to the data input terminals D of the flip-flops 186 and 187, respectively. On the other hand, as the output of the multiplex circuit 20, data OD3 and OD4 are output and supplied to the data input terminals D of the flip-flops 188 and 189, respectively.
[0099]
The clock signal CLK is supplied to the clock terminals CLK of the flip-flops 186, 187, 188, and 189, and the data OD1 to OD4 are data synchronized with the clock signal CPO, and the data of the flip-flops 186, 187, 188, and 189 are displayed. Output from the output terminal Q as output signals O1 to O4.
[0100]
The reset signal R is given to the reset terminals R of the flip-flops 186, 187, 188 and 189 so that the state can be cleared.
[0101]
The flip-flops 186, 187, 188, and 189 are provided with a scan input data terminal SI and a scan output data terminal SO, which are controlled by a clock supplied to the scan clock terminals SC1 and SC2, and scan. It has a function of outputting a signal applied to the input data terminal SI to the scan output data terminal SO. A scan clock CPSO1 is supplied to the scan clock terminal SC1 of each flip-flop, and a scan clock CPSO2 is supplied to the scan clock terminal SC2.
[0102]
The scan input data SIDO is input to the scan input data terminal SI of the flip-flop 186.
[0103]
The scan output data terminal SO of the flip-flop 186 is connected to the scan input data terminal SI of the flip-flop 187. In other words, the scan input data SID input to the scan input data terminal SI of the flip-flop 186 is output to the scan output data terminal SO in synchronization with the scan clocks CPSO1 and CPSO2, and the scan input of the flip-flop 187 of the next stage. Transferred to the data terminal SI.
[0104]
Similarly, the scan output data terminal SO of the flip-flop 187 is connected to the scan input data terminal SI of the flip-flop 188 via the intermediate flip-flop (not shown), and the scan output data terminal SO of the flip-flop 188 is flip-flop. The scan data is sequentially connected to the scan input data terminal SI of 189, and the scan data is synchronized with the scan clock terminals CPSO 1 and CPSO 2, and flip-flops 186 and 187, intermediate stage flip-flops and flip-flops 188 and 189. Are sequentially scanned.
[0105]
The scan data output from the scan output data terminal SO of the flip-flop 189 is output as scan output data SODO.
[0106]
Through the above configuration, the scan input data SIDO is output as output data SODO through the flip-flops 186 and 187, the intermediate stage flip-flops and the flip-flops 188 and 189 that operate in synchronization with the scan clocks CPSO1 and CPSO2. Scan paths up to are formed.
[0107]
Even with the above configuration, the flip-flops 181, 182, 183, and 184 incorporated in the megacell 1 are scan designed, and the flip-flops 186, 187, 188, and 189 incorporated in the megacell 171 are also scan designed. The output of each of the megacells 1 and 171 can be arbitrarily controlled from the outside, and the logic gate disposed on the input side of the megacell 171 is controlled by controlling the output of the megacell 1 when the test of the megacell 171 is executed. By performing the failure detection of the unit 18, the failure detection rate of this portion can be improved.
[0108]
Embodiment 4
FIG. 4 is a circuit block diagram of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. In particular, the internal structure of an LSI chip designed using megacells 1 and 171 is illustrated.
[0109]
As shown in the figure, the LSI is composed of megacells 1, 171, a random logic unit 17, and a memory 62, and each circuit block is connected to each other by a data address bus 64 and through an external interface 61. It is connected to the outside of the LSI chip.
[0110]
The megacell 1 has the same internal structure as that shown in FIG. 1, that is, it includes scan flip-flop blocks 63 and 68 connected in series, and the output thereof can be arbitrarily controlled by a scan signal.
[0111]
On the other hand, the megacell 171 and the random logic unit 17 also have the same internal structure as that shown in the random logic unit 17 of FIG. 2, and by the function of receiving a scan signal from the outside and sending it out through the scan path, It has a structure that allows its own failure test.
[0112]
An output from the megacell 1 is output to the megacell 171 through the bus 66 and output to the random logic unit 17 through the bus 67.
[0113]
On the other hand, scan signals are applied to the scan flip-flop blocks 63 and 68 of the megacell 1 from the outside of the LSI via the external interface 61. On the other hand, the scan outputs of the scan flip-flop blocks 63 and 68 are transferred through the scan path 65 passing through the internal scan path of the random logic unit 17 and the internal scan path of the megacell 171, and are derived from the external interface 61 to the outside of the LSI. .
[0114]
According to the configuration of the fourth embodiment, in the system ASIC in which the megacell 1, the random logic unit 17 and the megacell 171 are mixedly loaded, the test scan path passes through the series through the megacell 1, the random logic unit 17 and the megacell 171. Therefore, each output state can be arbitrarily activated in the LSI failure test. For this reason, there is no need to create a mechanism or program for fault detection individually, and there is no need to assign individual test pins for testing, simplifying the system configuration and improving the fault detection rate. It is possible to plan.
[0115]
As described above, the embodiments of the present invention have been described. In any case, regardless of the test method of the megacell 1 itself, the output section of the megacell 1 in which the arrangement, wiring, delay, and timing adjustment are completed, that is, the megacell output section 2 Is composed of a scan flip-flop and an output buffer, and a scan path is formed in the output section of the megacell 1, so that it is not necessary to add a test circuit outside the megacell 1 when testing the peripheral circuit of the megacell 1. By making the signal output from the megacell 1 arbitrarily controllable, the failure detection rate of the external circuit can be greatly improved.
[0116]
Further, even when an arbitrary signal is given to the external circuit, it is not necessary to operate the megacell 1 itself, so that the program work for that purpose can be simplified.
[0117]
Further, since it is not necessary to arrange a test circuit outside the megacell 1, the number of gates of the LSI itself can be suppressed, and adverse effects of the test circuit on the original functions of the LSI, such as delay effects, can be excluded. In addition, the test circuit is of a nature that needs to be individually designed for each external circuit, but if this is not required, the labor and cost for designing the test circuit can be reduced, and the LSI can be efficiently developed. Is possible.
[0118]
On the other hand, since the scan path of the megacell 1 and the scan path of the peripheral circuit are connected so that the output signal of the megacell can be arbitrarily controlled, a test program with a high failure detection rate can be easily created by automatic test program extraction. It is possible to reduce the labor, time and cost involved in test preparation and test execution, and improve the failure detection rate.
[0119]
【The invention's effect】
As described above, according to the semiconductor integrated circuit device of the present invention, a scan path and a gate are formed in the synchronization flip-flop of the output portion of the megacell whose characteristics are known, and the operation can be arbitrarily controlled from the outside. Therefore, it is possible to give an arbitrary signal for testing to the external circuit arranged around the megacell. Furthermore, by connecting the scan paths arranged inside the external circuit in series, the internal state of the LSI from the outside As a result, it is possible to improve the system ASIC failure detection rate with less preparation and less labor, and to enable effective LSI testing. . Further, the number of external test terminals can be reduced, and there is no need for timing adjustment between the megacell and the external circuit by adding a test circuit.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention.
FIG. 2 is a circuit block diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention.
FIG. 3 is a circuit block diagram of a semiconductor integrated circuit device according to a third embodiment of the present invention.
FIG. 4 is a circuit block diagram of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.
FIG. 5 is a circuit block diagram for explaining a configuration of a general megacell.
6 is a circuit block diagram of a semiconductor integrated circuit device of Conventional Example 1. FIG.
7 is a circuit block diagram of a semiconductor integrated circuit device of Conventional Example 2. FIG.
[Explanation of symbols]
1,171 Megacell
2 Megacell output section
31, 33 Output buffer
32, 34 Gated output buffer
41, 42, 43, 44, 45 Output terminal
81, 82, 83, 84 Flip-flop
112 114 Test gate
141, 142, 143 input terminals
17 Random logic part
18 Logic gate part
181, 182, 183, 184 flip-flop
186, 187, 188, 189 flip-flop
19 Decoter circuit
20 Multiplex circuit
21 Test circuit
22, 23, 24, 25 Input terminals
61 External interface
62 memory
63, 68 Scan flip-flop block
64 Data address bus
65 Campus
66, 67 Data bus

Claims (10)

A megacell signal output unit having a logic configuration selected from a library prepared in advance is arranged corresponding to each output signal of the megacell , and outputs a plurality of megacell output signals in synchronization with the output clock signal. A plurality of flip-flops to send to
Based on a scan clock, a test scan path for sequentially transmitting the state of each flip-flop from one flip-flop to another flip-flop in series is formed,
An arbitrary data pattern is externally input to the first flip-flop of the scan path, and the state of the flip-flop of the final stage of the scan path is output to the outside. A semiconductor integrated circuit device comprising an input / output terminal group for supplying a clock signal to be supplied to a flip-flop from the outside.   2. The semiconductor integrated circuit device according to claim 1, further comprising gate means provided on the signal output side of each flip-flop for controlling the signal output. In a logic block connected to the output signal of the megacell,
A logic block side scan path for sequentially transferring the states of a plurality of flip-flops arranged in the logic block from one flip-flop to another;
A signal is sent from the last stage of the megacell scan path or the last stage of the logic block scan path to the flip flop of the first stage of the logic block scan path or the first stage of the mega cell scan path. A signal path;
A logic block side output terminal for outputting the state of the flip-flop at the final stage of the scan path to the outside;
A semiconductor integrated circuit device according to claim 1. In the logic block connected to the output signal from the megacell,
A logic block side scan path for sequentially transferring the states of a plurality of flip-flops arranged in the logic block from one flip-flop to another;
An arbitrary signal is externally input to the first flip-flop of the logical block side scan path, the state of the final flip-flop of the scan path is output to the outside, and the logical block scan path is scanned to perform the scan operation. A logic block side input / output terminal group for supplying a clock signal to be supplied to each flip-flop from outside
A semiconductor integrated circuit device according to claim 1.   5. The semiconductor integrated circuit device according to claim 3, wherein the logic block is another megacell having a logic configuration selected from a library prepared in advance. In the signal output of at least one megacell having a logic configuration selected from a pre-prepared library,
They are arranged corresponding to each output signal of the mega-cell, a plurality of the state of the flip-flop in synchronization with the output clock signal you sending a plurality of output signals of the megacell to megacell outside, successively, different from one flip-flop The flip-flop is formed with a test megacell scan path for serial transfer,
In at least one logic block arranged separately from the megacell,
A test logic block side scan path for sequentially transferring the states of a plurality of flip-flops arranged inside the logic block from one flip-flop to another flip-flop in series,
An integrated scan path configured by connecting at least one of the megacell side scan path and at least one of the logic block side scan path in series;
An arbitrary signal is input from the outside to the flip-flop at the first stage of the integrated scan path, and the state of the flip-flop at the final stage of the integrated scan path is output to the outside. An input / output terminal group for supplying a clock signal to be supplied to each flip-flop constituting the integrated scan path from the outside;
A semiconductor integrated circuit device comprising:   The semiconductor integrated circuit device according to claim 6, wherein the logic block is another megacell having a logic configuration selected from a library prepared in advance. Regardless of the test method of the megacell itself, in the megacell having a logic block having a plurality of synchronization and scanning flip-flops and a plurality of output buffers in the output unit, and adjusting the placement and routing and delay and timing,
The output of one scan flip-flop inside the logic block is connected to the input of another scan flip-flop inside the same logic block, thereby forming a test scan path inside the megacell. The scan data input at the beginning of the campus, the scan data output at the last stage of the scan path, and the scan clock signal are defined as external terminals of this megacell. By controlling the scan signal, the output signal from this megacell A semiconductor integrated circuit device which can be arbitrarily controlled.   9. The semiconductor integrated circuit device using the mega cell according to claim 8, wherein the output signal of the mega cell is controlled by a scan signal, so that the output of the mega cell can be detected during a test of the scan designed logic circuit group outside the mega cell. A semiconductor integrated circuit device, wherein a signal of a logic gate portion existing up to an input of a scan flip-flop in a logic circuit group to be tested can be controlled.   9. The semiconductor integrated circuit device using a mega cell according to claim 8, wherein a scan path formed inside the mega cell and a scan path formed inside a logic circuit outside the mega cell are connected, and a logic circuit outside the mega cell is connected. By arbitrarily controlling the output signal from the megacell at the time of test execution, the signal of the logic gate that exists between the output of the megacell and the input of the scan flip-flop in the logic circuit to be tested can be arbitrarily A semiconductor integrated circuit device characterized in that it is controllable.

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