JP3640441B2 - Pin electronics circuit for VLSI test system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pin electronics circuit, particularly a driver and a programmable load circuit, which is an I / O (Input / Output) with a device under measurement (hereinafter referred to as “DUT”) in a VLSI test system.
[0002]
[Prior art]
Large scale integrated circuits (hereinafter referred to as “VLSI”) have come to have a pin count of 256 pins, 512 pins to over 1000 pins. The VLSI test system for testing the VLSI has a set of I / Os of a driver, a comparator, and a programmable load circuit corresponding to each pin of the DUT. In other words, the pin electronics circuit of the 512-pin VLSI test system has 512 sets of drivers, comparators, and programmable load circuit I / Os, which are incorporated into one test head.
[0003]
FIG. 5 shows a block diagram of the DUT 10 and a set of I / O 14 of the pin electronics circuit in the VLSI test system. Each pin of the DUT 10 corresponds to a set of I / O 14, a test signal from the driver 15 is input to the input pin of the DUT 10, and a response signal is output to the comparator 16 from the output pin.
[0004]
The comparator 16 is a voltage comparator and compares it with an expected value. However, since the input current is zero, when the output pin of the DUT 10 is a pin for sending a load current, a circuit for taking in the rated load current is required. Therefore, a programmable load circuit (hereinafter referred to as “PL circuit”) 17 which is a kind of variable constant current source incorporates this rated load current.
The PL circuit 17 operates as a pair with the comparator 16, but the comparator 16 operates when the driver 15 does not operate. Therefore, as shown in FIG. This signal is operated by receiving a signal indicating that the driver 15 is not operating.
[0005]
FIG. 6 shows a schematic diagram of a conventional driver 15 and a PL circuit 17. The driver 15 can be operated by a DRE (driver enable) signal, but at the same time, the PL circuit 17 is inactivated in response to a negative signal of the DRE signal. As shown in FIG. 5, the driver 15 is driven by the pattern signal from the pattern generator 12 and sends the current voltage of the test signal to the DUT 10.
[0006]
On the other hand, when the driver 15 is in a disabled state (non-operating state), the PL circuit 17 operates. However, the PL circuit 17 also has a PLE (PL circuit enable) signal and is in an enabled (operating) state or a disabled (non-operating) state. And can choose. This is because the output of the DUT 10 depends on whether a resistance load is required or a constant current load is required. The pull-in current value of the PL circuit 17 is controlled by the I _{4 set} current and the I _{5 set} current.
[0007]
FIG. 7 shows a circuit diagram of FIG. The circuit is driven by a plus potential V _CC , a minus potential V _EE and a ground potential of the ± power supply. The driver 15 includes a DER control unit driven by the first half currents I ₁ and I ₂ and a current / voltage output unit driven by the second half bias current I ₃ . Both the currents I ₁ and I ₂ operate between V _CC and V _EE and are always constant. However, the bias current I ₃ is a DRE (driver It becomes a binary state of a constant value and a zero value depending on the driving state of (enable). That is, the bias current I ₃ is constant during operation, but zero during non-operation.
[0008]
On the other hand, since the PL circuit 17 absorbs the rated output current of the DUT 10, the sink current values I ₄ and I ₅ vary depending on the DUT 10 standard and test conditions. Therefore, the sink current value draws the output current from the DUT 10 with the set current values of I _{4 set} and I _{5 set} , but the draw current value differs depending on the DUT 10 or each output pin.
[0009]
In this way, since the driver 15 and the PL circuit 17 each independently use the power supply current, the total current value changes each time. FIG. 8 shows the situation. DRE enabled, disabled, D _r V _in, it flows a current of I / O 14 of the test head by PLE, the current value of I ₄ and I ₅ is greatly changed, and shifted up or down the total current is larger Yes.
[0010]
[Problems to be solved by the invention]
As described above, the current of the I / O 14 arranged in the test head varies depending on the test conditions. When the number of pins of the DUT 10 is as small as several tens of pins, there was no particular problem. However, the number of pins gradually increased. It has become a fluctuation. Therefore, the temperature change of the test head becomes large depending on the situation, and the circuit operation becomes unstable. There has also been a problem in designing the margin of the power supply capacity for supplying current.
[0011]
When the number of pins of the DUT 10 becomes larger and exceeds 1000 pins, it is necessary to minimize this current fluctuation, always keep it constant, and minimize the power supply capacity.
The present invention minimizes changes in the currents I (V _CC ) and I (V _EE ) of the I / O 14 regardless of whether the driver is driven or not.
[0012]
[Means for Solving the Problems]
In order to solve the above problem, the present invention provides a bias current compensation circuit that draws the same amount of current I _3a when the bias current I ₃ of the driver is disabled (disabled) by the DRE signal, and this current I _3a is supplied to the PL circuit. Is used as a current for operating the.
[0013]
Therefore, the I / O current value of the VLSI test system is constant, the power consumption of the test head is always constant, and the temperature is also constant.
[0014]
The invention of claim 1 is provided with a bias current compensation circuit in which the current of the driver and the current of the PL circuit are made common in addition to the conventional driver, comparator and PL circuit.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail together with examples.
[0016]
【Example】
FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram thereof, FIG. 3 is a current waveform diagram, and FIG. 4 is a circuit diagram of another embodiment. Here, the same reference numerals are given to the portions corresponding to the portions of FIGS. 5, 6, and 7.
First, FIG. 1 will be described. FIG. 1 is a block diagram in which a bias current compensation circuit 20 is provided with respect to the conventional block diagram of FIG. 6 and a current for the PL circuit 17 is drawn from the bias current compensation circuit 20.
[0017]
FIG. 2 is a circuit diagram of FIG. 1 and corresponds to the conventional circuit diagram of FIG. A bias current compensation circuit 20 is configured between the circuit of the driver 15 and the PL circuit 17.
With reference to FIG. In the enabled state, the driver 15 has a bias current I ₃ flowing through the output transistors Q _out1 and Q _out2 . When the driver 15 is disabled, both Q _out1 and Q _out2 are cut off, so that the bias current I ₃ becomes 0 mA.
[0018]
Therefore, in the disabled state, the bias compensation circuit 20 generates I ₃ = I _3a = I _3b to keep the power supply current constant. When this circuit is added, the currents I _1a and I _2a increase. Therefore, I _1a and I _2a are set to sufficiently small values, and I _1a is amplified to I _3a and I _2a is amplified to I _3b by Q ₅ and Q ₆ and Q ₈ and Q ₉ current mirror circuits.
[0019]
Further, by using I _{3 a} and I _3b as currents for operating the PL circuit , the power consumption of the entire circuit can be reduced. That is, not only the compensation of the on / off current of the bias current I ₃ but also the compensated currents I _3a and I _3b are reused.
[0020]
The relationship between the currents I _3a and I ₄ will be described. Since the relationship between I _3b and I ₅ is exactly the same, this is omitted. Most of the constant current I _3a generated by Q ₆ is the current (I ₄ + I _4a ) of the PL circuit 17, and the remaining current {I _3a − (I ₄ + I _4a )} is the emitter current of Q ₇ (I _eQ7 ). Flows into GND.
The on-off of PL circuit 17 is carried out in the transistor Q ₁₀ and Q _11. The switch circuit current (I _4a ) is amplified by the current mirror circuit Q ₁₂ / Q ₁₃ to obtain a programmable load current I ₄ .
[0021]
A current waveform diagram of this circuit is shown in FIG. FIG. 3A is a waveform diagram when PLE is off, and FIG. 3B is a waveform diagram when PLE is on. As shown in c and d, there is almost no current shift.
[0022]
(Other examples)
FIG. 4 shows another embodiment. FIG. 4 is obtained by adding some circuits to further stabilize the circuit operation of FIG. That is, transistors Q ₁₈ and Q ₁₉ are added to prevent the potential of nodes (A) and (B) of the PL circuit 17 from dropping, and the emitter currents of the transistors Q ₇ and Q ₁₀ become 0 mA. In order to prevent this, bias resistors R _XH and R _XL are added. By adding these, the circuit operation of FIG. 2 is further stabilized.
[0023]
【The invention's effect】
As described in detail above, the present invention operates stably in the pin electronics circuit of the I / O 14 with the DUT 10 in the VLSI test system even when the driver 15 is turned on and off with little change in power supply current.
[0024]
Therefore, since the number of pins of the DUT 10 is increasing more and more, more than 1000 pins, this is a circuit that is absolutely necessary for stable operation of the pin electronics circuit, and its technical effect is great.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a circuit diagram of FIG.
FIG. 3 is a current waveform diagram of each part in FIG. 1;
FIG. 4 is a circuit diagram of another embodiment of the present invention.
FIG. 5 is a block diagram of I / O of a VLSI test system in which the present invention is used.
FIG. 6 is a schematic diagram of a conventional driver and a PL circuit.
7 is a circuit diagram of FIG. 6. FIG.
FIG. 8 is a current waveform diagram of FIG.
[Explanation of symbols]
10 DUT (device under test)
12 pattern generator 13 Pattern comparator 14 I / O (Input / Output)
15 Driver 16 Comparator 17 PL Circuit (Programmable Load Circuit)
20 Bias current compensation circuit

Claims (1)

In the I / O (14) with the DUT (10) in the VLSI test system for testing the VLSI,
A current-voltage output unit configured by connecting a plurality of transistors in series between two power sources is provided, and the current-voltage output unit is controlled to be in an operating state and a non-operating state by a DRE signal. A constant bias current flows through the unit, and a test signal of the rated voltage is given from the current voltage output unit to the input pin of the DUT (10) while the constant bias current is flowing. A driver (15) in which the bias current flowing in the section is controlled to zero;
A comparator (16) that compares the output voltage from the output pin of the DUT (10) with an expected value;
A PL circuit capable of setting a value of a programmable load current flowing through the output pin of the DUT (10) in a non-operating state within the range of the constant bias current value;
When controlled by the DRE signal and the driver is controlled to be non-operating, a current having a value equal to the constant bias current flowing in the current voltage output unit of the driver is drawn from the power source, and this current is supplied to the PL circuit. A bias current compensation circuit that supplies the PL circuit as a current for operating
A pin electronics circuit for a VLSI test system.

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