JP3638909B2 - Phase distortion correction amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase distortion correction amplifier suitable for application to, for example, a power amplifier of a radio communication device.
[0002]
[Prior art]
Conventionally, as a frequency of a radio communication device for ships or mobile phone base stations, for example, L band (0.39 GHz to 1.55 GHz), S band (1.55 GHz to 5.2 GHz), etc., GHz band High frequency is assigned. As such a high-frequency power amplifier, a GaAsFET amplifier is generally employed.
[0003]
FIG. 7 shows a basic configuration of a common source GaAsFET amplifier 2 disclosed in Japanese Patent Laid-Open No. 2000-312116 according to the prior art.
[0004]
In the GaAsFET amplifier 2, the source of the GaAsFET 4 is grounded, and the drain is connected to the output terminal via a capacitor, and is connected to the positive power supply Vd through a coil.
[0005]
The gate of the GaAsFET 4 is connected to the bias circuit 6 via a coil. The bias circuit 6 has a voltage follower configuration in which a source follower type FET 10 is connected to the output of the operational amplifier 8. A negative voltage Vf obtained by dividing the voltage of the negative power source −Ve by a resistor is applied to the positive phase input terminal of the operational amplifier 8.
[0006]
When the RF (Radio Frequency) input signal power S1 is supplied from the input terminal to the gate of the GaAsFET 4 via the capacitor and the signal level is increased, the gate of the GaAsFET 4 is increased. The bias current flowing from the source to the source increases. This increase in the bias current is covered by an increase in the current supplied from the source of the FET 10 constituting the voltage follower buffer, so that the source voltage of the FET 10 does not change. Since the source voltage of the FET 10 is the gate voltage Vg of the GaAsFET 4, the gate voltage Vg of the GaAsFET 4 is held constant.
[0007]
This describes that the saturation output signal power of the output signal power S2 of the GaAsFET amplifier 2 can be increased.
[0008]
[Problems to be solved by the invention]
By the way, in recent high-frequency wireless communication using digital technology, a transmission speed can be increased within the same frequency band, and therefore, a multi-phase modulation scheme of four or more phases is frequently used.
[0009]
However, when the input signal power S1 is increased in the above-described conventional GaAsFET amplifier 2, the difference (phase difference) θ2-θ1 between the phase θ2 of the output signal power S2 and the phase θ1 of the input signal power S1 is measured. As shown in the characteristic C1 of FIG. 8, this is linear when the input signal power S1 is small, but the phase difference, that is, the phase distortion increases as the input signal power S1 increases. The inventor confirmed.
[0010]
When the phase difference becomes large, there is a problem that the possibility of malfunctioning increases in phase modulation communication. When importance is attached to the linearity of the phase, the GaAsFET amplifier 2 according to the above-described prior art, There is a problem that it can only be used with low power.
[0011]
The present invention has been made in consideration of such problems, and the difference between the phase of the output signal power and the phase of the input signal power (phase difference) is increased over a wider range as the input signal power increases. It is an object of the present invention to provide a phase distortion correction amplifier that can be realized.
[0012]
[Means for Solving the Problems]
In the phase distortion correction amplifier according to the present invention, in the common source GaAsFET amplifier, the output of a voltage follower configured by an operational amplifier is connected to the gate of the GaAsFET, and the operational amplifier increases the input signal power applied to the gate. Then, an element having such a characteristic that the output voltage of the voltage follower decreases when the gate current increases is selected (invention according to claim 1).
[0013]
As the input signal power increases, the output voltage of the voltage follower dynamically decreases following the increase in the gate current, that is, the gate voltage decreases. By configuring so that the phase distortion caused by the increase in input signal power is offset by the phase change caused by the decrease in the gate voltage, the phase difference between the input and output signals becomes linear, and the phase distortion caused by the increase in input signal power is reduced. Improved.
[0014]
The characteristic of the decrease in the gate voltage with respect to the increase in the gate current can be adjusted by inserting a resistor between the output terminal of the operational amplifier and the negative input terminal of the operational amplifier (claim 2). invention).
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0016]
In the drawings to be referred to below, the same reference numerals are given to the components corresponding to those shown in FIGS. Moreover, in order to avoid complexity, it demonstrates with reference to the said FIG. 7, FIG. 8 as needed.
[0017]
FIG. 1 shows a basic configuration of a GaAsFET amplifier 22 according to an embodiment of the phase distortion correction amplifier of the present invention.
[0018]
In the GaAsFET amplifier 22, the source of the GaAsFET 4 is grounded, and the drain is connected to the output terminal 28 via the high-frequency passage capacitor 24, and is connected to the positive power source Vd through the high-frequency blocking coil 30. .
[0019]
The gate of the GaAsFET 4 is connected to the bias circuit 26 via the high frequency blocking coil 32. The bias circuit 26 is connected to the output of the operational amplifier 34 having a voltage follower configuration.
[0020]
A negative voltage Vf obtained by dividing the negative power source −Ve by the resistors 36 and 38 is supplied to the positive phase input terminal of the operational amplifier 34.
[0021]
Further, the gate of the GaAsFET 4 is connected to the input terminal 42 through a high frequency passing capacitor 40.
[0022]
When the RF (Radio Frequency) input signal power S1 is supplied from the input terminal 42 to the gate of the GaAsFET 4 to the GaAsFET amplifier 22 configured as described above and the signal level is increased, the direction from the gate of the GaAsFET 4 to the source direction. The bias current flowing through the gate current, that is, the gate current Ig increases.
[0023]
FIG. 2 shows the measurement result of the characteristic (current change characteristic) of the gate current Ig with respect to the input signal power S1. The horizontal axis is a linear axis, and the vertical axis is a logarithmic axis.
[0024]
As the input signal power S1 increases, the gate current Ig increases. The inventors of this application have found that the input / output phase characteristics become linear by decreasing the gate voltage Vg in accordance with the increase in the gate current Ig. In other words, it has been found that the distortion characteristic is improved by correcting the gate voltage Vg to dynamically decrease following the increase in the input signal power S1.
[0025]
FIG. 3 shows a change characteristic of the output voltage Vo with respect to a change of the output current Io of the operational amplifier 34. As the output current Io increases, the voltage drop of the output voltage Vo increases.
[0026]
That is, when the output current Io increases, in other words, when the gate current Ig increases, the output voltage of the operational amplifier 34 decreases. In other words, the output voltage of the bias circuit 26 decreases and the coil 32 causes a direct current. , The gate voltage Vg of the GaAsFET 4 connected by being short-circuited decreases.
[0027]
FIG. 4 shows the measurement result characteristic C2 of the difference (phase difference) θ2-θ1 between the phase θ2 of the output signal power S2 and the phase θ1 of the input signal power S1 when the input signal power S1 is increased in the GaAsFET amplifier 22. Is shown. A dotted line characteristic C1 is a phase characteristic according to the prior art shown in FIG.
[0028]
As can be seen from the phase characteristic C2, according to the GaAsFET amplifier 22 of this embodiment, the linearity of the phase difference is maintained in a wider range of the input signal power S1 as compared with the phase characteristic C1 according to the prior art. Has been.
[0029]
FIG. 5 shows a change in gain (decibel conversion of the ratio of the output signal power S2 to the input signal power S1) with respect to the increase in the input signal power S1, that is, the gain characteristic A. It has been confirmed that the gain characteristic A is equivalent to that of the GaAsEFT amplifier 2 according to the prior art shown in FIG.
[0030]
Thus, according to the embodiment described above, in the common source GaAsFET amplifier 22, the output of the voltage follower constituted by the operational amplifier 34 is connected to the gate of the GaAsFET 4. In the operational amplifier 34, an element having a characteristic that the output voltage of the voltage follower, that is, the gate voltage Vg decreases when the input signal power S1 applied to the gate increases and the gate current Ig increases is selected. In other words, the operating point where the output impedance of the voltage follower is high, in this embodiment, the voltage follower is operated in the range shown in FIG. 3, for example, when the output current Io is 10 [μA] to 10 [mA]. ing.
[0031]
In this case, when the input signal power S1 increases and the gate current Ig increases, when the gate voltage Vg decreases, the input / output phase difference (θ2−θ1) becomes a linear direction. The phase distortion accompanying the increase is improved.
[0032]
In order to minimize the phase distortion of the gate voltage Vg with respect to the increase in the gate current Ig, the output terminal of the operational amplifier 34 and the negative input terminal of the operational amplifier 34 are shown in FIG. With the configuration of the GaAsFET amplifier 22A in which the resistors 44 and 46 (either one or both) are inserted between the two, the reduction characteristic of the gate voltage Vg can be adjusted.
[0033]
Further, a low resistor may be inserted in series with the coil 32 and the voltage drop may be combined for use.
[0034]
The change characteristics of the gate current Ig with respect to the input signal power S1 shown in FIG. 2 vary depending on the characteristics of the individual GaAsFETs 4 or the use conditions thereof. Therefore, the change amount of the gate voltage Vg is different for each individual GaAsFET 4 or The configuration of the bias circuit 26 that best suits the use conditions, in other words, the linear region of the characteristic C2 of the input signal power S1 versus the phase difference (θ2-θ1) shown in FIG. , Selection of divided voltage Vf, selection of resistors 44 and 46, etc.).
[0035]
That is, in the present invention, the output of the voltage follower including the operational amplifier 34 is connected to the gate of the GaAsFET 4 in order to cancel out the phase change amount due to the fluctuation of the gate voltage Vg and the phase distortion accompanying the increase in the input signal power S1. The circuit is configured to improve the phase distortion. Therefore, it is important to select an operational amplifier 34 having an optimum gate voltage fluctuation amount (phase change amount) for each GaAsFET 4.
[0036]
In addition, the present invention is not limited to the above-described embodiment, and it is needless to say that various configurations can be adopted without departing from the gist of the present invention.
[0037]
【The invention's effect】
As described above, according to the present invention, the linearity of the phase characteristic of the GaAsFET amplifier can be improved more linearly over a wider range of input signal power.
[0038]
Therefore, the phase distortion correction amplifier of the present invention is particularly suitable for application to a power amplifier of a wireless communication apparatus such as a ship for communication using a phase modulation method or a base station of a mobile phone.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a change characteristic diagram of a gate current with respect to a change in input signal power.
FIG. 3 is an output characteristic diagram of an operational amplifier.
FIG. 4 is a change characteristic diagram of a phase difference with respect to an input signal power change.
FIG. 5 is a gain change characteristic diagram with respect to input signal power change;
FIG. 6 is a circuit diagram showing a configuration of another embodiment of the present invention.
FIG. 7 is a circuit diagram showing a configuration of a conventional technique.
FIG. 8 is a change characteristic diagram of a phase difference with respect to a change in input signal power (prior art).
[Explanation of symbols]
2, 22, 22A ... GaAsFET amplifier 4 ... GaAsFET
6, 26 ... Bias circuit 8, 34 ... Operational amplifier 10 ... FET 24, 40 ... Capacitor 28 ... Output terminal 30, 32 ... Coil 36, 38, 44, 46 ... Resistor 42 ... Input terminal

Claims (2)

In a common source GaAsFET amplifier,
Connect the output of a voltage follower composed of an operational amplifier to the gate of the GaAsFET,
In the operational amplifier, an element having a characteristic that the output voltage of the voltage follower decreases when the input signal power applied to the gate increases and the gate current increases is selected. Correction amplifier. The phase distortion correction amplifier according to claim 1.
A phase distortion correction amplifier, wherein a resistor is inserted between an output terminal of the operational amplifier and a negative input terminal of the operational amplifier to adjust a characteristic that the output voltage decreases.

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