JP3638625B2 - Multiple processing equipment - Google Patents

Description

[0001]
[Industrial application fields]
The present invention particularly relates to a plurality of processing apparatuses each having a memory and a data processing unit and connected to each other via an external communication unit so as to communicate with each other.
[0002]
[Prior art]
Conventionally, there has been a multiple processing apparatus as shown in FIG.
Each processing apparatus 90 according to the conventional example ₀ ~ 90 _n As shown in FIG. _i CPU 93 for performing various data processing _i Respectively.
[0003]
Further, as shown in FIG. _i Is a reception buffer 92 for receiving packets transferred via the external communication means 97. _i And a transmission buffer 91 for holding a packet to be transmitted _i And an external communication processing unit 95 that performs transmission processing and reception processing with other processing devices via the external communication means 97 _i And memory 94 _i Data transfer to the CPU 93 _i DMA99 performed without intervention _i It has.
[0004]
In the multi-processing apparatus according to the conventional example, the external communication processing unit 95 is used for communication between the processing apparatuses. _i However, regarding the transfer of data in a plurality of different types of memory spaces in one processing device, the external communication processing unit 95 _i Regardless of the CPU 93 _i Self or DMA99 _i I was trying to do it.
[0005]
[Problems to be solved by the invention]
Now, in the multiple processing device according to the conventional example, as described above, the external communication processing unit 95 is used for data communication processing with the external processing unit. _i For transferring data in a plurality of different types of memory spaces in its own processing device, the CPU 93 _i Self or DMA99 _i Was processing.
CPU 93 for transferring data in a plurality of different types of memory spaces in its own processing device _i If it is performed by itself, there is a problem that the processing load of the CPU increases and the processing capability of each processing apparatus may be reduced.
[0006]
Further, in order for the DMA to transfer data in a plurality of different types of memory spaces in its own processing device, it is not only necessary to provide this DMA in addition to the external communication processing unit, but also the memory 94. _i In order to transfer the data expressed in the packet format to the corresponding area, it is necessary to extract the address from the packet format or to specify the address, and there is a problem that the processing may be complicated. It was.
[0007]
Therefore, the present invention uses the function of a communication processing device that transfers data between a plurality of different types of memory in each processing device, and transfers data between the processing devices (PE; processor elements) via a network. This is done for the purpose of reducing the burden on the CPU, improving the processing performance of each processing apparatus, and consequently improving the performance of the entire plurality of processing apparatuses.
[0008]
Further, if it takes time for the data transfer in the memory in each processing device (PE) by the communication processing unit, the CPU data waiting state in each processing device occurs. It is an object to prevent the processing performance of each processing apparatus from being deteriorated by configuring the capacity to be higher than the throughput of data transfer between the processing apparatuses.
[0009]
[Means for Solving the Problems]
In order to solve the above technical problem, the first invention has a memory 14 as shown in FIG. _i I = 0 to n and the data processing unit 13 _i A plurality of data processing devices 10 each having ₀ -10 _n Is a plurality of processing devices connected to each other via the external communication means 17 so as to be able to communicate with each other.
[0010]
In addition, each processing apparatus 10 _i Includes a reception buffer 12 for receiving a packet transferred via the external communication means 17. _i Holds the packet to be transmitted, and the internal / external communication processing unit 15 _i In accordance with an instruction from the external communication means 17 or the internal communication means 16 _i The return-capable transmission buffer 11 for switching to one of these and sending it out _i A determination as to whether the destination of the packet to be transmitted is itself or another processing device, and a returnable transmission buffer 11 based on the determination result _i Switching of communication means of the packet transmission destination for the reception buffer 12 _i The memory 14 indicated by the packet received via the packet or the packet addressed to itself _i 14 corresponding storage area _{i, 0} ~ 14 _{i, m} Instruction to write to the internal communication means 16 rather than the external communication means 17. _i By providing a large number of parallel communication paths or reducing the minimum interval of communication processing, the internal communication means 16 _i Internal / external communication processing unit 15 that performs processing so as to increase the amount of data per unit time of communication processing via _i And the memory 14 _i And data processing unit 13 _i Receive buffer 12 _i The returnable transmission buffer 11 _i And the internal / external communication processing unit 15 _i And the internal communication means 16 having a larger number of parallel communication paths than the external communication means 17. _i And.
[0011]
Here, “communication means” is a concept including a communication path, and includes a bus or a network such as a crossbar. Including.
A “packet” is a binary digit string including data and control signals, which is transmitted or exchanged as a whole unit. Data, control signals, and possibly error control information may be included, and these pieces of information are arranged in a fixed format.
[0012]
A packet includes a packet header that is communication information such as a transfer destination, a transmission source, and a data size, and a body that is information to be transmitted to the other party.
The “processing device” refers to a functional unit that decodes and executes an instruction in a computer or the like, and corresponds to a processor element (PE) described in the embodiment.
The processing device is not limited to a parallel processing device, and is also applied to a distributed processing device.
[0013]
The “storage area” is used for a plurality of different types provided in the memory. For example, as shown in the embodiment, a global area used for data transfer or for data processing is used. There is a local area used.
“Data transfer” includes, for example, a communication format in which a token is transmitted and a return token is received for a packet transmitted with a token and transmitted.
[0014]
“The amount of data per unit time of communication processing via the internal communication means is larger than that of the external communication means” means that the processing capacity (throughput) via the internal communication means is higher than the processing capacity via the external communication means. Therefore, compared with the external communication means 17, the internal communication means 16 _i This is realized by providing a larger number of parallel communication paths, or by reducing the minimum interval (seconds) of communication processing via the internal communication means than by the external communication means. “Throughput (processing capacity)” refers to a measure of the amount of work performed by a computer system within a given time.
[0015]
Such hardware changes are possible for the following reasons. The external communication means is designed so that it can be connected to various communication devices by standardizing the communication rules, etc., so as to satisfy the generality. Added. If the form of the external passage is changed, it affects all devices connected to the external communication means. On the other hand, the influence of the change in the format in each processing apparatus connected to the external communication means stops in each processing apparatus and can be easily changed.
[0016]
As shown in FIG. 2, the second invention is an arbitrary processing device among a plurality of processing devices connected to each other through external communication means for storing data and processing various data. When there is a packet transmission instruction (S1), it is determined whether or not the destination of the packet to be transmitted is itself or another processing device (S2), and the external communication means is ready for transmission. Waiting (S3), if the destination of the packet to be transmitted is another processing device, the packet is transmitted for each predetermined amount of data per unit time via the external communication means after becoming ready for transmission (S4) The transmission is repeated until the transmission of one packet is completed (S5). When the destination of the packet to be transmitted is its own processing device, the predetermined amount of data per unit time Also it performs a large amount of data processing Ri, performs the appropriate writes to regions of the memory of its own processor (S6) it is.
Here, the “predetermined amount of data” is the amount of processing data per unit time performed via the external communication means, and the predetermined data amount is the number of parallel communication paths of the communication means and the minimum interval of the external communication means. (Seconds) etc.
[0017]
On the other hand, as shown in FIG. 3, the embodiment of the first invention is the internal / external communication processing unit 25 of the first invention. _i The self-addressing determination unit 20 determines whether the destination of the packet to be transmitted is its own processing device or another processing device. _i When the transmission instruction is given and the transmission becomes possible, the self-addressed determination unit 20 _i On the basis of the determination result by the return possible transmission buffer 16 _i Switching of packet transmission destination communication means for address selection unit 23 _i Address selection and the memory 14 based on the address _i Communication instructing unit 22 for instructing access to _i And have. The internal / external communication processing unit 25 _i The address selection unit 23 selects one of the address of the packet to be transmitted or the address of the received packet based on the instruction. _i And the address selector 23. _i The memory 14 based on the address selected by _i 14 corresponding storage area _{i, 0} ~ 14 _{i, m} Access instruction unit 24 for instructing access to _i The internal communication means 16 rather than the external communication means 17 _i The processing is performed so as to increase the amount of data per unit time of communication processing via the network.
[0018]
[Action]
Subsequently, operations of the first invention and the second invention will be described.
As shown in FIG. 1 or FIG. 2, the internal / external communication processing unit 15 in step S1. _i If there is an instruction to transmit a packet in step S2, the internal / external communication processing unit 15 _i Determines whether the packet to be transmitted is addressed to itself. The determination of whether or not the packet is destined for itself is made, for example, by checking the self-addressed bit indicating whether or not the packet is to be transmitted at a predetermined bit position of the packet to be transmitted. This is done by determining whether or not the number is the same as the machine number indicating its own processing device.
If the packet to be transmitted is not addressed to itself, the process proceeds to step S3 and waits for a state where transmission is possible.
[0019]
In step S4, the internal / external communication processing unit 15 _i Instructs to transmit via the external communication means 17 after being ready for transmission.
Packets are transmitted by the amount of data that can be transferred at one time. After the transmission is performed, the next transmission is performed after waiting for the transmission ready state in step S3, and is performed until the transmission of one packet is completed in step S5. To enter the “sendable state”, for example, there is a case where transmission is performed with a token representing a transmission right, or a method in which a token is added to a packet for transmission and the next transmission is performed after a return token is present. .
[0020]
On the other hand, if it is determined in step S2 that the packet to be transmitted is addressed to itself, the process proceeds to step S6, and the internal / external communication processing unit 15 _i Is the returnable transmission buffer 11 _i In contrast, the internal communication means 16 _i And instructing the transfer of the packet via the address, obtaining an address from the data position indicating the destination of the packet to be transmitted, _i 14 corresponding storage area _{i, 0} ~ 14 _{i, m} Instruct to access to write data to
That is, the processing apparatus 10 ₀ -10 _n The packet is transferred to the inside of the returnable transmission buffer 11. _i As if the transmission data held in the reception buffer 12 _i It is performed by being treated as if it is held in
[0021]
Each processing apparatus 10 ₀ -10 _n Internal communication means 16 _i When transferring a packet via the internal communication means 16 compared to the external communication means 17 _i Has more parallel communication paths. Also, the internal / external communication processing unit 15 _i Is internal communication means 16 rather than external communication means 17. _i Processing is performed so as to increase the amount of data per unit time of communication processing via the Internet. Therefore, the transmission of the packet to the own processing device is configured to have a higher throughput than the transmission of the packet to the external processing device.
The internal / external communication processing unit 15 _i External communication by is not adversely affected by enabling internal communication. Further, since the data transfer time to the inside can be shortened, the data processing unit 13 _i Thus, the waiting time of data until the data is aligned can be shortened, and the performance degradation of each processing apparatus can be prevented, and the degradation of the processing performance of the entire processing apparatus can be prevented.
[0022]
As described above, in the present invention, the internal communication means 16 _i And the internal / external communication processing unit 15 _i Are provided in the same manner as the data transfer via the external communication means 17. ₀ -10 _n Data can be transferred to the inside. Thereby, each processing apparatus 10 ₀ -10 _n When transferring data internally, each processing device 10 ₀ -10 _n Internal / external communication processing unit 15 provided inside _i Process, each data processing unit 13 _i Do not put a burden on. Also, each processing device 10 such as DMA ₀ -10 _n In order to transfer data internally, a device that performs external communication can be shared, and it is not necessary to provide a dedicated device, so the configuration is simplified.
[0023]
【Example】
Next, examples of the present invention will be described.
FIG. 4 is an overall block diagram of a plurality of processing devices in which a plurality of distributed memory processing devices (processor elements, PE) according to the present embodiment are connected to each other via an external communication unit 37. Show.
Here, the “distributed memory type processing device” is different from a device in which memories are distributed in each processing device and a common memory is provided separately from each processing device. .
[0024]
Each processing device 30 _o ~ 30 _n As shown in the figure, the memory 34 is composed of a main storage device or the like. _o ~ 34 _n The CPU 33 corresponds to a data processing unit that performs various data processing and controls execution of instructions or control of the communication processing unit. ₀ ~ 33 _n And a communication unit 38 that manages packet communication. ₀ ~ 38 _n And are provided. Furthermore, each processing apparatus 30 ₀ ~ 30 _n Each of the memories 34 _o ~ 34 _n , CPU33 ₀ ~ 33 _n , And communication unit 38 ₀ ~ 38 _n The internal communication means 36 having a larger number of parallel communication paths than the external communication means 37. ₀ ~ 36 _n Connected by.
In this embodiment, the width of the external communication means 37 is 4 bytes, and the internal communication means 36 ₀ ~ 36 _n Is 8 bytes.
Examples of the external communication unit 37 include a bus and a network.
[0025]
FIG. 5 shows a processing apparatus 30 according to the first embodiment. _i The block diagram of is shown.
As shown in FIG. _i Corresponds to the data processor and the CPU 33 _i Inside the cache 33a _i Is provided.
In addition, each processing device 30 _i As shown in the figure, the reception buffer 32 for receiving the data transferred via the external communication means 37 is used. _i And the packet to be transmitted, and the internal / external communication processing unit 35 _i In accordance with an instruction from the external communication means 37 or the internal communication means 36 _i The return-capable transmission buffer 31 for switching to either one of these and sending it out _i And are provided.
[0026]
Internal communication means 36 _i Is an internal bus, and as described above, the throughput is improved by providing a larger number of parallel communication paths than the external communication means 37. Reference numeral 361 _i Is a returnable transmission buffer 31. _i To memory 34 _i The communication processing unit 35 using this route. _i The global area 34 _{i, 1} And 34 _{i, 2} Transfer packets to and from. As a result, the CPU 33 _i Can be reduced, and the performance of each processing apparatus can be improved.
[0027]
Reference 39 _i Is the processing device 30 _i And the external communication means 37. Generally speaking, this tends to result in poor throughput due to hardware constraints. Therefore, path 39 _i And internal communication means 36 _i Are configured with the same throughput. _i The data transfer speed to is slow. Therefore, the internal communication means 36 _i Is route 39 _i The CPU 33 is waiting for data necessary for processing by adopting a configuration with better throughput. _i The idle time can be reduced and the performance of the processing apparatus can be improved.
[0028]
In FIG. 5, the internal / external communication processing unit 35 _i Indicates that the destination of the packet to be transmitted is itself or other external processing device 30 ₀ ~ 30 _n And the return possible transmission buffer 31 based on the determination result. _i Switching of the communication means of the packet transmission destination with respect to the memory 34 and the memory 34 indicated by the packet received via the external communication means 37 or the packet addressed to itself _i Applicable global area 34 _{i, 1} Or local area 34 _{i, 2} Instruction to write to the internal communication means 36 rather than the external communication means 37 _i The internal / external communication processing unit 35 performs processing so as to increase the amount of data per unit time of communication processing via _i And have.
[0029]
Furthermore, each processing apparatus 30 according to the present embodiment. _i Of the memory 34 _i In the portion corresponding to the main storage device, a global area 34, which is a storage area of two different types in which a packet is stored and the movement of the packet can mutually be performed, is stored. _{i, 1} And local area 34 _{i, 2} Is provided.
Here, the global area 34 _{i, 1} Is an area used for data transfer within each process, and the local area 34 _{i, 2} Is an area used for processing in each processing apparatus.
Further, the CPU 33 _i As shown in FIG. _i And the memory 34 _i Local area 34 _{i, 2} Process in
[0030]
Although not shown, the memory 34 _i In addition, a disk or the like may be provided outside the main storage device.
Reference numeral 31a _i Is memory 34 _i Packet and the internal / external communication processing unit 35 _i Is a selection unit that selects packets from _i Is a returnable transmission buffer 31. _i Send packet or receive buffer 32 from _i This is a selection unit for selecting the received packet from. Reference numeral 31c _i , 31b _i And 32b _i Represents a register.
Here, the internal / external communication processing unit 35 _i The returnable transmission buffer 31 _i And receive buffer 32 _i And register 31a _i , 31c _i 32b _i And the selector 31a _i , 32a _i Is the communication unit 38 in FIG. _i It corresponds to.
[0031]
FIG. 6 shows the internal / external communication processing unit 35. _i The function of is shown in detail.
As shown in the figure, the internal / external communication processing unit 35 according to the present embodiment. _i The self-addressing determination unit 40 determines whether the destination of the packet to be transmitted is its own processing device or another processing device. _i When the transmission instruction is given and the transmission becomes possible, the self-addressed determination unit 40 _i The returnable transmission buffer 31 is based on an instruction from the determination result by _i Instruction for switching the communication means of the packet transmission destination to be transmitted to either the external communication means or the internal communication means, and the address selection unit 43 _i Address selection for the memory 34 and the memory 34 based on the address. _i Communication instruction unit 32 for instructing access to _i And have.
[0032]
Further, the internal / external communication processing unit 35 _i In response to the instruction, the address selector 43 selects the address of the packet to be transmitted or the address of the received packet. _i And the address selector 43 _i The memory 34 based on the address selected by _i Applicable global area 34 _{i, 1} Or local area 34 _i1,2 Access instruction unit 44 for instructing access to _i The internal communication means 36 rather than via the external communication means 37 _i The processing is performed so as to increase the amount of data per unit time of communication processing via the network.
[0033]
Further, the communication instruction unit 42 _i Includes a token adding unit 42a for adding a token to a packet to be transmitted. _i A return token detection unit 42b for detecting a return token issued when a buffer on the other side or the buffer in the external communication means 37 is free and transmission is possible. _i And a termination output unit 42 indicating that the transmission process for the packet to be transmitted has been completed. _i And have.
[0034]
Further, in this embodiment, the self-addressed determination unit 40 _i As shown in FIG. 6, a self-addressed bit reading unit 40a that reads out a self-addressed bit included in a predetermined position of the packet. _i And a bit determination unit 40b for determining the read bit. _i And have. “Self-addressed bit” refers to a bit indicating whether or not the destination of packet transfer is its own processing device.
[0035]
Subsequently, an operation at the time of transmission according to the present embodiment will be described with reference to FIG.
A packet arriving from a network which is an external communication means is received by a reception buffer, and then when a memory access priority (not shown) is taken, a global area 34 of the memory is obtained. _{i, 1} Is remembered. CPU33 _i Since processing is performed in the local area, the global area 34 _{i, 1} To local area 14 _{i, 2} Transfer to is required. A packet to be transmitted to the network which is the external communication means 37 is transmitted to the local area 34. _{i, 2} To global area 34 _{i, 1} Need to be transferred to. As shown in FIG. 7, in step SJ1, the CPU 33 _i The packet header to be transmitted by the memory 34 _i To the transmission queue provided on the main memory (not necessarily the global area). This fact is related to the communication processing unit 35. _i And the inside / outside communication processing unit 35 _i An instruction to send to is issued.
[0036]
In step SJ2, the internal / external communication processing unit 35 _i Shows the packet header in the transmission buffer 31. _i The address selecting unit 43 _i Via the access instruction unit 44 for the packet instructed _i Thus, for example, an 8-byte fetch request is sent to the memory 34. _i Put out. Here, 8 bytes means the transmission buffer 31. _i Is a unit that does not overflow.
In step SJ3, the memory 34 _i The fetch request is issued several times until all packet headers stored in the packet header are completed, and the returnable transmission buffer 31 _i Write to.
[0037]
In step SJ4, all the packet headers are read and the returnable transmission buffer 31 is read. _i Retained. In step SJ5 at the time of reading the packet header of every 8 bytes, the self-address determination unit 40 _i Determines whether the destination of the packet to be transmitted is its own processing apparatus or another external processing apparatus. The determination is made by the self-addressed determination unit 40. _i Self-addressed bit reading section 40a _i The self-addressed bit at a predetermined position in the packet header indicating whether the destination of the packet to be transmitted is its own processing device or “1”, or another external processing device or “0” This is done by reading The read self-addressed bit is the bit determination unit 40b. _i Thus, it is determined whether the bit is “1” or “0”, and the result is sent to the communication instruction unit 42. _i Notify
[0038]
Here, the packet header has at least a self-addressed bit and a destination address. Specifically, the format of the packet header is as shown in FIG. 8, and the packet header includes, for example, an identifier of the destination processing device in the first word, and the packet in the mth word. Information indicating the size of the packet, and the nth includes a self-addressed bit indicating whether or not the packet is addressed to itself and an address indicating the storage location of the memory of the destination processing apparatus in which the packet is to be stored It is. Data representing the substantial content called the body from the p-th after these packet headers is included.
[0039]
Self-addressed determination unit 40 _i If it is determined that the packet is not transmitted to itself, the process proceeds to step SJ6. In step SJ6, the communication instruction unit 42 _i Token adding unit 42a _i For example, one token is added for every 4 bytes per word determined by the number of communication paths to the external communication means, and the communication processing unit 35 _i Is the return transmission buffer 31 _i Is controlled so as not to overflow, and the return possible buffer 31 _i Is sent to the external communication means 37.
[0040]
Thereafter, the return token detecting unit 42b is connected via the external communication means 37. _i Until the return token is detected from the transmission destination PE. If it is detected in step SJ7 that the return token has been returned, the process returns to step SJ6 and adds a token for each word. A packet header is sent to the external communication means 37.
The above processing steps SJ6 and SJ7 are similarly repeated not only for the packet header but also for the body, and the termination output unit 42c. _i Is repeated until a terminator indicating that transmission of all data of the packet has been completed is sent in step SJ8.
[0041]
On the other hand, in step SJ5, the self-addressed determination unit 40 _i If it is determined that it is addressed to itself, the process proceeds to step SJ9.
In step SJ9, the communication instruction unit 42 _i Is the address selector 43. _i The transmission buffer 31 _i The access instruction unit 44 uses the address extracted from the packet to be transmitted held in the access instruction unit 44. _i The transmission buffer 31 _i The local area 34 of the memory indicated by the address of the packet to be transmitted stored in _{i, 1} To write to. In this case, unlike the transfer of the packet via the external communication unit 37, the token is not added to the packet, and it is not necessary to detect the return token. This is because the communication processing unit 35 _i Is how many bytes of the packet _i And receive the same number of bytes from the memory 34 _i This is because it knows what to send to the store bus.
[0042]
To explain this point in more detail, the token is the transmission buffer 31. _i To receive buffer 32 _i Is necessary for sending data so as not to overflow, and when it is transferred to itself, it is as if the transmission buffer 31 _i Receive buffer 32 _i It appears to the communication processing unit as if Therefore, the processing starts from the end of the role of the token.
[0043]
As described above, since the present embodiment is configured as described above, the CPU 33 _i Can perform processing using the data in the cache, and when the communication processing unit finishes packet transfer, it can move to the next processing that opened the transfer data. When the processing is completed, even if the processing data is data to be transferred to the network, the communication processing unit transfers the data, so that the next processing can be performed.
[0044]
Further, when a network that is a connection device between processing devices (between PEs) is configured with a crossbar or the like, the bus width between the PE and the network is limited from the viewpoint of hardware. Alternatively, the transfer time may be longer. In this case, the route 39 to the network _i By each processing device 30 ₀ ~ 30 _n By configuring the internal communication means so that the throughput of the internal communication means is improved, for example, the external communication means is configured so that the data transmission of the internal communication means is 2 bytes / 1 cycle with respect to 1 byte / 2 cycles. Thus, the waiting time of the CPU until the processing data is ready can be shortened.
[0045]
In the above description, the processing amount of the CPU is described as being larger than the processing amount of the communication processing unit. However, when the processing amount of the communication processing unit is large, it can be considered that it can be dealt with by increasing the number of communication processing units.
[0046]
Next, a second embodiment will be described based on FIG.
Unlike the processing apparatus according to the first embodiment, the distributed memory type processing apparatus according to the second embodiment is the self-addressed bit reading section 40a as the self-addressed determination section. _i And bit determination unit 40b _i Instead of the address reading unit 50a _i And a comparison unit 50b for comparing the machine number with its own processing device _i Are provided.
[0047]
In other words, in the second embodiment, unlike the first embodiment, the packet format is not shown in FIG. 8, but as shown in FIG. If the number of the processing apparatus indicating the destination is the same as the machine number of the processing apparatus of its own, it is determined that the transmission data is addressed to itself.
[0048]
Unlike the first embodiment, this example does not need to provide a bit indicating the address to the packet and can use the destination of a normal processing device, so that it is not necessary to change the packet format and is therefore easy to handle. .
In addition, the same code | symbol as the code | symbol used in the case of the processing apparatus of a 1st Example shows the same thing.
In the above example, a method of performing data communication using a token and a return token has been described. However, the present invention is not limited to this example, and the IEEE CSMA / CD (Ethernet) method, token passing ring method, token passing bus, etc. It can also be applied to a system, a MAN system, a digital PBX system, and the like.
[0049]
【The invention's effect】
As described above, according to the present invention, the internal communication means having a larger data width compared to the external communication means is provided, and whether the destination of the packet to be transmitted is another processing device or not. It is determined whether it is a processing device, and in the case of a packet addressed to itself, it has a self-wrapping function by instructing to write to the corresponding area of the memory.
[0050]
Accordingly, the CPU is not burdened to transfer data to itself using the function of the communication processing unit without using a CPU or separately providing a device such as a DMA, and the configuration is simplified. be able to.
In addition, the throughput of the transmission to itself is better than that of the communication processing unit communicating with the external processing device. Therefore, it is possible to improve the performance of the multiple processing devices and the data communication method by shortening the waiting time of the CPU of each processing device.
[Brief description of the drawings]
FIG. 1 is a principle block diagram of the first invention.
FIG. 2 is a principle flowchart of the second invention.
FIG. 3 is a block diagram showing an embodiment of the first invention.
FIG. 4 is an overall block diagram of the device configuration according to the first embodiment.
FIG. 5 is a block diagram according to the first embodiment.
FIG. 6 is a block diagram showing an internal / external communication processing unit according to the first embodiment.
FIG. 7 is a flowchart according to the first embodiment.
FIG. 8 is a diagram showing a packet format example according to the first embodiment;
FIG. 9 is a block diagram showing an internal / external communication processing unit according to the second embodiment.
FIG. 10 is a diagram showing an example of a packet format according to the second embodiment.
FIG. 11 is a block diagram according to a conventional example.
[Explanation of symbols]
10 ₀ -10 _n , 30 ₀ ~ 30 _n Processing equipment
11 _i , 31 _i Returnable send buffer
12 _i , 32 _i Receive buffer
13 _i , 23 _i (33 _i Data processing unit (CPU)
14 _i , 24 _i , 34 _i memory
15 _i , 25 _i , 35 _i , 45 _i Internal / external communication processor
16 _i , 26 _i , 36 _i Internal communication means
17, 37 External communication means

Claims (2)

A plurality of processing devices (10 ₀ to 10 _n ) each having a memory (14 _i ; i = ₀ to _n ) and a data processing unit (13 _i ) and connected to each other via an external communication means (17). )
Each processing device (10 _i )
A reception buffer (12 _i ) for receiving a packet transferred via the external communication means (17);
The packet to be transmitted is held, and the held packet is switched to either the external communication means (17) or the internal communication means (16 _i ) in accordance with an instruction from the internal / external communication processing unit (15 _i ) and transmitted. A returnable transmission buffer (11 _i );
Determination of whether the destination of the packet to be transmitted is self or another processing device, switching of communication means of the packet transmission destination for the returnable transmission buffer (11 _i ) based on the determination result, and reception buffer (12 _i ) or an instruction for writing to the corresponding storage area (14 _{i, 0 to} 14 _{i, m} ) of the memory (14 _i ) indicated by the packet received via (12 _i ) or the packet addressed to itself By providing a larger number of parallel communication paths for the internal communication means (16 _i ) than for the means (17) , or by reducing the minimum interval of communication processing, the internal communication means (16 _i ), And an internal / external communication processing unit (15 _i ) that performs processing so as to increase the amount of data per unit time of communication processing via
The memory (14 _i ) is connected to the data processing unit (13 _i ), the reception buffer (12 _i ), the returnable transmission buffer (11 _i ), and the internal / external communication processing unit (15 _i ) and external communication means. A multi-processing device comprising internal communication means (16 _i ) having a larger number of parallel communication paths than (17). The internal / external communication processing unit (25 _i ) is a self-addressed determination unit (20 _i ) that determines whether the destination of a packet to be transmitted is its own processing device or another processing device ,
When a transmission instruction is given and transmission is possible , switching of communication means for sending packets to the returnable transmission buffer (16 _i ) based on the determination result by the self-addressed determination unit (20 _i ) A communication instruction unit (22 _i ) for selecting an address for the address selection unit (23 _i ) and instructing an access to the memory (14 _i ) based on the address ;
Based on the instruction, the address selection unit which performs one of selection of addresses of the address or the received packet of the packet to be transmitted (23 _i), on the basis of the selected address by the address selector (23 _i) An access instruction section (24 _i ) for instructing access to the corresponding storage area (14 _{i, 0 to} 14 _{i, m} ) of the memory (14 _i ), and internal communication rather than external communication means (17). The multi-processing device according to claim 1, wherein processing is performed so as to increase a data amount per unit time of communication processing via the means (16 _i ) .

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