JP3629006B2 - Device for determining initial arrangement of integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an automatic cell placement method in the layout design of integrated circuits such as LSI, VLSI, and ULSI, and in particular, the approximate wiring length for optimizing the cell placement of an integrated circuit using a mini-cut method. The present invention relates to an increase / decrease prediction apparatus and an integrated circuit initial arrangement determination apparatus.
[0002]
With recent advances in manufacturing technology, there is a remarkable increase in the degree of integration of integrated circuits and an increase in circuit scale, and the number of cells included in an integrated circuit chip is steadily increasing. Along with this, the factor that determines the performance of the circuit is that the specific gravity of the wiring delay is higher than the delay of the gate.
[0003]
[Prior art]
Partitioning is known as a method for determining an initial arrangement of cells of an integrated circuit. In this partitioning, a given circuit is divided into K (K is a natural number) partial circuits (blocks) to minimize the number of nets, that is, the number of cuts across the blocks. It is. A mini-cut method is known as a typical algorithm of this partitioning.
[0004]
In this mini-cut method, cut lines for cutting chips horizontally and vertically and their processing order are determined, and the layout is determined by sequentially performing logical two-division for each cut line. At this time, the cut line may be set at the boundary of all blocks.
[0005]
When the processing order of the cut lines is determined, an area (a set of blocks) on the chip is determined for each cut line. Furthermore, depending on the location of the cut line, the condition of the number of cells in the division (cell set M _1, M ₂ When dividing into M _1, M ₂ The upper limit of the number of cells is also determined. The logical division is performed so as to minimize the number of wirings (nets) passing on the cut line. At that time, the division must satisfy the cell number condition.
[0006]
Thus, the basis of the mini-cut method is to move cells arranged in one block to another block and reduce the number of nets crossing the cut line.
FIG. 27 is a flowchart for explaining a conventional mini-cut method.
[0007]
First, an initial arrangement of cells and a cut line are determined (S1). Next, a cell gain g is obtained for each cell (S2). The cell gain g is the number of cuts that decreases when a certain cell is moved to another block.
[0008]
Subsequently, the cell gain g is sorted in descending order for each block (S3). Subsequently, the cell having the largest cell gain g is selected from the block having the largest cell size, and this cell is moved to another block (S4).
[0009]
Next, the cell gain g of the moved cell and the cell connected to the cell by the net is updated, and the cell gain g is sorted again for each block (S5). Then, it is determined whether or not there is a cell having a positive cell gain g (S6), and if it exists (S6, YES), the processes in steps S4 to S5 are repeated again. When it is determined that there is no longer a cell having a positive cell gain g (S6, NO), the process ends.
[0010]
With the above processing, the initial arrangement of cells is optimized.
The above-described mini-cut method will be described more specifically with reference to FIG.
In the figure, a perpendicular line 1 indicated by a broken line is a cut line. Further, the cell 2 shown by knitting is a cell having a positive cell gain g, and the cell 3 not knitted is a cell having a cell gain g of “0”.
[0011]
In any of the cell arrangement states shown in FIGS. 32A, 32B, and 32C, the number of cuts can be reduced by moving the knitting cell 2 to the other block on the other side of the cut line 1. Can be reduced. In actual cell movement, in each block, consideration is given so that the ratio between the area of the block and the total area of the cells included in the block is balanced.
[0012]
[Problems to be solved by the invention]
In the conventional mini-cut method described above, the number of net connections between a set of cells included in each divided block, i.e., by hierarchically performing an operation to minimize the number of cuts, A more optimal cell arrangement is obtained.
[0013]
However, in the mini-cut method, cell placement is determined using only information in the hierarchically divided areas (cell total area, number of cells, etc.), so the wiring length of the entire integrated circuit is controlled. There was a problem that could not be done.
[0014]
For this reason, the length of a certain net becomes longer than necessary, and as a result, the performance of the entire integrated circuit, such as signal propagation delay, is degraded. FIG. It is a figure explaining the method of a general schematic wiring. In this schematic wiring, wiring is executed on the assumption that a terminal exists at the center of a divided block instead of an actual terminal. Based on this execution result, a virtual wiring length (rough wiring length) is obtained. In the figure, net1, net2, and net3 are nets, and white circles 1 to 6 are virtual terminals. However, in this method, the length of the net connected to a fixed cell such as a RAM, a ROM, or an I / O buffer cell may be calculated shorter than the actual length. For this reason, it is important to predict the wiring length of the net more accurately in order to perform the cell placement while keeping the net line length restriction specified in advance.
[0015]
In addition, in the mini-cut method, as the hierarchization progresses and each block is further divided into smaller blocks, the actual wiring length tends to be longer in a block including many cells, and the wiring length calculated using the schematic wiring And the actual wiring length is different. That is, the approximate wiring length calculated based on the approximate wiring information is easily calculated shorter than the actual wiring length.
[0016]
Therefore, in this case as well, it is important to predict the wiring length of the net more accurately in order to perform cell placement while complying with the specified net line length restriction.
[0017]
In the mini-cut method, the present invention makes it possible to predict more accurately the increase / decrease of the net wiring length of the net when moving net cells to the divided block when performing schematic wiring between the divided blocks. Objective. In addition, as described above, the cells are arranged so that the restrictions on the designated wiring length of the net can be observed while accurately predicting the increase / decrease of the approximate wiring length of the net when moving the cell of the net to the divided block. For the purpose.
[0018]
[Means for Solving the Problems]
FIG. 1 is a diagram for explaining the principle of the present invention (first invention).
The first invention includes the following means.
[0019]
Assuming that the terminal of each cell is located at the center of the block to which each cell belongs, the rough wiring unit 41 performs wiring between cells connected to each net.
The wiring length increase / decrease predicting means 42, when dividing a block by a cut line based on the rough wiring information obtained by the rough wiring means 41, selects a cell belonging to the block with respect to the cut line. If it moves to the divided block on the side of, it is predicted whether the approximate wiring length of the net connected to the cell will increase or decrease.
[0020]
Therefore, when a block is divided by a cut line, it is determined whether the cell that belongs to the block is moved to any divided block, so that the approximate wiring length of the net to which the cell is connected does not decrease or increase It becomes possible to do.
[0021]
FIG. 2 is a diagram for explaining the principle of the present invention (second invention).
In the second invention, a cut line is set in an integrated circuit region, and cells are divided between regions divided by the cut line so that the number of cuts, which is the number of wires cut by the cut line, is minimized. On the premise of an initial arrangement determining device for an integrated circuit that determines the initial arrangement of cells constituting the integrated circuit while repeating the movement operation, the following means are provided.
[0022]
Assuming that the terminal of each cell is located at the center of the block to which each cell belongs, the rough wiring means 51 performs wiring between cells connected to each net.
The wiring length calculation means 52 obtains the approximate wiring length (logical wiring length) of each net based on the approximate wiring information obtained by the approximate routing means 51.
[0023]
Based on the approximate wiring length of each net calculated by the wiring length calculating means 52, the vibration net detecting means 53 determines a net whose current approximate wiring length exceeds a preliminarily constrained wiring length. Detect as.
[0024]
The wiring length increase / decrease prediction means 54 is based on the rough wiring information obtained by the rough wiring means 51 when the block belonging to the vibration net detected by the vibration net detection means 53 is divided by the cut line. It is predicted whether the cell connected to the vibration net belonging to the block will be moved to any divided block to increase or decrease the approximate wiring length of the violation net.
[0025]
The mini-cut method executing means 55 moves the cell connected to the above-mentioned violation net to the divided block where the wiring length is predicted not to be reduced or increased by the wiring length reduction prediction means 54, The cell is set as a fixed cell, and then the mini-cut method is performed on the block.
[0026]
According to the second aspect of the invention, before the mini-cut method is performed on the block to which the cell connected to the vibration net belongs, the cell whose length is not decreased or increased is not increased. Since it is moved to the divided blocks, it is possible to reliably reduce the wiring length of the above-mentioned vibration net in the process of hierarchically executing the mini-cut method, and as a result, the number of the vibration nets is reduced. Can be made.
FIG. 3 is a diagram for explaining the principle of the present invention (third invention).
[0027]
In the third aspect of the invention, a cut line is set in the area of the integrated circuit, and cells are divided between the areas divided by the cut line so that the number of cuts, which is the number of wires cut by the cut line, is minimized. On the premise of an initial arrangement determining device for an integrated circuit that determines the initial arrangement of cells constituting the integrated circuit while repeating the movement operation, the following means are provided.
[0028]
Assuming that the terminal of each cell is located at the center of the block to which each cell belongs, the rough wiring means 61 performs wiring between cells connected to each net.
The wiring length calculating means 62 obtains the approximate wiring length (logical wiring length) of each net based on the approximate wiring information obtained by the approximate routing means 61.
[0029]
The critical net detecting means 63 critically determines a net whose current approximate wiring length exceeds α% of the preliminarily restricted wiring length based on the approximate wiring length of each net calculated by the wiring length calculating means 62. Detect as net.
[0030]
The stable net detecting means 64 detects a net that has been cut by the cut line before the execution of the mini-cut method and has been cut by the cut line after the execution of the mini-cut method as a stable net.
[0031]
The cell moving unit 65 is a stable net based on the detection result of the critical net detection unit 63 and the detection result of the stable net detection unit 64, and is connected to the net that is also a critical net. Move all cells to the same block.
[0032]
The mini-cut method executing means 66 executes the mini-cut method using the cell arrangement obtained by the process 65 of the cell moving means as the initial arrangement.
The α is a value within the range of 70 ≦ α ≦ 80, for example.
[0033]
In the third aspect of the invention, since the critical net that is a stable net is moved to the same block after all cells connected to the critical net are executed, the critical net is cut. It is easy to obtain a final arrangement of cells that are not performed. Therefore, it is possible to reduce the probability that a critical net changes to a violation net, and in the process of hierarchically executing the mini-cut method, it is possible to gradually shorten the critical net wiring length. Finally, the wiring length can be shortened.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
In the first embodiment of the present invention, when performing schematic wiring in the mini-cut method, if a fixed cell is connected to a certain net, the distance between the fixed cell and the center coordinate of the block to which the fixed cell belongs is determined. By obtaining this distance and adding this distance to the net line length, the approximate wiring length can be obtained more accurately.
[0035]
FIG. 4 is a diagram illustrating a cell arrangement state of the integrated circuit 140 in which fixed cells exist.
In the figure, the x-axis is set in the horizontal direction and the y-axis is set in the vertical direction. In addition, the numbers “1” to “5” in the x-axis and y-axis directions shown in the figure are the values of the block coordinates in the x-axis and y-axis directions, respectively.
[0036]
Each block of the integrated circuit 140 is identified by a block ID (block ID). This block ID is represented by (x, y). x and y are block coordinate values in the x-axis direction and y-axis direction of the block, respectively. White circles to which numbers “1” to “5” are assigned are virtual terminals of five cells (Cells 1 to 5) set in the schematic wiring of the integrated circuit 140. A black circle to which the number “6” is assigned is a terminal of the fixed cell Cell6. Furthermore, nets 1, 2, and 3 represent nets.
[0037]
FIG. 5 is a diagram showing a net list indicating to which net each of the six cells (Cell 1 to 6) is connected in the integrated circuit 140.
FIG. 6 is a diagram showing a cell list indicating information on cells connected to the nets (net1 to n3). As shown in the figure, in net1, information in which Cell1 and Cell6 are connected is indicated by a linked list. this,
net1 = {Cell1, Cell6}
It expresses with. Similarly,
net2 = {Cell2, Cell5}
net3 = {Cell3, Cell4}
It expresses.
[0038]
A list having the net1, net2, and net3 as elements (objects) is expressed as net2cell. That is,
net2cell = {net1, net2, net3}
It expresses.
[0039]
Further, FIG. 7 is a diagram showing the configuration of the cell table 150 that stores information such as which block belongs to each of the six cells (Cells 1 to 6) and whether or not it is a fixed cell. is there.
[0040]
In the figure, the value “i” of Cell ID (cell ID) is a number serving as an identifier of Celli. Cell position (x, y) is a coordinate value of a fixed cell. Furthermore, fixed Flag is a flag indicating whether or not each cell Celli (i = 1 to 6) is a fixed cell, and “1” indicates that it is a fixed cell.
[0041]
In the cell table 150 illustrated in FIG. 7, information indicating that Cell 6 having a cell ID value “6” is a fixed cell and the coordinate value is (30, 40) is stored. Information indicating that Cells 1 to 5 other than Cell 6 are not fixed cells is also stored.
[0042]
FIG. 8 is a diagram showing the configuration of a block table 160 that stores the value of the center coordinate of each block of the integrated circuit 140.
In the table 160, each block is indicated by a block ID, and the coordinates (x, y) of its center position (center position) are stored corresponding to the block ID. That is, for example, (5, 5) is stored as the center coordinates of the block whose block ID is (1, 1). Also, (25, 45) is stored as the center coordinates of the block whose block ID is (3, 5).
[0043]
FIG. 9 is a flowchart for explaining processing for obtaining the approximate wiring length of each net in the first embodiment.
First, the first object (object) is taken out from net2cell, and this is substituted into variable net (S101).
[0044]
Thereby, in the case of net2cell shown in FIG. 6, first, net1 is substituted into the variable net.
Next, it is determined whether or not the variable net is “NULL” (empty) (S102). If it is not “NULL” (S102, no), a block (for the net assigned to the variable net ( Schematic wiring is performed in block units. Then, based on the general wiring information obtained by this general wiring, the general wiring length of each net is calculated by the conventional method (S103).
[0045]
With this schematic wiring, the net net1 4 When the schematic wiring as shown in FIG. 10 is performed, a schematic wiring list shown in FIG. 10A is created. In FIG. 9A, grnet1 is a list of schematic wirings of the net net1, and (i, j) {i = 1 to 5; j = 1 to 5} are blocks belonging to the routing of the schematic wirings. Block ID.
[0046]
Next, the first block ID (i, j) is extracted from the net schematic wiring list set in the variable net, and the i and j are respectively stored in the variable block. x, block. Substitute for y (S104).
[0047]
Subsequently, it is determined whether or not there is an unprocessed block ID in the schematic wiring list, that is, whether or not a new block ID has been extracted from the schematic wiring list (S105). If an unprocessed block ID is extracted (S105, yes), it is checked whether there is a cell belonging to the block having the block ID. If there is a cell, the cell is a fixed cell. Is determined (S106).
[0048]
If it is a fixed cell (S106, yes), the distance between the fixed cell and the center coordinate of the block in which the fixed cell exists is calculated, and this distance is added to the already determined approximate wiring length. (S107). The distance is, for example, the distance d in the x-axis direction between the center coordinates of the fixed cell and the block. _x (The absolute value of the difference between the two x coordinates) and the distance d in the y-axis direction between the fixed cell and the center coordinates of the block _y (The absolute value of the difference between the two y-coordinates) (see FIG. 4).
[0049]
Next, the next block ID (i, j) is taken out from the schematic wiring list, and the i, j is assigned to the variable block. x, block. Substitute for y (S108). And it returns to step S105 again.
[0050]
On the other hand, if it is determined in step S106 that the cell is not a fixed cell (S106, no), the process proceeds to step S108 without performing the process in step S107.
The processes in steps S105 to S108 are repeated until it is determined in step S105 that there is no block ID extracted from the schematic wiring list (S105, no).
[0051]
Through the above processing, the fixed cell Cell6 belonging to the block ID (3, 5) is detected in the net net1, and the central coordinates (25, 45) of the block having the block ID (3, 5) and the fixed cell Cell6 The distance between the coordinates (30, 50) is added to the schematic wiring in step S107. The center coordinates (25, 45) of the block are read from the block table 160 in FIG. 8, and the coordinates (30, 50) of the fixed cell Cell6 are read from the cell table 150 in FIG.
[0052]
If it is determined in step S105 that the processes in steps S105 to S108 have been completed for all block IDs in the schematic wiring list of the first net extracted from net2cell (S105, yes), the next object is extracted from net2cell. (S109) The processes in steps S102 to S108 described above are performed again on the net that is the object.
[0053]
Thereby, in the case of net2cell shown in FIG. 6, next, schematic wiring is performed on net2 in step S103, and a schematic wiring list grnet2 shown in FIG. 10B is created. Since no fixed cell is connected to net2, the process of step S107 is not executed. Therefore, the approximate wiring length does not increase.
[0054]
Subsequently, net3 is taken out from net2cell as the next object in step S109, and schematic wiring is also performed in step 103 for this net3. Then, a schematic wiring list grnet3 shown in FIG. 10C is created. Since the fixed cell is not connected to net3 as well as net2, the process of step S107 is not executed. Therefore, the approximate wiring length does not increase.
[0055]
Next, in step 102, it is determined that the object extracted from the net2cell is “NULL” (S102, yes), and the processing of the flowchart of FIG. 9 ends.
[0056]
Next, a second embodiment of the present invention will be described.
In the second embodiment, when there are a plurality of cells connected to the net in the same block in a certain net, the probability is determined how much those cells are distributed depending on the number of cells, By adding the distribution probability to the net line length, the approximate wiring length can be obtained more accurately.
[0057]
FIG. 11 is a diagram showing an integrated circuit 200 having such a net.
In the figure, the net net3 is connected to five cells Cell3, 7, 8, 9, and 10 that exist in the block having the block ID (2, 2).
[0058]
The net list of this integrated circuit 200 is shown in FIG. 12, and the cell list is shown in FIG. FIG. 14 is a configuration diagram of a cell table 210 that manages to which block each cell of the integrated circuit 200 belongs. For example, by referring to the cell list of FIG. 12 and the cell table 210 of FIG. 14, five cells (Cell3, 7, 8, 9, 10) belonging to the net net3 are blocks having a block ID (2, 2). You can know that it belongs to.
[0059]
In the second embodiment, in a block to which a certain net belongs, the number of cells connected to the net and belonging to the block is defined as cellNum. And the wiring length w of the net in the inside of the block is
w = Klog (cellNum) (1)
Asking.
[0060]
At this time, K is an arbitrary constant. As the value of K, for example, when the perimeter of the block is L,
K = 0.7L (2)
And
[0061]
FIG. 15 is a flowchart for explaining the process for obtaining the approximate wiring length of the net in the second embodiment.
First, the top object (object) is taken out from net2cell, and this is substituted into variable net (S201).
[0062]
Next, it is determined whether or not the variable net is “NULL” (empty) (S202). If it is not “NULL” (S202, no), a block (for the net assigned to the variable net ( Schematic wiring is performed in block units. Then, based on the general wiring information obtained by this general wiring, the general wiring length of each net is calculated by the conventional method (S203).
[0063]
Next, the first block ID (i, j) is extracted from the net schematic wiring list set in the variable net, and the i and j are respectively stored in the variable block. x, block. Substitute for y (S204).
[0064]
Subsequently, it is determined whether or not there is an unprocessed block ID in the schematic wiring list, that is, whether or not a new block ID has been extracted from the schematic wiring list (S205). Then, if an unprocessed block ID is extracted (S205, yes), it is checked whether there is a cell belonging to the block having the block ID. If there is a cell, the number of cells is obtained and this is set as a variable. Substitute in cellNum (S206).
[0065]
Then, the wiring length w in the block is calculated by the above equation (1). Then, w is added to the already determined approximate wiring length (S207).
Next, the next block ID (i, j) is taken out from the schematic wiring list, and the i, j is assigned to the variable block. x, block. Substitute for y (S208). And it returns to step S205 again.
[0066]
The processes in steps S205 to S208 are repeated until it is determined in step S205 that there is no block ID extracted from the schematic wiring list (S205, no).
[0067]
With the above processing, in the case of the net net3 of the integrated circuit 200 shown in FIG. 11, (2, 2) is extracted as the block ID in the first step S204, and block. x is “2”. “2” is substituted for y. In step S206, the number of cells (= 5) connected to the net net3 belonging to the block having the block ID (2, 2) is calculated. Then, “5” is assigned to the variable cellNum. Subsequently, the calculation of the above formula (1) is executed in step S207, and the calculation result w is added to the approximate wiring length so far.
[0068]
In the next step S204, (2, 3) is extracted as the block ID, and block. x is “2”. “3” is substituted for y. In step S206, the number (= 1) of cells connected to the net net3 belonging to the block having the block ID (2, 3) is calculated. Then, “1” is assigned to the variable cellNum. Subsequently, the calculation of the above formula (1) is executed in step S207, and the calculation result w (= 0) is added to the approximate wiring length so far.
[0069]
In the case of the net net1 of the integrated circuit 200 shown in FIG. 11, the calculation of the equation (1) is executed in step S207 for the blocks having the block IDs (1, 1) and (3, 5). Since the number of blocks with the block IDs (1, 1) and (3, 5) is “1”, the intra-block wiring length w is “0”, and the approximate wiring length calculated in step 203 above. Does not change. Therefore, in this case, the same approximate wiring length as that in the conventional case can be obtained.
[0070]
In the case of the net net2 of the integrated circuit 200 shown in FIG. 11, the calculation of the above equation (1) is executed in step S207 for the blocks having the block IDs (5, 1) and (2, 4). Also in this case, since the number of blocks having the block IDs (5, 1) and (2, 4) is “1”, the same approximate wiring length as that of the conventional net is obtained as in the net 2 described above. It is done.
[0071]
As described above, when calculating the approximate wiring length of a net, for the block to which the cell of the net belongs, the distribution probability of the cell in the block based on the number of cells of the net belonging to the block is calculated. The intra-block wiring length w is calculated using the above-described formula (1), and this is added to the approximate wiring length calculated by the conventional method, so that a plurality of cells belonging to the same block are connected. The approximate wiring length of a net can be calculated more accurately than before.
[0072]
Next, a third embodiment of the present invention will be described.
In this third embodiment, when a block is cut in the mini-cut method, it is determined how much the wiring length increases or decreases when the cells included in the block are arranged in which divided block. The prediction is based on the wiring information.
[0073]
FIG. 16 is a schematic diagram for explaining the method of the third embodiment.
This figure shows a case where the block 302 to which the cell Cell2 connected to the net net2 belongs is cut by the cut line 304 in the integrated circuit 300. In this case, by cutting the block 302 in the vertical direction by the cut line 304, the block 302 is divided into two divided blocks 302L and 302R shown in FIG.
[0074]
At this time, the increase / decrease in the wiring length when the cell Cell2 is arranged in the two divided blocks 302L and 302R is predicted based on the schematic wiring information. In this case, if the cell Cell2 is arranged toward the divided block 302L, it is predicted that the approximate wiring length will decrease.
[0075]
FIGS. 17 to 20 show schematic wirings when cells belonging to a block (hereinafter referred to as source cells) are arranged in which divided block when the block is cut in the vertical direction by a cut line. It is a figure explaining the method of estimating whether length increases. A cell connected to the source cell via the net is called a target cell.
[0076]
FIG. 20 shows that when the source cell 411 is wired with the target cell 421 belonging to the upper block, the approximate wiring length increases when the block 410 to which the source cell 411 belongs is cut in the vertical direction. It is a figure explaining the method to predict. The target cell 421 is a cell directly connected to the source cell 411.
[0077]
In this case, the block 420 to which the target cell 421 belongs has already been divided, and the target cell 421 belongs to one of the divided blocks 420R and 420L. Also, the source cell 411 is arranged in either the right divided block 410R or the left divided block 410L by cutting the block 410 in the vertical direction.
[0078]
If the wiring connected to the target cell 421 passes through not only the divided block to which the target cell 421 belongs, but also the other divided block, as shown in FIG. Divided block 41 0 The approximate wiring length does not increase regardless of whether it is moved to R or the left divided block 410L.
[0079]
On the other hand, when the wiring connected to the target cell 421 passes only within the divided block to which the target cell 421 belongs, as shown in FIGS. Is moved to the divided block opposite to the target cell 421, the approximate wiring length is increased by the length β.
[0080]
When the wiring pattern of the target cell 421 is other than those shown in FIGS. 9A, 9B, and 9C, the increase in the approximate wiring length is “0”.
Next, FIG. 18 is a diagram for explaining a method for predicting an increase in the approximate wiring length based on the wiring pattern of the source cell 411.
[0081]
As shown in the figure, when the wiring connected to the source cell 411 passes through only one of the right divided block 410R and the left divided block 410L, the divided block through which this wiring passes is shown. When moving to another divided block, the approximate wiring length increases by the length β. That is, in this case, it is necessary to newly extend the schematic wiring by the length β.
[0082]
In cases other than the above, the approximate wiring length does not increase even if the source cell 411 is moved toward any divided block. For example, when the schematic wiring of the source cell 411 passes through the entire block 410 in the horizontal direction, the schematic wiring length does not increase.
[0083]
Next, FIG. 19 illustrates a method for predicting an increase in the approximate wiring length when the source cell 411 belongs to the upper block and the target cell 421 is a lower target cell belonging to the lower block. FIG.
[0084]
At this time, the block 420 to which the target cell 421 belongs has not been divided yet. In this case, the schematic wiring pattern connected to the target cell 421 passes only one of the two divided blocks 421R and 421L generated when the block 420 is cut in the vertical direction in the future. If the pattern is such that, when the source cell 411 is moved to a divided block opposite to the divided block, the approximate wiring length increases by β. Except for such a case, the approximate wiring length does not increase.
[0085]
FIG. 20 is a diagram for explaining the prediction method of FIG. 19 in more detail.
As shown in FIG. 2A, before dividing the block 410 to which the source cell 411 belongs in the vertical direction, the schematic wiring connected to the source cell 411 extends downward in the vertical direction, and the lower target It is assumed that the schematic wiring connected to the cell 421 extends up and down in the vertical direction and right side in the horizontal direction.
[0086]
In this case, as shown in FIG. 4B, when the source cell 411 is moved toward the left divided block 410L, the approximate wiring length increases by the length β. On the other hand, as shown in FIG. 5C, when the source cell 411 is moved toward the right divided block 410R, the approximate wiring length does not increase.
[0087]
Further, as shown in FIG. 4D, before the block 410 to which the source cell 411 belongs is divided in the vertical direction, the schematic wiring connected to the source cell 411 extends to the lower side in the vertical direction and both sides in the horizontal direction. It is assumed that the schematic wiring connected to the lower target cell 421 extends up and down in the vertical direction and right side in the horizontal direction.
[0088]
In this case, as shown in FIG. 5E, when the source cell 411 is moved toward the left divided block 410L, the approximate wiring length increases by the length β. On the other hand, as shown in FIG. 5F, when the source cell 411 is moved toward the right divided block 410R, the approximate wiring length does not increase.
[0089]
As described above, when the block 410 to which the source cell 411 belongs is cut in the vertical direction, the source cell 411 is divided into either the divided block 411R or the divided block 411L based on the schematic wiring pattern information of the source cell 411 and the target cell 421. Although the method for predicting whether or not the approximate wiring length increases or does not increase when moving in the direction described above is basically the same when the source cell 411 and the target cell 421 are connected by the approximate wiring in the horizontal direction. It is possible to predict whether the wiring length will increase or not increase depending on the method.
[0090]
It is also possible to predict not only the case where the approximate wiring length is “increased” or “not increased” but also the case where the approximate wiring length is decreased. That is, in consideration of patterns other than those shown in FIGS. 17 to 20, if the position to move the source cell 411 is determined so that the distance between the source cell 411 and the target cell 421 is basically shortened. Good.
[0091]
Next, a fourth embodiment of the present invention will be described.
In the fourth embodiment, a net that does not comply with a pre-specified line length constraint is defined as a violation net, and when a block to which a cell connected to the violation net belongs is divided. Using the method of the third embodiment, the cell is moved toward the divided block where the approximate wiring length decreases (if the cell cannot be moved to the divided block where the approximate wiring length decreases, the approximate wiring length does not increase. The cell is moved as a fixed cell after the movement.
[0092]
Since the vibration net set as a fixed cell in this way is not handled as a cell to be moved when the mini-cut method is executed, the approximate wiring length of the violation net will not increase due to the execution of the mini-cut method. Absent. By applying the above processing to the cells connected to the vibration net before each mini cut method executed hierarchically, the approximate wiring length of the violation net is surely reduced. It becomes possible to finally eliminate the vibration net.
[0093]
Hereinafter, the integrated circuit 400 illustrated in FIG. 21 will be described as an example.
For the three nets net1, 2, and 3 in the integrated circuit 400, the wiring lengths of “60”, “60”, and “80” are designated in advance as line length constraints (designated wiring lengths). Shall. Therefore, the net net1 becomes a violation net when its logical wiring length exceeds “60”. Similarly, a violation net is established when “60” is exceeded for net net2 and “80” is exceeded for net net3. The logical wiring length corresponds to, for example, the schematic wiring length. The unit of the length of the logical wiring length and the approximate wiring length is, for example, the length of the grid interval.
[0094]
FIG. 22 is a diagram showing a configuration of a management table 450 that manages whether or not each net of the integrated circuit 400 is a violation net.
As shown in the figure, the management table 450 stores designated wiring lengths, logical wiring lengths, violation flags (critical flags), and critical flags (critical flags) corresponding to the nets 1, 2, and 3. Has been.
[0095]
The above-mentioned violation flag is set to “TRUE” when the corresponding net becomes a violation net. If it is not a vibration net, it is set to “FALSE”.
[0096]
In this embodiment, a net whose logical wiring length exceeds α% of the designated wiring length is defined as a critical net. As the value of α, for example, a value in the range of “70” to “80” is used. The critical flag is set to “TRUE” when the corresponding net is a critical net, and is set to “FALSE” when the net is not a critical net.
[0097]
Further, the net list and cell list shown in FIGS. 23 and 24 are created for the integrated circuit 400.
In the management table 450 shown in FIG. 22, the fact that the net net1 is a violation net is stored as a violation flag. Further, it is stored by a critical flag that the net net3 is a critical net. Further, the fact that the net net2 is neither a violation net nor a critical net is stored by a violation flag and a critical flag.
[0098]
FIG. 25 is a flowchart for explaining a method of executing the mini-cut method in the fourth embodiment.
First, the first object is extracted from net2cell and is substituted for variable net (S401).
[0099]
Subsequently, it is determined whether or not the variable net is “NULL” (S402). This determination is a process of determining whether or not the determination of the vibration net has been completed for all the nets connected to the net2cell.
[0100]
In step S402, it is determined by referring to the management table 450 whether the net set in the variable net is a violation net (S403).
[0101]
As a result of this determination, it is determined that the net net1 is a violation net.
If it is determined in the above step 403 that the net set in the variable net is a violation net (S403, yes), it belongs to the block that is connected to that net and is currently the cut target. After clustering (clustering) processing is performed in which the cells are moved toward the divided blocks where the approximate wiring length decreases and fixed (clustering), the cells to be clustered are set as fixed cells (S404). ).
[0102]
The fixed cell setting process is performed using, for example, a specific flag prepared for each cell. By the above processing, for example, when the block whose block ID is (2, 5) is the block to be cut, the processing of step S404 is performed on the cell Cell6, and the cell Cell6 It is moved toward the divided block 425L shown in FIG. 21, which is generated when cutting in the direction.
[0103]
Next, the next object is taken out from net2cell and substituted into variable net (S405), and the processes of steps S402 and S403 are performed again.
As a result, it is determined in step S403 that the net net2 is not a vibration net (S403, no), and then the process proceeds to step S405.
[0104]
In step S405, the net net3 is extracted from the net2cell, the net net3 is substituted into the variable net, and the process returns to step S402. Subsequently, in step 403, it is determined that the net net3 is not a vibration net (S403, no), and the process proceeds to step S405.
[0105]
In step S405, the object is not extracted from the net2cell, and “NULL” is set in the variable net. Then, the process returns to step S402 again, it is determined that the variable net is “NULL” (S402, yes), and the mini-cut method is executed in step 406.
[0106]
The mini-cut method is performed on cells other than fixed cells. Therefore, the cell Cell6 of the net 1 determined to be connected to the above-described vibration net is not moved because it is set as a fixed cell.
[0107]
Next, a fifth embodiment of the present invention will be described.
In the fifth embodiment, the handling of a stable net when executing the mini-cut method proposed by the applicant of the invention of the Japanese Patent Application Laid-Open No. 7-141415 previously filed by the present applicant is described above. Applies to the net.
[0108]
In the above-mentioned invention, a net that is cut before execution of the mini-cut method and that is also cut after execution of the mini-cut method is defined as a stable net, and all the nets connected to the stable net are defined. The cell is forcibly moved to one block to obtain the optimum arrangement of the cells. In addition, the cell thus moved is regarded as a fixed cell and is prohibited from being moved again by the execution of the mini-cut method.
[0109]
In the fifth embodiment, a net that is a critical net is preferentially selected from the stable nets, and all cells connected to the critical net are moved to one block.
[0110]
A critical net can be thought of as a reserve arm of a violation net. When a cell connected to the critical net is moved to the other block by executing the mini-cut method, its wiring length increases. There is a possibility of becoming a violation net. Therefore, for the net that has become a critical net, it is necessary to perform an operation for making the wiring length shorter by combining the net into one block. Further, it is known that the stable net has a high probability of being cut even after execution of the mini-cut method. Therefore, in the initial cell placement (initial solution) given before the mini-cut method, reducing the number of critical nets as stable nets as much as possible reduces the wiring length of critical nets. Is desirable.
[0111]
The fifth embodiment is basically based on the above idea.
FIG. 26 is a flowchart for explaining a process of making a critical net that is a stable net before each execution into a non-stable net when the mini-cut method is repeatedly executed. In this flowchart, when a critical net is detected, a table similar to the management table 450 shown in FIG. 21 is referred to.
[0112]
When the execution of the mini-cut method is completed, first, the moved flag (moved Flag) of all the cells in the integrated circuit is set to “0” (S501).
The moved flag is a flag individually provided for all cells in the integrated circuit, and is a flag indicating whether or not the corresponding cell has been moved once by execution of the mini-cut method. Then, it is set to “1” if it has been moved, and “0” if it has not been moved.
[0113]
Next, a net that has been registered as a stable net before execution of the mini-cut method and that has been cut after execution of the mini-cut method is selected as a stable net, and the net is selected as a stable net table. (S502).
[0114]
This stable net table is configured as shown in FIG. 13 of the above-mentioned specification of the invention, and the stable net is managed by a flag (stableNetTable [i] .Flag). Note that i is a net number. This flag is a flag for storing whether or not the corresponding stable net has been subjected to the processes of steps S505 to S507 described below.
[0115]
Subsequently, all the stable net table flags are cleared to “0” (S503).
That is, the fact that all stable nets are unprocessed is registered in the stable net table.
[0116]
Next, the following steps S505 to S507 are repeated until all the flags of the stable net table become “1”.
In step S505, a critical net is preferentially selected from the stable nets whose flag is “0” registered in the stable net table. If there are multiple critical nets, a critical net is selected at random from among them. If there is no more critical net, the remaining stable nets are selected at random (S505).
[0117]
In the next step S506, all the cells connected to the selected net are moved to one block. In this case, the selection of the block to be moved is determined by, for example, the algorithm shown in the flowchart of FIG. 10 or FIG. That is, for example, as shown in the flowchart of FIG. 10, the moved flags of all the cells connected to the selected net are checked, and if the moved flag of all the cells is “0”, which block is moved to Whether to do it is selected at random. On the other hand, if cells whose moved flag is “1” are gathered only in one block, the cells belonging to the other block are moved to that block.
[0118]
In the subsequent step S507, the stable net table flag is set to “1” for the stable net in which the cell has been moved. Also, the moved flag of all cells connected to the stable net is set to “1”.
[0119]
Thereby, since all cells of the stable net in which all the cells are moved to one block are handled as fixed cells, they are not moved in the processing of the subsequent steps S505 to S506. The situation where the process of the moved stable net becomes invalid can be prevented.
[0120]
The result of the processing shown in the flowchart of FIG. 26 described above is given to the mini-cut method as an initial solution (initial arrangement), and by executing the mini-cut method, it becomes easy to obtain a final solution in which the critical net is not cut. As a result, the wiring length of the critical net can be shortened.
[0121]
The first to fifth embodiments can be combined.
That is, the sixth embodiment, which combines the first, third and fourth embodiments, makes it possible to more accurately determine the approximate wiring length of the vibration net and to reduce the number of the vibration nets. Can do.
[0122]
Further, according to the seventh embodiment which combines the first, second, third and fourth embodiments, the approximate wiring length of the vibration net can be obtained more accurately than in the sixth embodiment. As it becomes possible, the number of violation nets can be reduced.
[0123]
Furthermore, the eighth embodiment combining the first, third, fourth and fifth embodiments makes it possible to more accurately determine the approximate wiring length of the vibration net and It is possible to reduce the number of the vibration nets by reducing the probability of changing to the vibration nets.
[0124]
Furthermore, according to the ninth embodiment that combines the first, second, third, fourth, and fifth embodiments, the approximate wiring length of the vibration net can be obtained more accurately than the eighth embodiment. As well as reducing the probability that a critical net will change to a violation net, thereby further reducing the number of violation nets.
[0125]
【The invention's effect】
As described above, according to the present invention, in the cell arrangement of an integrated circuit, it is possible to more accurately predict increase / decrease in the approximate wiring length of a net cell when moving to a divided block, and to specify It is possible to reduce the number of nets exceeding the specified wiring length. Therefore, it is possible to observe the wiring length restriction of each net. As a result, the delay due to wiring can be suppressed within a specified range, and the performance of the circuit can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram (part 1) for explaining the principle of the present invention;
FIG. 2 is a diagram (part 2) for explaining the principle of the present invention;
FIG. 3 is a diagram (part 3) for explaining the principle of the present invention;
FIG. 4 is a diagram for explaining a method of obtaining a wiring length of a net connected to fixed cells in an integrated circuit.
FIG. 5 is a diagram showing a net list in the integrated circuit shown in FIG. 4;
6 is a diagram showing a cell list in the integrated circuit shown in FIG. 4; FIG.
7 is a diagram showing a configuration of a cell table in the integrated circuit shown in FIG. 4;
8 is a diagram showing the configuration of a block table that stores the value of the center coordinate of each block of the integrated circuit shown in FIG. 4;
FIG. 9 is a flowchart illustrating a process for obtaining the approximate wiring length of each net in the first embodiment.
FIG. 10 is a diagram showing a schematic wiring list created by the schematic wiring process of the flowchart of FIG. 9;
FIG. 11 is a diagram illustrating an example of an integrated circuit in which a plurality of cells connected to one net exist in a certain block.
12 is a diagram showing a net list of the integrated circuit shown in FIG. 11. FIG.
FIG. 13 is a diagram showing a cell list of the integrated circuit shown in FIG. 11;
14 is a configuration diagram of a cell table that manages to which block each cell of the integrated circuit shown in FIG. 11 belongs.
FIG. 15 is a flowchart illustrating a process for obtaining the approximate wiring length of each net in the second embodiment.
FIG. 16 is a schematic diagram for explaining a technique for predicting increase / decrease in wiring length based on wiring information of schematic wiring in the third embodiment.
FIG. 17 is a diagram for explaining a method for predicting whether a divided wiring block increases the approximate wiring length when cells belonging to the block are arranged in a vertical direction when the block is cut in the vertical direction. Part 1).
FIG. 18 is a diagram for explaining a method for predicting, when a block is cut in a vertical direction by a cut line, if a cell belonging to the block is arranged in which divided block, an approximate wiring length is increased. Part 2).
FIG. 19 is a diagram for explaining a method for predicting, when a block is cut in a vertical direction by a cut line, if a cell belonging to the block is arranged in which divided block, an approximate wiring length is increased. Part 3).
FIG. 20 is a diagram for explaining a method for predicting whether a divided wiring block increases the approximate wiring length when cells belonging to the block are arranged in a vertical direction when the block is cut in the vertical direction; Part 4).
FIG. 21 is a diagram showing a configuration of an integrated circuit used for explaining a fourth embodiment.
FIG. 22 is a diagram showing a configuration of a management table in which a vibration net and a critical net are registered.
FIG. 23 is a diagram showing a net list of the integrated circuit shown in FIG. 21;
FIG. 24 is a diagram showing a cell list of the integrated circuit shown in FIG. 21;
FIG. 25 is a flowchart for explaining processing for handling a vibration net as a fixed cell in the fourth embodiment;
FIG. 26 is a flowchart for explaining movement processing for a critical net in the fifth embodiment;
FIG. 27 is a flowchart illustrating a mini-cut method.
FIG. 28 is a diagram for explaining a cell moving operation method by a mini-cut method;
FIG. 29 is a diagram showing general schematic wiring data of an integrated circuit in the mini-cut method.
[Explanation of symbols]
41, 51, 61 Outline wiring means
42, 52, 62 First wiring length calculation means
53, 63 Violation net detection means
54 Wiring length increase / decrease prediction means
55 Mini-cut method execution means
63 Critical net detection means
64 Stable net detection means
65 cell moving means

Claims (3)

While setting up a cut line in the integrated circuit and hierarchically repeating the operation of moving cells between the areas divided by the cut line so that the number of cuts, which is the number of wires cut by the cut line, is minimized, In an integrated circuit initial arrangement determining apparatus for determining an initial arrangement of cells constituting an integrated circuit,
Assuming that the terminal of each cell is located at the center of the block to which each cell belongs, schematic wiring means for wiring between cells connected to each net,
Based on the schematic wiring information obtained by the schematic routing means, a wiring length calculating means for calculating a schematic wiring length (logical wiring length) of each net;
Based on the approximate wiring length of each net calculated by the wiring length calculation means, a violation net detecting means for detecting a net whose current approximate wiring length exceeds a preliminarily restricted wiring length as a violation net; ,
When blocks belonging to Vaio configuration nets detected by the Vaio Configuration net detecting means is divided by the cut line, based on the general routing information obtained by the general routing unit, Vaio configuration nets belonging to the block Wiring length increase / decrease predicting means for predicting whether the approximate wiring length of the violation net decreases if the cell connected to is moved to the divided block on which side of the cut line,
After moving the cell connected to the violation net toward the divided block where the wiring length is predicted not to decrease or increase by the wiring length increase / decrease prediction means, set the cell as a fixed cell, and then Mini cut method execution means for executing the mini cut method on the block ;
An initial arrangement determining device for an integrated circuit, comprising: Further, based on the approximate wiring length of each net calculated by the wiring length calculating means, a critical net that detects a net whose current approximate wiring length exceeds α% of the preliminarily restricted wiring length as a critical net. Detection means;
A stable net detecting means that detects a net that has been cut by the cut line before the start of the mini-cut method and that has been cut by the cut line even after the start of the execution;
Based on the detection result of the critical net detection means and the detection result of the stable net detection means, all cells connected to the net that is a stable net and also a critical net are made into the same block. the moved, the cell moving means to set all the cells moved to the fixed cellular,
With
2. The integrated circuit initial arrangement determining apparatus according to claim 1, wherein the mini-cut method executing means executes the mini-cut method using the cell arrangement obtained by the processing of the cell moving means as an initial arrangement. 3. The integrated circuit initial arrangement determining apparatus according to claim 2 , wherein α is a value in a range of 70 ≦ α ≦ 80.

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