JP3622287B2 - Digital signal reproduction circuit and reproduction method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital signal reproduction circuit and reproduction method for reproducing a digital signal recorded on, for example, a tape, and more particularly to an equalizer and an automatic adjustment method that can be automatically adjusted.
[0002]
[Prior art]
In digital magnetic recording / reproduction such as a digital VTR, it is known to pass a reproduction signal through an equalizer in order to increase the density of magnetic recording and improve the error rate. Furthermore, a configuration for automatically and optimally controlling equalizer characteristics is also known. It has also been proposed to remove nonlinear distortion using the Viterbi algorithm. Since non-linear distortion at the time of recording depends on the pattern of subsequent data, the conventional linear equalizer cannot sufficiently cope with it, so Viterbi decoding is used.
[0003]
As an automatic equalizer adjustment method, the error rate of the reproduction signal is obtained, a control signal that minimizes the error rate is generated, and the amplitude characteristic and phase characteristic of the equalizer are controlled by this control signal. It is considered. In the method of automatically adjusting the equalizer characteristics based on the error rate, it is necessary to increase the error rate detection accuracy in order to adjust the equalizer characteristics to an optimum one. In general, in a digital VTR or the like, error correction coding is performed as an error countermeasure during recording / reproduction. Therefore, the error rate can be detected from the decoding result of the error correction code, for example, the total number of errors.
[0004]
[Problems to be solved by the invention]
It is considered that the equalization error of the equalizer basically causes a random error. As described above, the method of correcting an error caused by nonlinear distortion by viterbi decoding almost reduces the number of single errors. Therefore, as a result of using Viterbi decoding, the number of single errors used as an evaluation value is reduced in automatic equalizer adjustment.
[0005]
Thus, performing the automatic adjustment of the equalizer while performing Viterbi decoding loses the most effective evaluation value. In other words, the rate of change in the number of C1 single errors with respect to changes in the equalization parameter decreases, and burst errors such as dropouts caused by scratches on magnetic tape and head clogs, which are unrelated to equalization errors. The evaluation value is affected. As a result, the time required for adjustment becomes long, and an equalization error remains.
[0006]
Accordingly, an object of the present invention is to provide a digital signal reproducing circuit capable of automatically adjusting the equalizer characteristics quickly and accurately by turning off the Viterbi decoding operation when automatically adjusting the equalizer characteristics. It is to provide a reproduction method.
[0007]
[Means for Solving the Problems]
According to the present invention, error correction encoded data is reproduced, the reproduced signal is supplied to the Viterbi decoding means via the equalizer, and the output of the Viterbi decoding means is supplied to the error correction coding decoding means. In the digital signal reproduction circuit,
By controlling the equalization parameters for the equalizer, a control means for automatically controlling the characteristics of the equalizer to the optimum one is provided,
The control means controls the equalization parameter based on the evaluation value corresponding to the number of errors obtained by the decoding means,
The Viterbi decoding means is a digital signal reproduction circuit characterized in that the function can be turned on / off by the control means, and the Viterbi decoding means is turned off when the equalization parameter is controlled. The present invention is also a digital signal reproduction method for adjusting the equalizer in this way.
[0008]
The number of errors corrected by the error correction code is used as an evaluation value indicating the quality of the equalization state of the equalizer. In the automatic adjustment state of the equalizer, the Viterbi decoding function is turned off. As a result, error correction is not performed by Viterbi decoding. As a result, the evaluation value is a value that more strongly reflects the equalization error. As a result, the rate of change of the evaluation value with respect to the change of the equalization parameter is increased, and automatic adjustment can be quickly performed. Further, the resolution of the evaluation value is increased and the equalizer can be adjusted accurately.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the present invention. A reproduction signal reproduced from the magnetic tape 2 by the magnetic head 1 is supplied to the equalizer 4 via the reproduction amplifier 3. The equalizer 4 includes an amplitude equalizer 4a and a phase equalizer 4b each having an analog IC configuration. As the equalizer 4, PR4 (Partial Response class 4), an integral equalizer, or the like can be used. As will be described later, the amplitude-to-frequency characteristic of the amplitude equalizer 4a and the phase-to-frequency characteristic of the phase equalizer 4b are controlled by the equalization parameter from the CPU 10. In the case of PR4, a phase linear cosine equalizer is used, the amplitude characteristics are controlled by changing the gain of the upper and lower frequency bands around the Nyquist frequency, and the phase distortion of the electromagnetic conversion system is corrected. Thus, the phase characteristic is changed. When controlling the characteristics of the equalizer 4, it is possible to reduce the equalization error by controlling at least one of the amplitude and the phase.
[0010]
An output signal of the equalizer 4 is supplied to the A / D converter 5 and the PLL 6. The PLL 6 extracts a clock signal from the reproduction signal, and A / D conversion is performed using the extracted clock. The output signal of the A / D converter 5 is supplied to the Viterbi decoder 7. The Viterbi decoder 7 performs Viterbi decoding on the output signal of the A / D converter 5 to output reproduction data in which errors due to nonlinear distortion are corrected. The reproduced data from the Viterbi decoder 7 is supplied to the error correction circuit 8, and the error correction circuit 8 decodes the error correction code. Data reproduced from the error correction circuit 8 is taken out to the output terminal 9.
[0011]
The Viterbi decoder 7 can be controlled on / off by the CPU 10. Briefly, a configuration is adopted in which a path through which the reproduction signal passes through the Viterbi decoder 7 (when on) and a path that bypasses the reproduction signal (when off) are switched by a control signal of the CPU 10.
[0012]
The number of C1 errors is sent from the error correction circuit 8 to the CPU 10. The number of C1 errors is data of the number of errors corrected by the error correction circuit 8 using the C1 code. The C1 code is applied to a plurality of symbols in the recording / reproducing direction (a plurality of symbols in a sync block in the case of a digital VTR described later) among two error correction codes generally used for a product code. Refers to the sign. However, in the present invention, the error correction result of the outer code can be used, and it is not necessary to be a product code. Further, the CPU 10 takes in, for example, the number of C1 errors for 60 tracks and uses it as an evaluation value. In this case, the evaluation value may be formed by performing isolated value (noise component) removal processing, sorting processing, normalization processing, and the like on the C1 error count data fetched from the error correction circuit 8. . The period for obtaining the evaluation value is referred to as an evaluation value period.
[0013]
The number of C1 errors is the total number of C1 errors obtained by adding up all the numbers of errors detected and corrected by the C1 code, or the number of C1 single errors that are single symbol single errors. The total number of C1 errors is the total number of errors including a single symbol single error, a continuous error, and a code error within the evaluation value period (for example, when correction is not performed with the C1 code due to an error of 4 symbols or more). Code errors are counted as 4 errors. The number of C1 single errors is the total number of sync blocks of one symbol error within the evaluation value period. In this case, if two or more consecutive symbols are errors, those that can be corrected by the C1 code may be counted as C1 single errors.
[0014]
Furthermore, the total number of C1 errors and the number of C1 single errors may be switched and used according to the equalization state. Furthermore, when the state of equalization is very bad, the number of detected syncs may be used as the evaluation value. That is, the equalization error may be basically considered as a random error. In this sense, the C1 single error number is most suitable as an evaluation value in a region where the error is relatively small. As the equalization error increases from this state, continuity errors gradually increase, and the number of continuity errors increases from the number of C1 single errors. Therefore, in this region, the continuity error or the total number of C1 errors including the continuity error is the evaluation value with the highest sensitivity. Further, when the equalization error becomes large, the code error becomes almost, and the change in the total number of C1 errors becomes dull. On the other hand, the number of detected sinks that have hardly changed until then rapidly decreases. Therefore, in this region, the number of detected sinks is the highest sensitivity as the evaluation value. Thus, since the evaluation values with high sensitivity differ depending on the state of equalization, it is preferable to switch and use the three types of evaluation values.
[0015]
As will be described later, the CPU 10 receives the number of C1 errors and optimizes the amplitude characteristics and / or phase characteristics of the equalizer 4 (that is, minimizes errors due to equalization errors) by hill-climbing control. Determine equalization parameters. The equalization parameter is, for example, 8-bit data, and this equalization parameter is supplied to the equalizer 4 via a D / A converter as necessary. When controlling the amplitude and phase, it is necessary to determine the amplitude equalization parameter and the phase equalization parameter. When changing one of the amplitude characteristic and the phase characteristic, it is necessary to fix the other. For example, one of the amplitude equalization parameter and the phase equalization parameter is determined first, and then the other is determined. There is another method for optimally determining the equalization parameters. Here, for the sake of simplicity, the determination of the phase equalization parameter and the amplitude equalization parameter will be described without particular distinction.
[0016]
In hill-climbing control, a certain equalization parameter is set, the equalization error (evaluation value) by the equalization parameter before and after that is examined, the direction in which the equalization parameter is changed is determined, and the equalization error is not reduced. This is a control for changing the equalization parameter.
[0017]
FIG. 2 is a flowchart showing the automatic adjustment process of the equalizer 4 performed in the CPU 10 according to the embodiment of the present invention. First, in step ST1, the function (decoding operation) of the Viterbi decoder 7 is turned off. Thereby, the error correction circuit 8 performs error correction of the reproduction data that is not subjected to Viterbi decoding. In the next step ST2, the number of C1 errors is sampled. For example, the number of C1 errors for 60 tracks is read.
[0018]
In the next step ST3, it is determined whether or not the respective evaluation values of the current equalization parameter (initial value) N, the preceding equalization parameter N-1, and the subsequent equalization parameter N + 1 have been determined. If not fixed, the equalization parameter is changed before or after the current equalization parameter (step ST4). Evaluation values are determined for the front-side equalization parameters in the same manner as described above, and evaluation values are also determined for the rear-side equalization parameters. If the evaluation values for the front side and the rear side are determined, the process moves from step ST3 to step ST5. In this step ST5, an equalization parameter for making the evaluation value smaller than the present value is determined based on the magnitude relationship of the evaluation values determined by these three parties. That is, the direction of hill climbing control is determined. Then, the equalization parameter is updated (step ST6).
[0019]
After the update step ST6, step ST7 (sampling of the number of C1 errors similar to step ST2) is performed, and in step ST8, the evaluation values before and after the update are compared in magnitude. If the evaluation value after the update is smaller than the evaluation value before the update, that is, if the equalization error is reduced, the process returns from step ST8 to step ST6 (update equalization parameter), and the parameter is changed again. Update in the same direction. This process is repeated until the evaluation value before update becomes smaller. When the evaluation value before update becomes smaller, the equalization parameter that causes the evaluation value before update is determined as the optimal equalization parameter (step ST9). When the optimum equalization parameter is determined, the hill climbing control is stopped. Then, the function of the Viterbi decoder 7 is turned on (step ST10). This completes the automatic adjustment mode.
[0020]
The above-described automatic adjustment process of the equalizer is applied to both determination of the amplitude equalization parameter and the phase equalization parameter. Usually, the automatic adjustment of the equalizer is performed by using a reference tape when the reproducing apparatus is shipped. However, it can be performed not only at the time of shipment but also during normal reproduction.
[0021]
Next, a rotary head type digital VTR will be described as a specific example of the magnetic reproducing apparatus to which the present invention can be applied. As shown in FIG. 3, diagonal tracks are formed on the tape. T0 and T1 indicate track numbers, and inclined azimuth recording is performed in which the azimuth between adjacent tracks is different. FIG. 4 shows one track. On the track entrance side, a timing block is provided for reliably performing post-recording such as ITI (Insert and Track Information). This is provided in order to accurately position the area when the data written in the subsequent area is rewritten after dubbing.
[0022]
In this example, are converted composite digital color video signal is a luminance signal Y, the color difference signals C _R and component signal consisting of C _B, the compressed component signal by DCT conversion and variable-length code, recorded on the magnetic tape by the rotating head The As a recording method, an SD method (525 lines / 60 Hz, 625 lines / 50 Hz) and an HD method (1125 lines / 60 Hz, 1250 lines / 50 Hz) can be set.
[0023]
As shown in FIG. 5, in the case of the SD system, the number of tracks per frame is 10 tracks (in the case of 525 lines / 60 Hz), or 12 tracks (525 lines / 60 Hz) as shown in FIG. ). Although not shown, in the HD system, the number of tracks per frame is twice that of the SD system, that is, 20 tracks (1125 lines / 60 Hz) or 24 tracks (1250 lines / 50 Hz).
[0024]
As shown in the track format of FIG. 4, audio data, video data, and subcode data are recorded in the head scanning order after the ITI area. The areas for recording video data and audio data are provided with areas for writing auxiliary data (AUX) for recording additional information, respectively. In the AUX, data other than audio and video data such as recording date and time and recording time can be written. The subcode data, AUX, and data recorded in the semiconductor memory built in the cassette have a common format. This format is referred to as a pack structure.
[0025]
The areas in which the audio data, video data, and subcode are recorded are called an audio sector, a video sector, and a subcode sector, respectively. Between these sectors, gaps G1, G2, and G3 in which no data is recorded are arranged. The audio sector includes a preamble (presync block) PR1, a data portion (14 sync blocks), and a postamble PO1 (postsync block).
[0026]
The audio sync block is composed of 90 bytes as shown in FIG. The first 5 bytes are sync and ID data. Audio data (72 bytes) and audio AUX (AAUX) (5 bytes) are included in one sync block. This data is error correction encoded by a product code. That is, inner codes (referred to as C1 codes) are encoded for 77 bytes aligned in the horizontal direction. Specifically, the (85, 77) Reed-Solomon code is used as the C1 code, and an 8-byte C1 (inner code) parity is added. The direction of the C1 code sequence is the data recording / reproducing direction. Further, error correction coding of an outer code (referred to as C2 code) is performed on 9-byte data arranged in the vertical direction. Specifically, a (14, 9) Reed-Solomon code is used as the C2 code, and a 5-byte C2 (outer code) parity is added.
[0027]
The video sector includes a preamble (presync block) PR2, a data portion (149 sync block), and a postamble PO2 (postsync block). FIG. 8 shows the configuration of the video sector. The structure of the preamble and the postamble is the same as that of the audio sector shown in FIG. In the video sync block included in 149 video sectors, one sync block is composed of 90 bytes as in the audio sync block.
[0028]
The first 5 bytes of the sync block are a sync and an ID. The data portion is 77 bytes, and error correction encoding of the product code is performed in the same way as audio data. Specifically, the (85, 77) Reed-Solomon code is used as the C1 code, and the (149, 138) Reed-Solomon code is used as the C2 code. Then, C1 (inner code) parity (8 bytes) and C2 (outer code) parity (11 bytes) are respectively added. Two sync blocks with sync block numbers 19 and 20 and one sync block immediately before the C2 parity are dedicated to video AUX (VAUX), and 77-byte data is used as VAUX data. A central 135 sync block other than VAUX and C2 parity is an area in which video data of a compressed video signal is stored.
[0029]
Further, FIG. 9 shows a configuration of a subcode sector. Unlike the audio sector and video sector, the subcode sector preamble and postamble have no presync and postsync. The subcode sync block has a length of 12 bytes, and the first 5 bytes are a sync and an ID. The subsequent 5 bytes are the data part, and only the C1 code is encoded for the data part. Then, C1 parity (2 bytes) is added. Thus, the product code configuration is not adopted in the subcode. This is because the subcode is mainly for high-speed search, and the C2 parity can hardly be reproduced. Also, the sync length is shortened to 12 bytes for high-speed search up to about 200 times. There are 12 sub-code sync blocks per track.
[0030]
The number of C1 errors in an embodiment of the present invention is the number of errors corrected by the C1 code (the total number of C1 errors or the number of individual C1 errors) in the case of the above-described digital VTR. The C1 error number for is used. Since the C1 code is encoded for each block sync, if the number of block syncs for one symbol error is n1 within the evaluation value period, the number of C1 single errors is n1. If the number of block syncs for 2-symbol error is n2, the number of block syncs for 3-symbol error is n3, and the number of block syncs for code error is n4, the total number of C1 errors is obtained as (n1 + 2n2 + 3n3 + 4n4). .
[0031]
【The invention's effect】
In the present invention, since the Viterbi function is turned off only during the automatic adjustment of the equalization parameter and the improvement of the single symbol error is intentionally stopped, the ratio of the change in the evaluation value with respect to the change in the equalization parameter is increased, and the automatic adjustment is performed. Can be done quickly. In the region where the equalization error is small, the resolution of the evaluation value is improved, and a more optimal equalization parameter can be obtained. When the total number of C1 errors is used as the evaluation value, as a result of Viterbi decoding being turned off, the proportion of the number of C1 single errors in the total number of C1 errors increases. When the number of C1 single errors is used as the evaluation value, as a result of Viterbi decoding being turned off, the C1 single error is a value more strongly reflecting the equalization error.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a flowchart for explaining an example of an automatic adjustment process of an equalizer according to the present invention.
FIG. 3 is a schematic diagram showing a track pattern of a digital VTR to which the present invention can be applied.
FIG. 4 is a schematic diagram for explaining the configuration of one track of a digital VTR.
FIG. 5 is a schematic diagram showing an example of a track pattern when one frame data of a digital VTR to which the present invention can be applied is recorded.
FIG. 6 is a schematic diagram showing another example of a track pattern when one frame of data of a digital VTR to which the present invention can be applied is recorded.
FIG. 7 is a schematic diagram for explaining the configuration of one sector of audio data.
FIG. 8 is a schematic diagram for explaining the configuration of one sector of video data.
FIG. 9 is a schematic diagram for explaining the configuration of one sector of subcode data;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Magnetic head 2 Magnetic tape 4 Equalizer 7 Viterbi decoder 8 Error correction circuit 10 CPU

Claims (6)

A digital signal that reproduces the error-corrected encoded data, supplies the reproduced signal to the Viterbi decoding means via an equalizer, and supplies the output of the Viterbi decoding means to the decoding means of the error correction encoding In the playback circuit,
By controlling equalization parameters for the equalizer, a control means is provided for automatically controlling the characteristics of the equalizer to an optimum one,
The control means controls the equalization parameter based on an evaluation value corresponding to the number of errors obtained by the decoding means,
The Viterbi decoding means can be turned on / off by the control means, and the Viterbi decoding means is turned off when the equalization parameter is controlled. . The error correction encoded data is reproduced, the reproduction signal is equalized by an equalizer, the equalized reproduction signal is Viterbi decoded, and the Viterbi decoded data is decoded by the error correction coding decoding means. In the digital signal reproduction method,
By controlling the equalization parameter based on the evaluation value corresponding to the number of errors obtained by the decoding means, the equalizer characteristics are automatically controlled to be optimal,
The Viterbi decoding means can be turned on / off by the control means, and the Viterbi decoding function is turned off when the equalization parameter is controlled. Oite to claim 1,
The climbing control, a digital signal reproduction circuits, characterized in that so as to control the equalization parameter for the equalizer. Oite to claim 1,
Digital signal reproducing circuits which equalizer is characterized in that the equalizer PR4. In claim 2 ,
The climbing control, a digital signal playback method is characterized in that so as to control the equalization parameter for the equalizer. In claim 2 ,
Digital signal playback method, wherein the equalizer is the equalizer of PR4.

Images