JP3620520B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3620520B2
JP3620520B2 JP2002197052A JP2002197052A JP3620520B2 JP 3620520 B2 JP3620520 B2 JP 3620520B2 JP 2002197052 A JP2002197052 A JP 2002197052A JP 2002197052 A JP2002197052 A JP 2002197052A JP 3620520 B2 JP3620520 B2 JP 3620520B2
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Japan
Prior art keywords
insulating film
film
forming
semiconductor device
plug
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Expired - Fee Related
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JP2002197052A
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Japanese (ja)
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JP2004039964A (en
Inventor
徹 樋野村
雅司 濱中
秀樹 堂下
剛史 原田
恒生 伊倉
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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  • Formation Of Insulating Films (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に関し、特に、タングステンプラグ上に銅配線を形成する配線技術に関するものである。
【０００２】
【従来の技術】
タングステン（Ｗ）プラグ上層に銅（Ｃｕ）配線を形成する場合、Ｗプラグ上に層間絶縁膜を堆積し、その後にリソグラフィー、エッチング、バリア／シード堆積、Ｃｕめっき堆積、Ｃｕ−ＣＭＰ工程を経てＣｕ配線が形成される。従来技術では、Ｗプラグ上層の層間絶縁膜の堆積時に、絶縁膜表面に凹凸が形成され、その凹凸により後工程のＣｕ−ＣＭＰ時にＣｕ研磨残りが発生し、半導体装置の歩留まり低下を引き起こす問題があった。
【０００３】
以下、図３〜図５を参照しながら従来の半導体装置の製造方法について説明する。図３〜図５は従来の半導体装置の製造工程を示す断面図である。また、図６は従来の半導体装置の製造工程の問題点を示す断面図である。
【０００４】
まず、図３（ａ）に示すように、シリコン（Ｓｉ）基板上あるいは下部配線層１上に第１絶縁膜２を堆積した後、リソグラフィー法及びドライエッチング法により第１絶縁膜２にスルーホール３を形成する。
【０００５】
次に、ドライエッチング法あるいはウエットエッチング法によりスルーホール３の底部表面のクリーニングを行った後、図３（ｂ）に示すように、チタン（Ｔｉ）膜４を堆積し、続いて窒化チタン（ＴｉＮ）膜５、Ｗ膜６を順次堆積する。
【０００６】
次に、図３（ｃ）に示すように、第１絶縁膜２上のＴｉ膜４、ＴｉＮ膜５、Ｗ膜６を化学的機械的研磨（ＣＭＰ）法により除去し、Ｗプラグ７を形成する。この時、研磨のばらつきにより第１絶縁膜２の表面にはＷプラグ７の凹凸が発生する。
【０００７】
次に、図４（ａ）に示すように、第１絶縁膜２及びＷプラグ７上に第２絶縁膜８を堆積し、続いて図４（ｂ）に示すように、第２絶縁膜８に対してリソグラフィー法、ドライエッチング法を施すことで配線溝９を形成する。
【０００８】
次に、図４（ｃ）に示すように、第４導電体膜１０、第５導電体膜１１、第６導電体膜１２を順次堆積した後、続いて図５に示すように、ＣＭＰ法により第２絶縁膜８上の第４導電体膜１０、第５導電体膜１１、第６導電体膜１２を除去し、上部配線層１３を形成する。
【０００９】
【発明が解決しようとする課題】
しかしながら上記の製造方法によると、以下のような問題が発生する。
【００１０】
第１絶縁膜２及びＷプラグ７上に第２絶縁膜８を堆積する場合、堆積後の第２絶縁膜８上に、下部に存在するＷプラグに起因した凹凸が生じる。この第２絶縁膜８表面の凹凸が存在すると、後工程で第２絶縁膜８上の第４導電体膜１０、第５導電体膜１１、第６導電体膜１２をＣＭＰ法により除去する際に、この凹凸に第４導電体膜１０、第５導電体膜１１、第６導電体膜１２が除去されずに残存する。これにより、半導体装置の歩留まり低下を引き起こすこととなる。
【００１１】
すなわち、第２絶縁膜８の一実施例として、高密度プラズマを用いた化学的気相成長（ＣＶＤ）法により堆積されるフッ素（Ｆ）添加二酸化シリコン膜を用いた場合、Ｗプラグの電位と第２絶縁膜８堆積時のプラズマの相互作用により、図６（ａ）に示すように、Ｗプラグ７上でのみ第２絶縁膜８の局所的な薄膜化が生じる。このような第２絶縁膜８上の凹部は、図６（ｂ）に示すように、後工程で上部配線層１３を形成する際のＣＭＰ時において、第４導電体膜１０、第５導電体膜１１、第６導電体膜１２が除去されずに残存することとなり、上部配線層１３間の短絡を生じる。
【００１２】
本発明は上記の課題を鑑みて為されたものであり、下部Ｗプラグ上に平坦な層間絶縁膜を堆積し、高歩留まりの上部配線層を形成する半導体装置の製造方法を提供することを目的とする。
【００１３】
【課題を解決するための手段】
上記の目的を達成するために、本発明における半導体装置の製造方法は、半導体基板あるいは下部配線層の上に第１絶縁膜を形成する工程と、第１絶縁膜に半導体基板あるいは下部配線層に接続する金属プラグを形成する工程と、金属プラグが形成された第１絶縁膜上に第２絶縁膜を形成する工程と、第２絶縁膜上に第３絶縁膜を形成する工程と、第３絶縁膜の上あるいは膜中に上部配線層を形成する工程とを備え、第２絶縁膜を形成する工程は高密度プラズマを用いない堆積手法を用い、第３絶縁膜を形成する工程は高密度プラズマを用いた堆積手法を用いることを特徴とする。
【００１４】
この構成により、金属プラグ上に凹凸がなくしかも平坦度の高い絶縁膜を形成することが可能となり、上層配線間の短絡を防ぎ、半導体装置の高歩留まりを実現することができる。
【００１５】
上記の製造方法において、上部配線層を形成する工程は、第３絶縁膜に、または、第２絶縁膜及び第３絶縁膜に配線溝を形成する工程と、配線溝内に導電体膜を埋め込むようにして上部配線層を形成する工程とをさらに包含することが好ましい。
【００１６】
上記の製造方法において、第１絶縁膜、第２絶縁膜及び第３絶縁膜は、二酸化シリコン膜であり、金属プラグは、少なくともタングステンを含むプラグであり、導電体膜は、少なくとも銅膜を含むことが好ましい。
【００１７】
【発明の実施の形態】
以下、本発明の実施形態について図１〜図２に基づいて説明する。図１〜図２は本発明の半導体装置の製造工程を示す断面図である。
【００１８】
まず、図１（ａ）に示すように、トランジスタなどの集積回路素子（図示せず）が形成されたシリコン基板（あるいは下部配線層）１上にＣＶＤ法により、第１絶縁膜２（膜厚約１００〜２０００ｎｍ）を堆積する。この絶縁膜は二酸化シリコン（ＳｉＯ２）膜、フッ素添加二酸化シリコン膜、窒素添加二酸化シリコン膜あるいはホウ素及びリン添加二酸化シリコン膜からなる。この絶縁膜にリソグラフィー法及びドライエッチング法を適用することにより絶縁膜２にスルーホール３を形成する。
【００１９】
次に、図１（ｂ）に示すように、アルゴン（Ａｒ）や水素（Ｈ２）を用いるドライエッチング法によりスルーホール底部のコバルトシリサイド（ＣｏＳｉ２）層（図示せず）の表面の清浄化を行った後、Ｔｉ膜４をスルーホール内側壁及び底部に堆積し、続いてＴｉＮ膜５を前記Ｔｉ膜４上に堆積し、続いてＷ膜６を前記ＴｉＮ膜５上に堆積する。
【００２０】
次に、図１（ｃ）に示すように、第１絶縁膜２上のＴｉ膜４、ＴｉＮ膜５、Ｗ膜６をＣＭＰ法により除去し、Ｗプラグ７を形成する。この時、研磨のばらつきにより第１絶縁膜２の表面にはＷプラグ７の凹凸が発生する。
【００２１】
続いて、図２（ａ）に示すように、第１絶縁膜２上及びＷプラグ７上に第２絶縁膜８を堆積し、続いて第３絶縁膜１４を堆積する。
【００２２】
なお、第２絶縁膜８は、半導体基板１にバイアスを印加しないプラズマＣＶＤ法により堆積された二酸化シリコン膜、もしくはシリコン基板１にバイアスを印加しないプラズマＣＶＤ法により堆積されたフッ素添加二酸化シリコン膜、もしくはシリコン基板１にバイアスを印加しないプラズマＣＶＤ法により堆積された四窒化三シリコン膜、もしくは塗布法により堆積された二酸化シリコン膜等であることが望ましく、その膜厚は５０ｎｍ以上であることが望ましい。また、第３絶縁膜１４は半導体基板１にバイアスを印加する高密度プラズマを用いたＣＶＤ法により堆積されたフッ素添加二酸化シリコン膜であることが望ましい。
【００２３】
ここで、第２絶縁膜８及び第３絶縁膜１４の堆積方法について詳しく説明する。第２絶縁膜８は高密度プラズマを用いない堆積手法であることが望ましく、第３絶縁膜１４は高密度プラズマを用いるＣＶＤ法であることが望ましい。これは以下の理由による。
【００２４】
一般的に、高密度プラズマを用いたＣＶＤ法は、被堆積表面の凹凸形状に関わらず比較的平坦な成膜特性を得ることが可能である。しかしながら本発明のように第２絶縁膜８を堆積する表面上に、第１絶縁膜２と導電性を有するＷプラグ７とが存在するので、Ｗプラグ７の電位と堆積時の高密度プラズマとの相互作用により、Ｗプラグ７上において局所的に第２絶縁膜８の薄膜化が生じる。従って、第２絶縁膜８の堆積方法としては高密度プラズマを用いない堆積手法が望ましい。
【００２５】
上述の理由により、高密度プラズマを用いない堆積手法により第２絶縁膜８を堆積した場合、その表面状態は第１絶縁膜２とＷプラグ７との凹凸形状を反映したものとなる。そのような凹凸を有する第２絶縁膜８の表面に対して、高密度プラズマを用いるＣＶＤ法を用いて第３絶縁膜１４を堆積すると、高密度プラズマを用いるＣＶＤ法が有する表面平坦化の特性により、被堆積表面の凹凸に関わらず、平坦な表面を得ることができる。また、この際、先に堆積した第２絶縁膜８によりＷプラグ７と高密度プラズマとは絶縁されているため、Ｗプラグ７上での第３絶縁膜１４の局所的な薄膜化は生じない。
【００２６】
以上のような理由から、第２絶縁膜８は高密度プラズマを用いない堆積手法で、第３絶縁膜１４は高密度プラズマを用いるＣＶＤ法により堆積することが望ましい。
【００２７】
次に、図２（ｂ）に示すように、第２絶縁膜８及び第３絶縁膜１４に対して、リソグラフィー法、ドライエッチング法を行うことで第２絶縁膜８及び第３絶縁膜１４に配線溝９を形成し、続いて第４導電体膜１０、第５導電体膜１１、第６導電体膜１２を堆積する。
【００２８】
なお、第４導電体膜はＴａＮ膜もしくはＴａ／ＴａＮの積層膜であり、第５導電体膜および第６導電体膜はＣｕ膜であることが望ましい。
【００２９】
次に、図２（ｃ）に示すように、ＣＭＰ法により第３絶縁膜１４上の第４導電体膜１０、第５導電体膜１１、第６導電体膜１２を除去し、上部配線層１３を形成して、本実施形態の半導体装置は完成する。
【００３０】
【発明の効果】
以上説明したように、本発明における半導体装置の製造方法を用いれば、Ｗプラグ上に凹凸がなくしかも平坦度の高い絶縁膜を形成することが可能となり、上層配線間の短絡を防ぎ、半導体装置の高歩留まりを実現することができる。
【図面の簡単な説明】
【図１】本発明による半導体装置の製造工程を示す断面図
【図２】本発明による半導体装置の製造工程を示す断面図
【図３】従来の半導体装置の製造工程を示す断面図
【図４】従来の半導体装置の製造工程を示す断面図
【図５】従来の半導体装置の製造工程を示す断面図
【図６】従来の半導体装置の製造工程の問題点を示す断面図
【符号の説明】
１ 半導体基板（あるいは下部配線層）
２ 第１絶縁膜
３ スルーホール
４ チタン膜
５ 窒化チタン膜
６ タングステン膜
７ タングステンプラグ
８ 第２絶縁膜
９ 配線溝
１０ 第４金属膜
１１ 第５金属膜
１２ 第６金属膜
１３ 上部配線層
１４ 第３絶縁膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a wiring technique for forming a copper wiring on a tungsten plug.
[0002]
[Prior art]
When a copper (Cu) wiring is formed on a tungsten (W) plug upper layer, an interlayer insulating film is deposited on the W plug, and then Cu, through lithography, etching, barrier / seed deposition, Cu plating deposition, and Cu-CMP steps. A wiring is formed. In the prior art, when the interlayer insulating film on the upper layer of the W plug is deposited, unevenness is formed on the surface of the insulating film, and due to the unevenness, Cu polishing residue is generated during Cu-CMP in the subsequent process, which causes a decrease in yield of the semiconductor device. there were.
[0003]
Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to FIGS. 3 to 5 are cross-sectional views showing a manufacturing process of a conventional semiconductor device. FIG. 6 is a cross-sectional view showing problems in the manufacturing process of a conventional semiconductor device.
[0004]
First, as shown in FIG. 3A, after depositing a first insulating film 2 on a silicon (Si) substrate or a lower wiring layer 1, a through hole is formed in the first insulating film 2 by a lithography method and a dry etching method. 3 is formed.
[0005]
Next, after the bottom surface of the through-hole 3 is cleaned by a dry etching method or a wet etching method, a titanium (Ti) film 4 is deposited as shown in FIG. ) A film 5 and a W film 6 are sequentially deposited.
[0006]
Next, as shown in FIG. 3C, the Ti film 4, TiN film 5 and W film 6 on the first insulating film 2 are removed by a chemical mechanical polishing (CMP) method to form a W plug 7. To do. At this time, unevenness of the W plug 7 is generated on the surface of the first insulating film 2 due to variations in polishing.
[0007]
Next, as shown in FIG. 4A, a second insulating film 8 is deposited on the first insulating film 2 and the W plug 7, and then, as shown in FIG. 4B, the second insulating film 8 is deposited. A wiring trench 9 is formed by applying a lithography method and a dry etching method.
[0008]
Next, as shown in FIG. 4C, a fourth conductor film 10, a fifth conductor film 11, and a sixth conductor film 12 are sequentially deposited, and then, as shown in FIG. Thus, the fourth conductor film 10, the fifth conductor film 11, and the sixth conductor film 12 on the second insulating film 8 are removed, and the upper wiring layer 13 is formed.
[0009]
[Problems to be solved by the invention]
However, according to the above manufacturing method, the following problems occur.
[0010]
In the case where the second insulating film 8 is deposited on the first insulating film 2 and the W plug 7, irregularities due to the W plug existing below are formed on the second insulating film 8 after the deposition. If the unevenness on the surface of the second insulating film 8 exists, when the fourth conductor film 10, the fifth conductor film 11, and the sixth conductor film 12 on the second insulating film 8 are removed by a CMP method in a later step. In addition, the fourth conductor film 10, the fifth conductor film 11, and the sixth conductor film 12 remain on the unevenness without being removed. As a result, the yield of the semiconductor device is reduced.
[0011]
That is, as an example of the second insulating film 8, when a fluorine (F) -added silicon dioxide film deposited by a chemical vapor deposition (CVD) method using high-density plasma is used, the potential of the W plug is Due to the interaction of the plasma during the deposition of the second insulating film 8, the second insulating film 8 is locally thinned only on the W plug 7, as shown in FIG. Such recesses on the second insulating film 8 are formed in the fourth conductor film 10 and the fifth conductor at the time of CMP when forming the upper wiring layer 13 in a later step, as shown in FIG. 6B. The film 11 and the sixth conductor film 12 remain without being removed, causing a short circuit between the upper wiring layers 13.
[0012]
The present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device in which a flat interlayer insulating film is deposited on a lower W plug to form an upper wiring layer having a high yield. And
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a semiconductor substrate or a lower wiring layer, and a step of forming a semiconductor substrate or a lower wiring layer on the first insulating film. Forming a metal plug to be connected; forming a second insulating film on the first insulating film on which the metal plug is formed; forming a third insulating film on the second insulating film; A step of forming an upper wiring layer on or in the insulating film, the step of forming the second insulating film uses a deposition method that does not use high-density plasma, and the step of forming the third insulating film has a high density. A deposition method using plasma is used.
[0014]
With this configuration, it is possible to form an insulating film having no unevenness and high flatness on the metal plug, preventing a short circuit between upper layer wirings, and realizing a high yield of the semiconductor device.
[0015]
In the above manufacturing method, the step of forming the upper wiring layer includes the step of forming a wiring groove in the third insulating film or in the second insulating film and the third insulating film, and embedding a conductor film in the wiring groove. Thus, it is preferable to further include a step of forming the upper wiring layer.
[0016]
In the above manufacturing method, the first insulating film, the second insulating film, and the third insulating film are silicon dioxide films, the metal plug is a plug containing at least tungsten, and the conductor film contains at least a copper film. It is preferable.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS. 1 to 2 are sectional views showing a manufacturing process of a semiconductor device of the present invention.
[0018]
First, as shown in FIG. 1A, a first insulating film 2 (film thickness) is formed by CVD on a silicon substrate (or a lower wiring layer) 1 on which an integrated circuit element (not shown) such as a transistor is formed. About 100-2000 nm). This insulating film is made of a silicon dioxide (SiO 2 ) film, a fluorine-added silicon dioxide film, a nitrogen-added silicon dioxide film, or a boron- and phosphorus-added silicon dioxide film. Through holes 3 are formed in the insulating film 2 by applying a lithography method and a dry etching method to the insulating film.
[0019]
Next, as shown in FIG. 1B, the surface of the cobalt silicide (CoSi 2 ) layer (not shown) at the bottom of the through hole is cleaned by a dry etching method using argon (Ar) or hydrogen (H 2 ). Then, the Ti film 4 is deposited on the inner side wall and the bottom of the through hole, the TiN film 5 is deposited on the Ti film 4, and the W film 6 is deposited on the TiN film 5.
[0020]
Next, as shown in FIG. 1C, the Ti film 4, TiN film 5, and W film 6 on the first insulating film 2 are removed by CMP to form a W plug 7. At this time, unevenness of the W plug 7 is generated on the surface of the first insulating film 2 due to variations in polishing.
[0021]
Subsequently, as shown in FIG. 2A, a second insulating film 8 is deposited on the first insulating film 2 and the W plug 7, and then a third insulating film 14 is deposited.
[0022]
The second insulating film 8 is a silicon dioxide film deposited by a plasma CVD method without applying a bias to the semiconductor substrate 1, or a fluorine-added silicon dioxide film deposited by a plasma CVD method without applying a bias to the silicon substrate 1, Alternatively, a silicon tetranitride film deposited by a plasma CVD method without applying a bias to the silicon substrate 1 or a silicon dioxide film deposited by a coating method is desirable, and the film thickness is desirably 50 nm or more. . The third insulating film 14 is preferably a fluorine-added silicon dioxide film deposited by a CVD method using high-density plasma that applies a bias to the semiconductor substrate 1.
[0023]
Here, the deposition method of the second insulating film 8 and the third insulating film 14 will be described in detail. The second insulating film 8 is preferably a deposition method that does not use high-density plasma, and the third insulating film 14 is preferably a CVD method that uses high-density plasma. This is due to the following reason.
[0024]
In general, a CVD method using high-density plasma can obtain a relatively flat film formation characteristic regardless of the uneven shape of the surface to be deposited. However, since the first insulating film 2 and the conductive W plug 7 are present on the surface on which the second insulating film 8 is deposited as in the present invention, the potential of the W plug 7 and the high-density plasma during deposition Due to this interaction, the second insulating film 8 is locally thinned on the W plug 7. Therefore, a deposition method that does not use high-density plasma is desirable as a method for depositing the second insulating film 8.
[0025]
For the above-described reason, when the second insulating film 8 is deposited by a deposition method that does not use high-density plasma, the surface state reflects the uneven shape of the first insulating film 2 and the W plug 7. When the third insulating film 14 is deposited on the surface of the second insulating film 8 having such irregularities by using the CVD method using high-density plasma, the surface flattening characteristics of the CVD method using high-density plasma are included. Thus, a flat surface can be obtained regardless of the unevenness of the surface to be deposited. At this time, since the W plug 7 and the high-density plasma are insulated from each other by the second insulating film 8 deposited previously, the local thinning of the third insulating film 14 on the W plug 7 does not occur. .
[0026]
For the above reasons, it is desirable that the second insulating film 8 is deposited by a deposition method not using high-density plasma, and the third insulating film 14 is deposited by a CVD method using high-density plasma.
[0027]
Next, as shown in FIG. 2B, the second insulating film 8 and the third insulating film 14 are formed on the second insulating film 8 and the third insulating film 14 by performing a lithography method and a dry etching method. A wiring trench 9 is formed, and then a fourth conductor film 10, a fifth conductor film 11, and a sixth conductor film 12 are deposited.
[0028]
The fourth conductor film is preferably a TaN film or a Ta / TaN laminated film, and the fifth conductor film and the sixth conductor film are preferably Cu films.
[0029]
Next, as shown in FIG. 2C, the fourth conductor film 10, the fifth conductor film 11, and the sixth conductor film 12 on the third insulating film 14 are removed by the CMP method, and the upper wiring layer is removed. 13 is formed, and the semiconductor device of this embodiment is completed.
[0030]
【The invention's effect】
As described above, by using the method for manufacturing a semiconductor device according to the present invention, it is possible to form an insulating film having no unevenness and high flatness on the W plug, thereby preventing a short circuit between the upper layer wirings. High yield can be realized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the present invention. FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the present invention. FIG. 5 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device. FIG. 6 is a cross-sectional view showing a problem in the manufacturing process of a conventional semiconductor device.
1 Semiconductor substrate (or lower wiring layer)
2 First insulating film 3 Through hole 4 Titanium film 5 Titanium nitride film 6 Tungsten film 7 Tungsten plug 8 Second insulating film 9 Wiring groove 10 Fourth metal film 11 Fifth metal film 12 Sixth metal film 13 Upper wiring layer 14 3 Insulating film

Claims (3)

半導体基板あるいは下部配線層の上に第１絶縁膜を形成する工程と、
前記第１絶縁膜に前記半導体基板あるいは下部配線層に接続する金属プラグを形成する工程と、
前記金属プラグが形成された第１絶縁膜上に層間絶縁膜を形成する工程と、
前記層間絶縁膜中に前記金属プラグに接続する上部配線層を形成する工程とを備え、
前記層間絶縁膜を形成する工程は、
前記半導体基板にバイアスを印加しないプラズマＣＶＤ法もしくは塗布法により前記第１絶縁膜上に第２絶縁膜を形成する工程と、
前記半導体基板にバイアスを印加する高密度プラズマを用いたＣＶＤ法により前記第２絶縁膜上に第３絶縁膜を形成する工程とからなり、
前記第２絶縁膜を形成する工程において、前記第２絶縁膜を堆積する表面上に前記第１絶縁膜と前記金属プラグとが存在し、前記第１絶縁膜の表面に前記金属プラグの凹凸が生じていることを特徴とする半導体装置の製造方法。Forming a first insulating film on the semiconductor substrate or the lower wiring layer;
Forming a metal plug connected to the semiconductor substrate or the lower wiring layer in the first insulating film;
Forming an interlayer insulating film on the first insulating film on which the metal plug is formed;
Forming an upper wiring layer connected to the metal plug in the interlayer insulating film ,
The step of forming the interlayer insulating film includes:
Forming a second insulating film on the first insulating film by plasma CVD or coating without applying a bias to the semiconductor substrate;
Forming a third insulating film on the second insulating film by a CVD method using high-density plasma for applying a bias to the semiconductor substrate,
In the step of forming the second insulating film, the first insulating film and the metal plug are present on a surface on which the second insulating film is deposited, and unevenness of the metal plug is formed on the surface of the first insulating film. A method of manufacturing a semiconductor device, wherein the semiconductor device is generated . 前記上部配線層を形成する工程は、
前記層間絶縁膜に配線溝を形成する工程と、
前記配線溝内に導電体膜を埋め込むようにして前記上部配線層を形成する工程とをさらに包含し、
前記第１絶縁膜、前記第２絶縁膜及び前記第３絶縁膜は、二酸化シリコン膜であり、
前記金属プラグは、少なくともタングステンを含むプラグであり、
前記導電体膜は、少なくとも銅膜を含むことを特徴とする請求項１に記載の半導体装置の製造方法。The step of forming the upper wiring layer includes:
Forming a wiring trench in the interlayer insulating film ;
Further includes a step of forming the upper wiring layer so as to bury the conductive film on the wiring groove,
The first insulating film, the second insulating film, and the third insulating film are silicon dioxide films,
The metal plug is a plug containing at least tungsten;
The method of manufacturing a semiconductor device according to claim 1, wherein the conductor film includes at least a copper film . 前記第２絶縁膜は、前記金属プラグの電位と堆積時の前記高密度プラズマとの相互作用を防ぐことを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the second insulating film prevents an interaction between the potential of the metal plug and the high-density plasma during deposition .
JP2002197052A 2002-07-05 2002-07-05 Manufacturing method of semiconductor device Expired - Fee Related JP3620520B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9780113B2 (en) 2015-02-10 2017-10-03 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9780113B2 (en) 2015-02-10 2017-10-03 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device including a first ILD with sloped surface on a stacked structure and a second ILD on the first ILD

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