JP3619861B2 - Pipeline information output method, output device therefor, and computer-readable recording medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pipeline information output method and the like, and in particular, by outputting a group of instructions for a pipeline portion when a source program is translated by a combiner or an assembler, a user can The source program can be tuned after knowing in advance the type of each instruction used in the pipeline processing. In this specification, “source program” is simply referred to as “program” as necessary.
[0002]
In general, in order to improve the execution performance of a program, it is desirable for the user to perform the tuning operation of the program more efficiently while confirming the translated content of the source program. The target part of the pipeline processing of the program is designed to meet this demand.
[0003]
[Prior art]
Conventionally, the user has checked the output information indicating the status of optimization and vectorization at the time of translation of the source program, and then considered the hardware characteristics, and the pipeline processing part such as vector calculation Tuning of the source program including
[0004]
That is, pipeline information indicating the type / order of instructions used in pipeline processing, the number of instructions, the number of operations in the pipeline, etc. has not been provided to the user who performs the tuning execution. .
[0005]
[Problems to be solved by the invention]
As described above, the conventional program tuning has a problem in that work efficiency is poor because the pipeline information is not used as the determination material.
[0006]
Therefore, in the present invention, pipeline information at the time of source program translation is obtained and output so that the user can refer to the output contents to improve the efficiency of program tuning, and the object program The purpose is to improve execution performance.
[0007]
[Means for Solving the Problems]
The present invention solves this problem as follows.
Pipeline information indicating the type, order, and number of instructions used in pipeline processing for a group of instructions generated by translation of the target part using a computer when translating the source program including the target part for pipeline processing And displays a screen showing the processing procedure indicated by the pipeline information in time series for each type of instruction.
[0008]
In the present invention, pipeline information relating to a group of pipeline processing instructions at the time of source program translation is output, so that the user can efficiently execute program tuning with reference to the output contents.
[0009]
The present invention provides a pipeline information output method and output apparatus comprising such a solution, and a computer-readable program storage storing a program for causing a computer to execute pipeline information output processing. Targeted at medium.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIGS.
[0011]
FIG. 1 is an explanatory view showing a source program and a screen display example of pipeline information corresponding to the source program. 1 is a source program, and 2 is a screen displayed when the source program 1 is compiled. Pipeline information is shown.
[0012]
FIG. 2 is an explanatory diagram showing the concept of pipeline processing for the source program of FIG. 1, wherein 11 is a memory, 12 is a load / store pipeline (L / ST pipeline), 13 vector registers, and 14 is A multiplication / addition pipeline (M & A pipeline), 15 is a division pipeline, and 16 is an addition pipeline.
[0013]
Source program 1 is for arrays a, b, c, d, e, and f.
a (i) = (b (i) + c (i) × d (i)) ÷ e (i) + f (i)
It consists of a total of 1024 loop calculations.
[0014]
Pipeline information 2 is
-Vector load instruction L, vector store instruction S (L / ST pipeline)
-Vector multiplication instruction M, vector addition instruction A (M & A pipeline)
-Vector division instruction (DIV pipeline)
-Vector mask instruction (MASK pipeline)
It is made up of.
[0015]
The processing procedure indicated by the pipeline information 2 is as follows:
(1) Load the array b from the memory 11 into the vector register 13 via the load / store pipeline 12;
(2) Load the array c from the memory 11 to the vector register 13 via the load / store pipeline 12;
(3) The array d is loaded from the memory 11 to the vector register 13 via the load / store pipeline 12, and
(4) Multiply the array c and the array d of the vector register 13 by the multiplication / addition pipeline 14;
(5) In the multiplication / addition pipeline 14, add the array b of the vector register 13 and the multiplication result of (4),
(6) The array e is loaded from the memory 11 to the vector register 13 via the load / store pipeline 12, and
(7) The array f is loaded from the memory 11 to the vector register 13 via the load / store pipeline 12, and
(8) In the division pipeline 15, divide the addition result of (5) by the array e,
(9) The addition pipeline 16 adds the array f and the result of (8),
(10) Store the addition result of (9) in the array a of the vector register 13.
It has become.
[0016]
At this time,
Allocation / multiplication / addition of the vector load instruction (4) to the load / store pipeline 12 is performed at the same timing.
[0017]
Also,
-Allocation of vector load instruction (7) to load / store pipeline 12-Allocation of vector division instruction (8) to division pipeline 15-(9) to addition pipeline 16 All vector addition instructions are assigned at the same timing.
[0018]
Hardware (arithmetic circuit) corresponding to each pipeline to which a vector instruction is assigned at the same timing is controlled so as to execute the instruction contents after receiving data necessary for processing there. .
[0019]
For example, the arithmetic circuit corresponding to the addition pipeline 16 receives the output of the division pipeline 15 and the array f loaded into the vector register 13 by the vector load instruction (7) above, Addition processing is executed.
[0020]
The user can confirm from the pipeline information 2 in FIG.
・ Multiplication instructions and addition instructions exist individually, and compound instruction U related to multiplication and addition is not generated. ・ Total number of instructions is 10 (load instruction is 5, store instruction is 1, multiplication instruction is 1. Because the add instruction is 2, the divide instruction is 1), there are few operations in the pipeline.
[0021]
Based on the above confirmation contents, the following tuning items can be extracted.
(1) Designate an option to use the compound instruction U to the command processor.
(2) An optimization control line using the compound instruction U is added to the source program.
(3) Modify the source program so that the number of loop operations is halved, and double the number of operations in the pipeline.
[0022]
The tuning items (1) and (2) above use the optimization function of the compiler. Further, the tuning item (1) does not target the correction of the source program, and the tuning items (2) and (3) described above target the correction of the source program.
[0023]
FIG. 3 shows a source program 3 in which the optimization control line using the compound instruction U is designated in the DO loop of FIG. This corresponds to the tuning item (2) above, and the optimization control line is “! Ocl fmadd”.
[0024]
FIG. 4 shows pipeline information 4 when the tuning items (1) and (2) are dealt with.
[0025]
The pipeline information 4 in FIG.
-When the source program 1 is translated, a compound instruction U of a vector multiplication instruction M and a vector addition instruction A is used,
-As a result, the number of vector instructions is one less than that of the pipeline information of FIG. 1, that is, the vector operation processing is completed earlier by one instruction as a whole,
Is shown.
[0026]
At this time,
Allocation / multiplication / addition of the compound load U to the load / store pipeline 12 is performed at the same timing.
[0027]
Also,
-Allocation of vector load instruction (array f) to load / store pipeline 12-Allocation of vector division instruction to division pipeline 15-Allocation of vector addition instruction to addition pipeline 16 at the same timing Is called.
[0028]
The processing procedure indicated by the pipeline information 4 is the same as the above (1) to (10), and related operations between pipelines in which a plurality of vector instructions are allocated at the same timing are the same as in FIG. Be controlled.
[0029]
FIG. 5 shows a source program 5 in which the number of repetitions of the DO loop of FIG. 1 is halved and a screen display example of pipeline information 6 corresponding thereto. This corresponds to the tuning item (3) above.
[0030]
The processing procedure indicated by the pipeline information 6 in FIG.
First, the processing of the above (1) to (10) relating to the first half of the source program 5, and then the processing of (1) to (10) relating to the second half of the source program 5.
[0031]
The pipeline information 6 in FIG. 5 is compared with that in FIG.
・ The number of repetitions of the DO loop is half “512”,
-The number of vector instructions is twice "20",
Is shown.
[0032]
In the case of the above item (3), the number of DO loop repetitions is reduced to shorten the processing time per instruction, and the number of instructions is increased to facilitate instruction scheduling in the pipeline. As a result, the execution performance of the program is improved.
[0033]
FIG. 6 is an explanatory diagram showing the system configuration of the compiler.
21 is a source program 22, a compiler 23 is a source program 24, an input unit 24 is a lexical analysis, syntax analysis, and semantic analysis of the input source program. An analysis unit 25 is an internal representation of the computer. The intermediate language generation unit 26 that generates the intermediate language represented by (2) has a function of creating pipeline information, for example, by adding a change for improving processing efficiency by eliminating the redundancy of operations. The pipeline scheduling unit 28 is a code generation unit 29 is a pipeline information output function, the lister unit 30 is a buffer, etc. The storage unit 31 is the output of the compiler 22 The object program 32 is the pipeline information display unit Respectively. The distance between the processing unit corresponding to the compiler 22 and the display unit 32 is arbitrary.
[0034]
Among the above components,
The pipeline scheduling unit 27 corresponds to “means for obtaining pipeline information indicating the type, order, and number of instructions used in pipeline processing for an instruction group generated by translation of the target part ”;
The display unit 32 and the lister unit 29 correspond to “an output unit that displays a screen showing the processing procedure indicated by the pipeline information in time series for each type of instruction” .
[0035]
FIG. 7 is an explanatory diagram showing a procedure for outputting pipeline information, and the contents thereof are as follows.
(S1) The input unit 23 determines whether or not the user designates the output option of the pipeline information to the command processor. If “YES”, the process proceeds to the next step, and if “NO”, the output process is performed. Exit.
(S2) The pipeline scheduling unit 27 determines whether or not the input source program 21 is intended for vector operation. If “YES”, the process proceeds to the next step, and if “NO”, End the output process.
(S3) The pipeline scheduling unit 27 stores the processor information (for example, the sequence of the analyzed instructions) for the vector operation part of the source program 21 in the storage unit 30, and proceeds to the next step.
(S4) The lister unit 29 determines whether the processor information is stored in the storage unit 30. If “YES”, the process proceeds to the next step, and if “NO”, the output process ends.
(S5) The lister unit 29 outputs the processor information to the storage means 30, displays it on the display means 32, and ends the output process.
[0036]
Whether or not the processor information is stored in the storage unit 30 in step (S4) is based on the operation content of the lister unit 29.
[0037]
For example, the lister unit 29 has a function of rerunning after the compilation process is interrupted, and processing of the lister unit 29 for the storage unit when the pipeline information is not stored in the storage unit 30 at the time of the rerunning. This is to efficiently perform the above.
[0038]
FIG. 8 is an explanatory diagram showing an outline of a computer system that reads and executes a program from a computer-readable recording medium. , 42 is a display for displaying an image in accordance with an instruction from the main body 41, 43 is a display screen, 44 is a keyboard for inputting various information to the computer system 4, and 45 is an arbitrary screen on the display screen 43. Mouse for specifying the position, 46 is an external database (line-destination memory such as DASD), 47 is a modem for accessing the external database 46, 48 is a CD-ROM or floppy disk, etc. Each of the portable recording media is shown.
[0039]
As a recording medium for storing the program,
・ Program provider's database 46 (line destination memory)
・ Portable recording medium 48
Any of a RAM, a hard disk, and the like on the main unit 41 side may be used, and the program is loaded into the main unit 41 and executed on the main memory.
[0040]
【The invention's effect】
In this way, the present invention outputs the pipeline information related to the instruction group of the pipeline processing at the time of the source program translation, so that the user can efficiently perform the program tuning while referring to the output contents. It can be executed and the execution performance of the object program can be improved.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a source program and a screen display example of corresponding pipeline information according to the present invention.
FIG. 2 is an explanatory diagram showing the concept of pipeline processing for the source program of FIG. 1 according to the present invention.
FIG. 3 is an explanatory diagram showing a source program according to the present invention in which an optimization control line using a compound instruction U is designated in the DO loop of FIG. 1;
FIG. 4 is an explanatory diagram showing pipeline information when dealing with the tuning items (1) and (2) according to the present invention.
FIG. 5 is an explanatory diagram showing a source program according to the present invention in which the number of repetitions of the DO loop of FIG. 1 is halved and a screen display example of corresponding pipeline information.
FIG. 6 is an explanatory diagram showing a system configuration of a compiler according to the present invention.
FIG. 7 is an explanatory diagram illustrating a procedure for outputting pipeline information according to the present invention.
FIG. 8 is an explanatory diagram showing an outline of a computer system for reading and executing a program from a computer-readable recording medium according to the present invention.
[Explanation of symbols]
1: Source program 2: Source program 1 pipeline information 3: Source program 4 that addresses the tuning item (2): Addresses the tuning items (1) and (2) Pipeline information 5: Source program 6 corresponding to the tuning item (3): Pipeline information 11 of the source program 5: Memory 12: Load / store pipeline (L / ST pipeline)
13: Vector register 14: Multiplication / addition pipeline (M & A pipeline)
15: Division pipeline 16: Addition pipeline 21: Source program 22: Compiler 23: Source program input unit 24: Analysis unit 25: Intermediate language generation unit 26: Optimization unit 27: Pipeline scheduling Unit 28: Code generation unit 29: Lister unit 30 having pipeline information output function 30: Storage unit 31 such as a buffer 31: Object program 32: Display unit 4: Computer system 41: Built-in CPU, disk drive device, etc. Main unit 42: display 43: display screen 44: keyboard 45: mouse 46: external database (line-destination memory such as DASD)
47: Modem 48: Portable recording medium such as a CD-ROM or floppy disk

Claims (3)

When translating the source program including the target part of the pipeline processing,
Using a computer
A step of the type of instructions used for instructions that are generated by the target portion of the translation in the pipeline processing, order, Ru seek pipeline information indicating the number of instructions,
Displaying a screen showing a processing procedure indicated by the pipeline information in time series for each type of instruction;
A method for outputting pipeline information, characterized in that: In a translation apparatus for a source program including a target part of pipeline processing,
Means for obtaining pipeline information indicating the type, order, and number of instructions used in pipeline processing for an instruction group generated by translation of the target portion;
Output means for displaying a screen for understanding the processing procedure indicated by the pipeline information in time series for each type of instruction;
An apparatus for outputting pipeline information. A recording medium storing a translation program for a source program including a target part of pipeline processing,
The translation program, the type of instructions used in the pipeline processing with the instructions generated by the target portion of the translation, the order, asking the pipeline information indicating the number of instructions, wherein the time series for each type of instruction This is to make a computer realize the function of displaying a screen that shows the processing procedure indicated by the pipeline information .
A computer-readable recording medium.

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