JP3611300B2 - Signal generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal generation apparatus used for generating a test simulation signal for testing the performance of an array antenna apparatus.
[0002]
[Prior art]
In wireless communication systems targeting mobile objects such as humans and vehicles, array antenna devices are used for purposes such as detecting the direction of the mobile object in communication and directing the beam toward the mobile object to be communicated. Is done. In this type of array antenna apparatus, a plurality of antenna elements are arranged in a space in a predetermined arrangement, and the phase and amplitude (complex amplitude) of the received signal of each antenna element, the directivity of each antenna element, and each antenna element The direction of arrival of radio waves is detected from the positional relationship between the two. In this type of array antenna apparatus, the radio wave can be transmitted in a specific direction by controlling the phase of the radio wave transmitted from each antenna element. As a typical example of such an array antenna apparatus, about five antenna elements are arranged at equal intervals on a straight line or on a circumference.
[0003]
When manufacturing and developing the array antenna device, a test signal generator for testing is used rather than actually receiving radio waves outdoors in terms of economy. That is, in order to simulate the reception signal output from each antenna element, about five signal generation systems are formed, and signals having different phases and amplitudes are generated from each signal generation system.
[0004]
Conventionally, as this kind of simulation signal generator for testing, an apparatus having a configuration as shown in FIG. 4 has been used. A test sine wave signal generated by a signal generator is divided into a plurality of components by a signal distributor, and a desired delay amount and amplitude are given to each by an analog delay circuit and an amplifier, and a test simulation is performed. It is output from each output terminal as a signal.
[0005]
As another conventional apparatus, one having the configuration shown in FIG. 5 is also known. In this conventional apparatus, an analog test signal output from a signal generator is once converted into a digital signal by an A / D converter. This digital signal is divided into a plurality of components by a signal distributor, and each component is supplied to the D / A conversion circuit after receiving a delay when passing through the FIFO memory. The test signal restored to the analog signal is output from each output terminal after the amplitude is adjusted by the amplifier. The delay amount of each FIFO memory is changed by changing the number of column stages.
[0006]
[Problems to be solved by the invention]
In the conventional apparatus having the configuration shown in FIG. 4, an analog delay circuit is realized using a delay line or a delay element. In such a delay circuit, it is necessary to change the delay amount over a wide range according to the frequency of the test signal to be generated and the configuration of the array antenna to be tested. For this reason, it is necessary to prepare a large number of delay lines and delay elements, which causes a problem that the apparatus becomes complicated and expensive.
[0007]
Further, unlike the conventional device shown in FIG. 4, the conventional device having the configuration shown in FIG. 5 has a simple configuration of the delay circuit implemented in digital form. However, it is difficult to realize a high-precision and high-frequency A / D converter for once converting an analog signal generated by a signal generator into a digital signal. Has a problem that it is limited by the performance of the A / D converter. Actually, in the case of an A / D converter with 14-bit accuracy, the maximum operable frequency is limited to several tens of MHz. A D / A converter that operates at a high frequency of several hundred MHz with 14-bit accuracy can be realized. Further, as pointed out in Japanese Patent Laid-Open No. 11-145917, the signal generator shown in FIG. 5 has a problem that the memory amount of the FIFO increases when the delay resolution is increased.
[0008]
[Means for Solving the Problems]
The signal generator of the present invention that solves the above-described problems of the prior art includes a plurality of signal generation channels each including a direct digital synthesizer that generates a sine wave signal having a controllable frequency, phase, and amplitude, and each signal generation channel By controlling each direct digital synthesizer, the control unit sets the phase and amplitude relationship between each sine wave signal output from each signal generation channel to a desired one, so as to achieve a high frequency. The test sine wave signal can be generated easily and inexpensively.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
According to one preferred embodiment of the present invention, the control unit includes a feedback system including signal detection means for detecting a phase and amplitude relationship between each sine wave signal output from each signal generation channel. By adopting the configuration, further cost reduction of the apparatus is realized.
[0010]
According to another preferred embodiment of the present invention, the signal detection means selects a signal output from a specific one of the signal generation channels as a reference signal, and all the remaining signal selection means. Second signal selection means for sequentially selecting a signal output from one of the signal generation channels as a signal to be compared, and the phase and amplitude between the signals selected by these first and second selection means By adopting a relative system configuration comprising a comparison means for comparing with each other, the device can be realized at low cost by using inexpensive elements and circuits whose requirements relating to operational stability are moderate.
[0011]
According to still another preferred embodiment of the present invention, the sine wave signal output from each signal generation channel is used as a signal for simulating the reception signal output from the array antenna element. Then, a plurality of signal generation units composed of such signal generation channels are installed, the outputs of the corresponding signal generation channels included in each signal generation unit are combined, and the combined signal is transmitted to each array antenna element. Necessary for testing when radio waves from multiple transmission sources arrive at the array antenna under test by simulating the received signal output from the signal source, or when radio waves arrive via multipath from a single transmission source It is configured to simulate a received signal of a simple array antenna.
[0012]
【Example】
FIG. 1 is a block diagram showing the configuration of a signal generator according to an embodiment of the present invention. This signal generator is used to test the performance of an array antenna composed of five antenna elements, and generates five types of test simulation signals from the five antenna elements. Each of the five signal generation channels for generating these five types of test simulation signals includes a direct digital synthesizer DDSi, a filter Fi, an amplifier Ai, an attenuator ATi, and a switch SWi (i = 1 to 5). I have.
[0013]
In addition to the five signal generation channels, a first clock supply unit CL1 that supplies a common clock signal to each channel, a control unit CNT that controls the direct digital synthesizer DDSi of each channel, and each channel First and second A / D converters A / D1 and A / D2 for detecting the generated signal, and a second for supplying a clock signal for sampling to the first and second A / D converters Clock generation circuit CL2 and an input unit IN composed of a keyboard or the like for inputting a control command to the control unit CNT.
[0014]
Only the first half of the basic configuration of the direct digital synthesizer DDSi of each signal generation channel is simplified and illustrated in FIG. The first half of the synthesizer DDSi is composed of a sine wave holding memory M that holds the digital amplitude value of the sine wave signal, and an address generation circuit A that supplies a read address to the sine wave holding memory M. Although not shown, the latter half of the direct digital synthesizer is composed of a multiplier for amplitude adjustment and a D / A converter. A clock signal is supplied from the first clock generation circuit CL1 in FIG. 1 to the address generation circuit A, and a read head address is supplied from the control unit CNT in FIG.
[0015]
In each storage area of the sine wave holding memory M, an amplitude obtained by sampling a sine wave signal for one period, which changes over a range from −V volt to + V volt centered at 0 volt, at equal time intervals. The digital values are held in the order of increasing read addresses, as shown in the design. In the address holding circuit A, the address is incremented by one step in the cycle of the clock signal supplied from the outside, and the digital value of the amplitude held in each address is read. The read digital value of the amplitude of the sine wave signal is adjusted to an analog signal by a D / A conversion circuit (not shown) after the amplitude is adjusted by multiplication of a coefficient designated by the control unit CNT in a multiplier (not shown). Output from the direct digital synthesizer DDSi.
[0016]
The control unit CNT in FIG. 1 changes the frequency of the clock signal generated by the first clock generation unit CL1 in accordance with a control command input from the input unit IN by the user, thereby allowing direct digital of each signal generation system. Change the frequency of the sine wave signal generated by the synthesizer DDSi. This frequency change is performed over a high frequency range of several hundred MHz.
[0017]
Similarly, the control unit CNT changes the read head address commanded to the address generation circuit A (FIG. 3) of the direct digital synthesizer DDSi of the signal generation unit of each channel according to the control command input by the user from the input unit IN. By doing so, the phase of the sine wave signal generated by this synthesizer is changed. Furthermore, the control circuit CNT changes the amplitude of the sine wave signal output from each signal generation channel by supplying a coefficient for amplitude adjustment to a multiplier installed in each direct digital synthesizer DDSi. Let
[0018]
Further, the control unit CNT changes the characteristics of the filter Fi included in each signal generation channel according to the frequency of the clock signal, or changes the characteristics of the amplifier Ai and the attenuator ATi in order to increase the dynamic range. Let
[0019]
At the last stage of each signal generation channel, a signal switch SWi controlled by the control unit CNT is installed. Of the two output terminals of the signal switcher SWi, one is connected to the signal output terminal Oi, and the other is connected to the input terminal of the A / D converter 1 or A / D converter 2 of the signal detector. . That is, the other output terminal of the switch 1 of the channel 1 is connected to the input terminal of the first A / D converter 1 through a signal line having a length a. The other output terminals of the switches SW2 to SW5 of the channels 2 to 5 are connected to the second A / D converter 2 via individual signal lines having a length b and a common signal line having a length c. Connected to the input terminal. The lengths (electric lengths) between the switch SWi of each channel and the input terminals of the A / D converters 1 and 2 are set to be equal to each other according to the relationship of a = b + c.
[0020]
First, in each of the five signal generation channels, signal generation is started at a frequency designated by the user from the input unit IN. First, initialization is performed so that the phase and amplitude of the output of the direct digital synthesizer DDSi of each channel have the same value. Next, the sine wave signal of channel 1 is input to the A / D converter 1 and the sine wave signal of channel 2 is input to the A / D converter 2 by the operation of the switches SW1 and SW2. Digital signals output from the A / D conversion units 1 and 2 are fed back to the control unit CNT.
[0021]
The control unit CNT detects the phase difference and amplitude difference of the digital sine wave signals fed back from the A / D conversion units 1 and 2, and the channel 2 direct digital synthesizer so that these differences become zero. A calibration process is performed in which the phase and amplitude are adjusted by changing the read head address of DDSi and the coefficient of the multiplier. The amplitude is changed by multiplying the 16-bit sine wave signal read from the sine wave holding memory M of FIG. 3 by a 16-bit coefficient. When the calibration for the signal generation channel 2 is completed, the same calibration process is sequentially repeated for each signal generation unit from the channel 3 to the channel 5 to perform calibration. As a result, the phases and amplitudes of outputs from all channels are matched.
[0022]
When this calibration process is completed, the calibrated phase difference and amplitude ratio of channels 2 to 5 with respect to channel 1 become values that match test conditions such as the direction of arrival of the received radio waves determined by the input unit IN. The phase and amplitude are set in the direct digital synthesizer DDSi of channels 2-5.
[0023]
When the setting of the phase and amplitude of the sine wave signal output from each signal generation channel is completed through the above-described procedure, the switches SW1 to SW5 are switched, and the analog sine wave signal generated in each signal generation channel is changed to each. Supplied to channel output terminals O1-O5. Analog sine wave signals output from the output terminals O1 to O5 are supplied as test signals to a direction detection device to be tested (not shown).
[0024]
The phase difference and amplitude ratio of the sine wave signal of each channel set based on the test conditions specified from the input unit IN (for example, the arrival direction of the received radio wave) may be theoretically calculated. Alternatively, it may be experimentally obtained for an actual array antenna.
[0025]
For example, when a signal arrives at a spatially arranged array antenna from an azimuth angle θ and an elevation angle Φ, the directivity of the mth antenna element arranged at the position (xm, ym, zm) is set to Bm (θ, If Φ), the reception signal Sm of this antenna element is given by the following equation.
Sm (θ, Φ)
= Bm (θ, Φ) exp [j (2π / λ (xmsinθ sinΦ + ym cosθ sinΦ + zm cosΦ)]
Where λ is the wavelength of the incoming radio wave.
[0026]
FIG. 2 is a functional block diagram showing a configuration of a signal generator according to another embodiment of the present invention. The signal generator of this embodiment has a plurality of signals having the same configuration as a signal generator composed of five signal generation channels (excluding the switch SWi) constituting the signal generator 10 shown in FIG. The generators A, B,... N are provided. This signal generator is further output as a common part to the signal generators A to N from a clock generator that supplies a clock signal to each signal generator and each signal generation channel that constitutes each signal generator. Adders S1 to S5 for adding the corresponding ones of the sine wave signals, a variable attenuator for attenuating the amplitude of the added signal, output terminals OT1 to OT5 and an A / D converter A switch SW that switches between A / D 1 and 2 and a control unit CNT that sets the amplitude and phase of a sine wave signal that simulates each incoming radio wave supplied to the addition unit. The A / D converters A / D1, 2 are for detecting a signal for calibration, as in the case of the signal generator of FIG. The switch SW also switches the output of the channel 1 to the A / D converter 1 and switches one output of the channels 2 to 5 to the A / D converter 2 as in the case of FIG. It has become.
[0027]
Sine wave signals output from the corresponding ones of the five signal generation channels of each signal generation unit are added in the adders S1 to S5 and output to the output terminals OT1 to OT5. Each of the signal generation units A to N in FIG. 2 is transmitted from different signal generation sources, or received from each of the five array antennas through different propagation paths transmitted from a common signal generation source. It is for simulating a signal. The frequencies of the signals generated by the signal generators A to N can all be different. Further, the phase difference and amplitude ratio of the sine wave signals output from the five signal generation channels in the signal generators A to N can all be set independently according to the arrival direction of the received radio wave. .
[0028]
The case where the signal generator of the present invention is used for simulating the received signal by the array antenna has been exemplified above. However, the signal generator of the present invention can be expanded for other purposes, such as simulating other signals or microphone arrays that detect sound waves.
[0029]
【The invention's effect】
As described above in detail, according to the signal generator of the present invention, a desired sine wave signal is generated by controlling a plurality of direct digital synthesizers that generate sine wave signals of controllable frequency, phase and amplitude. Is done. As a result, it is possible to generate a high-frequency test signal with a simple and inexpensive circuit configuration.
[0030]
According to one preferred embodiment of the present invention, a feedback system including signal detecting means for detecting a phase and amplitude relationship between each sine wave signal output from each signal generation channel is employed. For this reason, labor and time for adjusting the relationship between the phase and amplitude of the signal can be greatly reduced, and the manufacturing cost can be reduced. In addition, it is possible to use inexpensive elements and circuits that do not require high operational stability, thereby further reducing the cost of the apparatus.
[0031]
According to another preferred embodiment of the present invention, the signal detecting means selects a signal output from one of a plurality of channels as a reference signal, and a signal sequentially selected from one of all remaining channels. A relative system configuration is used in which the phase and the amplitude are compared. For this reason, it is possible to configure the device with inexpensive elements and circuits that have a more gradual requirement for the stability of operation, and there is an advantage that further cost reduction of the device can be realized.
[Brief description of the drawings]
FIG. 1 is a functional block diagram showing a configuration of a signal generator according to an embodiment of the present invention.
FIG. 2 is a functional block diagram showing a configuration of a signal generator according to another embodiment of the present invention.
3 is a conceptual diagram for explaining the configuration and operation of the direct digital synthesizer of FIG. 1. FIG.
FIG. 4 is a functional block diagram showing an example of the configuration of a conventional signal generator.
FIG. 5 is a functional block diagram showing another example of the configuration of a conventional signal generator.
[Explanation of symbols]
DDS1 to DDS5 Direct digital synthesizers F1 to F5 Filters A1 to A5 Amplifiers AT1 to AT5 Attenuators SW1 to SW5 Switching devices O1 to O5 Signal output terminals A / D1 to A / D5 A / D converter CNT Controller CL1 Clock Generator

Claims (5)

A plurality of signal generation channels each including a direct digital synthesizer that generates a sinusoidal signal of controllable frequency, phase and amplitude;
A control unit configured to set a desired phase and amplitude relationship between the sine wave signals output from the signal generation channels by controlling the direct digital synthesizers of the signal generation channels; A signal generator comprising: 2. The signal generating apparatus according to claim 1, wherein the control unit further includes a signal detecting unit that detects a phase and amplitude relationship between the sine wave signals output from the signal generating channels. The signal detection means is output from a first signal selection means for selecting a signal output from a specific one of the signal generation channels as a reference signal and one of all remaining signal generation channels. A second signal selecting unit that sequentially selects a signal as a signal to be compared; and a comparing unit that compares the phase and amplitude between the signals selected by the first and second selecting units. The signal generator according to claim 2. 4. The sine wave signal output from each signal generation channel is a signal for simulating a reception signal of an incoming radio wave output from each antenna element of the array antenna apparatus. Each signal generator. Multiple signal generators including the same number of signal generation channels are installed, the outputs of the corresponding signal generation channels constituting each signal generator are combined, and the combined signal is output from each antenna element. The signal generation apparatus according to claim 4, which simulates an incoming wave reception signal.

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