JP3610222B2

JP3610222B2 - Capacitor

Info

Publication number: JP3610222B2
Application number: JP01840898A
Authority: JP
Inventors: 重喜武田
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 1998-01-30
Filing date: 1998-01-30
Publication date: 2005-01-12
Anticipated expiration: 2018-01-30
Also published as: JPH11219842A

Description

【０００１】
【発明の属する技術分野】
本発明は、印刷配線回路やマルチチップモジュール・ハイブリット回路等の印刷回路に好適な、誘電体の同一面上で所定の閉曲線の形状を有する２つの電極の端面同士を対向配置させて成るコンデンサに関するものである。
【０００２】
【従来の技術】
従来より、各種の電気回路や電子回路において容量素子として使用されるコンデンサは、通常は２つの平行平板状の導体から成る電極をそれらの平面を対向させて配置することにより、あるいはそのような平行平板状の電極を複数組み合わせて接続することにより、あるいは対向させた平行平板状の電極間に誘電率の高い誘電体を挿入して容量値を増すこと等により、集中定数回路素子として、目的の容量を有する電子部品として形成されている。
【０００３】
この場合、電極の面積をＳとし、それらが間隔ｄで配置されており、その間が比誘電率ε_ｒの誘電体で満たされているとすると、その容量値Ｃは、
Ｃ＝ε_ｒ×ε_０×Ｓ／ｄ
となる。
【０００４】
また、印刷配線回路やマルチチップモジュール・ハイブリット回路等の印刷回路基板や多層回路基板において回路素子としてコンデンサを形成する場合、容量値があまり高くないものであれば、それら誘電体層を積層して成る回路基板に内蔵させるコンデンサとして、層間に平行平板状の導体層から成る電極を誘電体層を介して対向させて設けることで形成されている。この場合の容量値は上記と同様の式で表わされる。
【０００５】
さらに、容量値が非常に小さいものであれば、基板を構成する誘電体層の同一平面上に導体層から成る２つの電極をそれらの端面同士を対向させて並べて、いわゆるインターディジタル型（櫛型）コンデンサとして純２次元的な形状で形成されていた。
【０００６】
このようなコンデンサは、通常は誘電体層の面上に微小な回路素子として形成され、厚みｔすなわち対向させた端面の高さが数μｍ〜数十μｍ、長さＬすなわち対向させた端面の全長がせいぜい十数ｍｍ〜数十ｍｍ程度であり、また多くは基板の表面に形成されていて端面同士の間のε_ｒも小さいため、このような形状のコンデンサにより高い容量値を得ることは困難であった。
【０００７】
従って、従来の通常のコンデンサは、要求される容量値に応じて以上のようなそれぞれの形状を選択し、容量値が小さい順から、導体層の端面同士を対向させたインターディジタル型等の２次元形状、平行平板状の電極等を対向させた２．５次元形状、さらに２．５次元形状のものを複数組み合わせた３次元形状という構造の回路素子・回路部品として形成され使用されてきた。
【０００８】
【発明が解決しようとする問題点】
しかしながら、以上のような従来のコンデンサでは、要求される容量値が決まるとそれを実現するための次元が決まってしまうこととなるため、次元の低い構造で、かつ実用的な寸法で大きな容量値が得られるコンデンサを実現することが困難であるという問題点があった。例えば、インターディジタル型の２次元形状のコンデンサでは通常は容量値が１ｐＦ程度であり、多層回路基板に内蔵された平行平板状の導体層による２．５次元形状のコンデンサでは比誘電率の高い誘電体層を使用しても通常は１０ｐＦ程度のものを実現することさえ困難であった。
【０００９】
これに対し、さらに容量値を増すためには、複数の平行平板状の電極を組み合わせる、あるいは大面積の平行平板状の電極をロール状に丸めてコンデンサを形成するという手段が採られるが、この場合には形状が３次元形状となるため寸法が大きくなってしまい、回路素子の高集積化や高密度実装化が進められている回路基板には使用することができず、また実際にコンデンサを生産する際のプロセスが複雑となるという制約もあった。
【００１０】
本発明は上記事情に鑑みて本発明者が鋭意研究に努めた結果完成されたものであり、その目的は、厚膜印刷技術や薄膜形成技術といった回路基板の製造に容易に適用できる技術でもって形成でき、各種の回路基板に対して高集積化や高密度実装化に対応して形成するのに適した２次元形状でありながら、上記の従来の２．５次元形状のコンデンサによる以上の大きな容量値を得ることができるコンデンサを提供することにある。
【００１１】
【問題点を解決するための手段】
本発明のコンデンサは、上記のような問題点を解決するため、２．５次元形状あるいは３次元形状のコンデンサで得られるのと同等以上の容量値を、より次元を低くした２次元形状のコンデンサで、しかも小さい寸法で得ることができるものである。本発明のコンデンサは、最小の次元である２次元形状のコンデンサであるインターディジタル型コンデンサと同様の２次元形状で、より次元の高い形状の容量値を実現させたものである。
【００１２】
すなわち、本発明のコンデンサは、誘電体の同一面上で、下記条件（１）〜（３）の少なくとも１つを満たす閉曲線の形状の内周を有する外側電極と、前記閉曲線の形状の外周を有する内側電極とが、前記内周の端面と前記外周の端面同士を対向させて配設されていることを特徴とするものである。
（１）正方形の枠内に配置され、この枠の２つの対角線に対して線対称な閉曲線である。
（２）前記枠を４つ正方形状に並べた大枠内に配置され、各々の枠内に配置した前記閉曲線の前記大枠の対角線と前記大枠の中心点側で交わる部位に開口部を形成するとともに互いに隣接する前記閉曲線の前記開口部同士を前記大枠の２つの対角線に対して線対称な補助曲線で接続して成り、前記大枠の２つの対角線に対して線対称な閉曲線である。
（３）前記枠内または前記大枠内の少なくとも一部を縮小または拡大し、前記（１）の閉曲線または前記（２）の閉曲線を平面上または曲面上に変形させて配置した閉曲線である。
【００１３】
本発明のコンデンサは、誘電体のある同一面上で、面の寸法に対し非常に小さい間隔の間隙をもって、外側電極と内側電極とを構成する平行２線の導体線あるいは２枚の導体膜が所定の形状とされたその端面同士を対向させて配設されて、それによりその端面同士の間に容量を形成しているものであり、これら平行２線の導体線あるいは２枚の導体膜は誘電体基板等の誘電体の同一面上に厚膜印刷技術や薄膜形成技術等の適当な技術を用いて容易に形成して配設することができる。
【００１４】
そして、外側電極の内周および内側電極の外周を上記の各条件を満たす閉曲線の形状とすると、この閉曲線は誘電体の同一面上に上記の条件に示された規則に従って交差することなく任意に長くすることのできる閉曲線であることから、その長さの間隙をもって２つの電極の端面同士を２次元形状で対向配置させることができ、それによって所望の高い容量値を容易に実現することができる。
【００１５】
このように、本発明のコンデンサによれば、誘電体の同一面上で、上記（１）〜（３）の少なくとも１つの条件を満たす閉曲線の形状の内周を有する外側電極の内周の端面と、同じ閉曲線の形状の外周を有する内側電極の外周の端面とを対向させて配設したことから、限られた面積の正方形の平面上あるいはその正方形を変形させた平面上または曲面上に、２つの電極の端面が所定の間隙をもって対向する長さを上記の各閉曲線の形状として極めて長くかつ任意に設定することができ、２次元の形状でありながら２．５次元形状のコンデンサ以上の容量値を得ることができる。
【００１６】
また、本発明のコンデンサによれば、上記の条件（１）を基本として条件（２）を適用することにより、正方形の枠と大枠との面積を同じとした場合にほぼ２倍の長さで外側電極の内周の端面と内側電極の外周の端面とを対向配置することができて、その端面同士の間に形成される容量により高い容量値のコンデンサを容易に実現することができる。さらに、条件（３）を適用することにより誘電体の平坦面上のみならず凹凸等の種々の曲面上にも所望の容量値のコンデンサを容易に実現することができる。
【００１７】
さらに、本発明のコンデンサによれば、誘電体の同一面上で２つの電極の端面同士を対向配置することにより構成されていることから、これら電極を厚膜印刷技術や薄膜形成技術といった回路基板の製造に容易に適用できる技術でもって形成することができるので、各種の回路基板に対してその表面や内部の誘電体層上に高集積化や高密度実装化に対応して形成することができ、しかも最小の次元である２次元形状で、より次元の高い形状のコンデンサと同等以上の高い容量値を実現することができる。
【００１８】
【発明の実施の形態】
以下、本発明のコンデンサについて図面に基づき説明する。
図１（ａ）〜（ｄ）は、それぞれ本発明のコンデンサの実施の形態の一例を説明するための平面図である。
まず、図１（ａ）に示すように、正方形の枠１（実線で示す）内に、この枠１の２つの対角線２（破線で示す）に対して線対称な閉曲線３を配置する。ここでは閉曲線３として円を例示しており、この場合にはさらに枠の中心点を原点として相対向する２辺に平行にｘ軸を、このｘ軸に垂直にｙ軸を配置した場合（それぞれ一点鎖線で示す）に、閉曲線３はこれらｘ軸およびｙ軸に対しても線対称となっている。
【００１９】
ここで、このような単純な閉曲線３では、本発明のコンデンサにより実現しようとする高い容量値は得られないので、この閉曲線３を仮に０次の閉曲線とする。
【００２０】
そこで、図１（ｂ）に示すように、この枠１を４つ正方形状に隙間なく並べて正方形の枠４とすると、この新たな正方形の枠４内には、その中央を原点にｘ軸およびｙ軸を配置した場合にそれぞれ第１・第２・第３・第４象限に図１（ａ）の閉曲線３が配置されることとなる。
【００２１】
次いで、図１（ｃ）に示すように、各々の閉曲線３の新たな正方形の枠４の２つの対角線５（破線で示す）と原点側で交わる部位に、その交点の周りを対角線５に対して、例えば１／４周の長さずつ、線対称にくり抜いて開口部を形成するとともに、互いに隣接する閉曲線３の開口部のそれぞれの端部同士を対角線５に対して線対称である４つの補助曲線６、例えば閉曲線３の開口部の端部同士の距離の１／２を半径とする円弧等で接続して新たな閉曲線７を形成する。これを仮に１次の閉曲線とすると、この閉曲線７の長さは、４つの閉曲線３の長さの和と等しくなる。
【００２２】
これにより、正方形の枠４内に配置され、この枠４の２つの対角線５に対して線対称な閉曲線７が得られる。本発明のコンデンサに対しては、例えばこの閉曲線７が条件（１）を満たす閉曲線となる。
【００２３】
次に、この図１（ｃ）に示す閉曲線７を用いて、図１（ｄ）に示すように、その正方形の枠４を４つ正方形状に並べて正方形の大枠８を形成し、この大枠８内の各々の枠４内に配置した閉曲線７の大枠８の対角線９と大枠８の中心点側で交わる部位に対角線９に対して線対称に開口部を形成するとともに、互いに隣接する閉曲線７の開口部の端部同士を大枠８の２つの対角線９に対して線対称な４つの補助曲線１０で接続する。これを仮に２次の閉曲線とする。
【００２４】
これにより、正方形の大枠８内に配置された、大枠８の２つの対角線９に対して線対称な閉曲線１１が得られる。本発明のコンデンサに対しては、例えばこの閉曲線１１が条件（２）を満たす閉曲線となる。
【００２５】
このとき、大枠８の１辺の長さは枠４の長さの２倍となっており、この閉曲線１１の長さは４つの閉曲線７の長さの和と等しくなっている。そこで、この大枠８を長さで１／２、面積で１／４となるように縮小すれば大枠８はもとの枠４と同じ大きさとなり、閉曲線１１の長さは閉曲線７の長さの２倍となって、同じ面積の正方形の内部に２倍の長さの閉曲線を規則性をもって配置させることができる。
【００２６】
従って、この場合は、閉曲線７の形状の内周を有する外側電極の内周の端面と、閉曲線７の形状の外周を有する内側電極の外周の端面とを対向配置した、すなわち閉曲線７の形状の間隙をもって２つの電極の端面同士を対向配置したコンデンサに対し、閉曲線１１の形状の間隙をもって同様に２つの電極の端面同士を対向配置したコンデンサは、同じ間隔で同じ厚みの２つの電極、すなわち同じ高さの端面同士を対向配置させたとき、ほぼ２倍の容量値を有するものとなる。
【００２７】
そして、枠４あるいは大枠８を縮小または拡大する倍率を任意に設定することにより、その結果得られた閉曲線の形状の内周を有する外側電極の内周の端面と、同じ形状の外周を有する内側電極の外周の端面とを、その閉曲線の形状の間隙をもって対向配置させることにより、所望の任意の容量値を有する２次元形状のコンデンサを得ることができる。
【００２８】
さらに、枠４内に配置された閉曲線７または大枠８内に配置された閉曲線１１に対して、枠４内または大枠８内の少なくとも一部を縮小または拡大することにより、所定の規則性をもって配置した閉曲線を平面上で変形させ、さらに平面上ではなく曲面上に変形させて配置した閉曲線とすることができ、この場合は、誘電体の平坦面上のみならず凹凸等の種々の曲面上にも所望の容量値のコンデンサを容易に実現することができる。
【００２９】
また、コンデンサの容量値は、同じ閉曲線の形状の間隙をもって対向配置した場合にその間隔を変え、また電極の厚みすなわち対向する端面の高さを変えることによっても変化させることができ、それによっても容量値を調整して所望の容量値のコンデンサを得ることができる。
【００３０】
このようにして実現された本発明のコンデンサの例を、図２（ａ）および（ｂ）にそれぞれ平面図で示す。図２において１２は誘電体である。ここでは正方形の平板状の誘電体基板を用いた例を示しているが、この誘電体１２には、多層回路基板の表面や内部の誘電体層等の種々の誘電体を用いることができ、その面の形状も平坦面のみならず凹凸等の種々の曲面であってもよい。
【００３１】
１３は図１（ｃ）に示した閉曲線７に相当する閉曲線の間隙であり、図２（ａ）の例ではこの閉曲線の間隙１３をもって、その閉曲線の形状の内周を有する外側電極としての導体線１４ａと、その閉曲線の形状の外周を有する内側電極としての導体線１４ｂとが、誘電体１２の同一面上でその端面同士を対向させて配設されており、これにより導体線１４ａの端面と導体線１４ｂの端面との間で容量を形成している。また、図２（ｂ）の例では、同様の閉曲線の間隙１３をもって、その閉曲線の形状の内周を有する外側電極としての導体層１６ａと、その閉曲線の形状の外周を有する内側電極としての導体層１６ｂとが、誘電体１２の同一面上でその端面同士を対向させて配設されており、これにより導体層１６ａの端面と導体層１６ｂの端面との間で容量を形成している。
【００３２】
このように、本発明のコンデンサにおいて誘電体の同一面上で対向配置させる外側電極と内側電極の２つの電極は、図２（ａ）に示すように閉曲線の間隙１３に沿った内周形状および外周形状を有する２本の導体線１４ａ・１４ｂとしてもよく、あるいは図２（ｂ）に示すようにその２本の導体線を端部としたような２つの導体層１６ａ・１６ｂとしてもよい。そのいずれの場合であっても、コンデンサの容量は閉曲線の間隙１３を介して対向し合った端面の部分で発生するため、本発明のコンデンサとして機能するものとなる。
【００３３】
また、２つの電極１４ａ・１４ｂおよび１６ａ・１６ｂを外部またはその誘電体１２の内部に形成された電気回路・電子回路と電気的に接続するには、図２（ａ）および（ｂ）に示すようにそれぞれの電極１４ａ・１４ｂおよび１６ａ・１６ｂにリード線やボンディングワイヤ等の導体線１５ａ・１５ｂを接続したり、電極端子を取着もしくは圧接したり、あるいは誘電体１２の内部に配設したビア導体やスルーホール導体等の貫通導体を接続したりすればよく、仕様に応じて適当な電気的接続手段を用いればよい。
【００３４】
次に、図３により本発明の実施の形態の他の例を説明する。図３（ａ）〜（ｃ）は、それぞれ本発明のコンデンサの実施の形態の他の例を説明する平面図である。
【００３５】
図３（ａ）は図１（ａ）と同様の０次の閉曲線を示すものであり、正方形の枠２１内に、この枠２１の２つの対角線２２に対して線対称な閉曲線２３を配置する。ここでは閉曲線２３として八角形を例示しており、この場合もさらに枠の中心点を原点として相対向する２辺に平行にｘ軸を、このｘ軸に垂直にｙ軸を配置した場合（それぞれ一点鎖線で示す）、これらｘ軸およびｙ軸に対しても線対称となっている。但し、このようにｘ軸およびｙ軸に対しても線対称であることは必要な条件ではなく、このことは図１の例においても同じである。
【００３６】
図３（ａ）の場合でも、このような単純な閉曲線２３では、本発明のコンデンサにより実現しようとする高い容量値は得られないので、この閉曲線２３も仮に０次の閉曲線とする。
【００３７】
次に、図３（ｂ）に示すように、この枠２１を４つ正方形状に隙間なく並べて正方形の枠２４とし、各々の閉曲線２３の新たな正方形の枠２４の２つの対角線２５と原点側で交わる部位に、その交点の周りを対角線２５に対して線対称にくり抜いて開口部を形成するとともに、互いに隣接する閉曲線２３の開口部のそれぞれの端部同士を対角線２５に対して線対称である４つの補助曲線２６、例えば直角に曲がった屈曲線等で接続して新たな閉曲線２７を形成する。これも仮に１次の閉曲線とすると、この閉曲線２７の長さは、４つの閉曲線２３の長さの和とほぼ等しくなる。
【００３８】
これにより、正方形の枠２４内に配置され、この枠２４の２つの対角線２５に対して線対称な閉曲線２７が得られる。本発明のコンデンサに対しては、例えばこの閉曲線２７が条件（１）を満たす閉曲線となる。
【００３９】
次に、この図３（ｂ）に示す閉曲線２７を用いて、図３（ｃ）に示すように、その正方形の枠２４を４つ正方形状に並べて正方形の大枠２８を形成し、この大枠２８内の各々の枠２４内に配置した閉曲線２７の大枠２８の対角線２９と大枠２８の中心点側で交わる部位に対角線２９に対して線対称に開口部を形成するとともに、互いに隣接する閉曲線２７の開口部の端部同士を大枠２８の２つの対角線２９に対して線対称な４つの補助曲線３０で接続する。これも仮に２次の閉曲線とする。
【００４０】
この結果、正方形の大枠２８内に配置された、大枠２８の２つの対角線２９に対して線対称な閉曲線３１が得られる。本発明のコンデンサに対しては、例えばこの閉曲線３１が条件（２）を満たす閉曲線となる。
【００４１】
これにより、図１に示した例と同様に、枠２４あるいは大枠２８を縮小または拡大する倍率を任意に設定することにより、あるいは枠２４内または大枠２８内の少なくとも一部を縮小または拡大することにより所定の規則性をもって配置した閉曲線を平面上で変形させ、または曲面上に変形させて配置した閉曲線とすることによって、その結果得られた閉曲線の形状の内周を有する外側電極の内周の端面と、同じ形状の外周を有する内側電極の外周の端面とを、その閉曲線の形状の間隙をもって対向配置させることにより、所望の任意の容量値を有する２次元形状のコンデンサを得ることができる。
【００４２】
次に、図４により本発明の実施の形態のさらに他の例を説明する。図４（ａ）〜（ｃ）は、それぞれ本発明のコンデンサの実施の形態の他の例を説明する平面図である。
【００４３】
図４（ａ）は図１（ｂ）および図３（ｂ）と同様の１次の閉曲線、すなわち本発明のコンデンサに対して条件（１）を満たす閉曲線を示すものであり、正方形の枠４１内に配置された、この枠４１の２つの対角線４２に対して線対称な閉曲線４３である。
【００４４】
次に、図４（ｂ）に示すように、この枠４１を４つ正方形状に隙間なく並べて正方形の大枠４４とし、各々の閉曲線４３の新たな正方形の大枠４４の２つの対角線４５と原点側で交わる部位に、その交点の周りを対角線４５に対して線対称にくり抜いて開口部を形成するとともに、互いに隣接する閉曲線４３の開口部のそれぞれの端部同士を対角線４５に対して線対称である４つの補助曲線４６、例えばほぼ直角に近い曲線等で接続して新たな閉曲線４７を形成する。これは２次の閉曲線に相当し、この閉曲線４７の長さは、４つの１次の閉曲線４３の長さの和とほぼ等しくなる。
【００４５】
これにより、正方形の大枠４４内に配置され、この大枠４４の２つの対角線４５に対して線対称な閉曲線４７が得られる。本発明のコンデンサに対しては、この閉曲線４７は条件（２）を満たす閉曲線となる。
【００４６】
次に、この図４（ｂ）に示す閉曲線４７を用いて、図４（ｃ）に示すように、その大枠４４を条件（１）にいう正方形の枠とみなして４つ正方形状に並べて正方形の大枠４８を形成し、この大枠４８内の各々の枠４４内に配置した閉曲線４７の大枠４８の対角線４９と大枠４８の中心点側で交わる部位に対角線４９に対して線対称に開口部を形成するとともに、互いに隣接する閉曲線４７の開口部の端部同士を大枠４８の２つの対角線４９に対して線対称な４つの補助曲線５０で接続する。これは仮に３次の閉曲線となる。
【００４７】
この結果、正方形の大枠４８内に配置された、大枠４８の２つの対角線４９に対して線対称な閉曲線５１が得られる。本発明のコンデンサに対しては、この閉曲線５１も条件（２）を満たす閉曲線となる。
【００４８】
これにより、図１および図３に示した例と同様に、枠４１あるいは大枠４４・４８を縮小または拡大する倍率を任意に設定することにより、あるいは枠４１内または大枠４４・４８内の少なくとも一部を縮小または拡大することにより所定の規則性をもって配置した閉曲線を平面上で変形させ、または曲面上に変形させて配置した閉曲線とすることによって、その結果得られた閉曲線の形状の内周を有する外側電極の内周の端面と、同じ形状の外周を有する内側電極の外周の端面とを、その閉曲線の形状の間隙をもって対向配置させることにより、所望の任意の容量値を有する２次元形状のコンデンサを得ることができる。
【００４９】
以上のようにして得られる本発明のコンデンサは、誘電体の表面上において２つの電極が対向配置されてその間隙に空気を介在させて形成される場合のみならず、その間隙に誘電体を充填させてもよく、多層回路基板の内部の誘電体層の同一面上に形成して、２つの電極の間隙をその上に位置する誘電体層や他の誘電体材料で充填させてもよいことは言うまでもない。
【００５０】
なお、本発明は以上の例に限定されるものではなく、本発明の要旨を逸脱しない範囲で種々の変更や改良を加えることは何ら差し支えない。例えば、このような閉曲線の形状の間隙に対して閉曲線に沿った貫通導体を並べて、容量値をさらに高めることもできる。
【００５１】
【発明の効果】
本発明のコンデンサによれば、誘電体の面上で、上記（１）〜（３）の少なくとも１つの条件を満たす閉曲線の形状の内周を有する外側電極の内周の端面とその閉曲線の形状の外周を有する内側電極の外周の端面とを、その閉曲線の形状の間隙をもって対向させて配設したことから、限られた面積の正方形の平面上あるいはその正方形を変形させた平面上または曲面上に、２つの電極の端面同士が対向する長さを上記の各閉曲線の形状として極めて長くかつ任意に設定することができ、２次元の形状でありながら２．５次元形状のコンデンサ以上の高い容量値を得ることができる。
【００５２】
また、本発明のコンデンサによれば、上記の条件（１）を基本として条件（２）を適用することにより、正方形の枠と大枠との面積を同じとした場合にはほぼ２倍の長さで電極の端面同士を対向配置することができ、さらに縮小または拡大する倍率を適当に設定することによって、高い容量値のコンデンサを容易に実現することができる。さらにまた、条件（３）を適用することにより誘電体の平坦面上のみならず凹凸等の種々の曲面上にも所望の容量値のコンデンサを容易に実現することができる。
【００５３】
さらに、本発明のコンデンサによれば、誘電体の同一面上に２つの電極の所定の形状の端面同士を対向配置することにより構成されていることから、これら電極は厚膜印刷技術や薄膜形成技術といった回路基板の製造に容易に適用できる技術でもって形成することができるので、各種の回路基板に対してその表面や内部の誘電体層上に高集積化や高密度実装化に対応して形成することができ、しかも最小の次元である２次元形状で、より次元の高い形状のコンデンサと同等以上の高い容量値を実現することができる。
【図面の簡単な説明】
【図１】（ａ）〜（ｄ）は、それぞれ本発明のコンデンサの実施の形態の一例を説明するための平面図である。
【図２】（ａ）および（ｂ）は、それぞれ本発明のコンデンサの実施の形態の一例を示す平面図である。
【図３】（ａ）〜（ｃ）は、それぞれ本発明のコンデンサの実施の形態の他の例を説明するための平面図である。
【図４】（ａ）〜（ｃ）は、それぞれ本発明のコンデンサの実施の形態の他の例を説明するための平面図である。
【符号の説明】
４、２４、４１・・・・・・・・・・・枠
５、９、２５、２９、４５、４９・・・・・対角線
６、１０、２６、３０、４６、５０・・・・・補助曲線
７、１１、２７、３１、４３、４７、５１・・・閉曲線
８、２８、４４、４８・・・・・・・・・大枠
１２・・・・・・・・・・・・・・・誘電体
１４ａ・・・・・・・・・・・・・・導体線（外側電極）
１４ｂ・・・・・・・・・・・・・・導体線（内側電極）
１６ａ・・・・・・・・・・・・・・導体層（外側電極）
１６ｂ・・・・・・・・・・・・・・導体層（内側電極）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a capacitor in which end faces of two electrodes having a shape of a predetermined closed curve are arranged opposite to each other on the same surface of a dielectric suitable for a printed circuit such as a printed wiring circuit or a multichip module / hybrid circuit. Is.
[0002]
[Prior art]
Conventionally, a capacitor used as a capacitive element in various electric circuits and electronic circuits is usually formed by arranging two parallel plate-shaped conductors with their planes facing each other, or in such a parallel state. As a lumped constant circuit element, by connecting a plurality of flat electrodes in combination, or by inserting a dielectric having a high dielectric constant between opposed parallel flat electrodes to increase the capacitance value, etc. It is formed as an electronic component having a capacity.
[0003]
In this case, assuming that the area of the electrode is S, they are arranged at a distance d, and the space between them is filled with a dielectric having a relative dielectric constant ε _r , the capacitance value C is
C = ε _r × ε ₀ × S / d
It becomes.
[0004]
When a capacitor is formed as a circuit element on a printed circuit board such as a printed wiring circuit, a multichip module / hybrid circuit, or a multilayer circuit board, the dielectric layer is laminated if the capacitance value is not so high. As a capacitor to be built in the circuit board, an electrode made of a parallel plate-like conductor layer is provided between layers with a dielectric layer facing each other. The capacitance value in this case is expressed by the same formula as above.
[0005]
Furthermore, if the capacitance value is very small, two electrodes made of a conductor layer are arranged on the same plane of the dielectric layer constituting the substrate with their end faces facing each other, so-called interdigital type (comb type) ) It was formed in a pure two-dimensional shape as a capacitor.
[0006]
Such a capacitor is usually formed as a minute circuit element on the surface of a dielectric layer, and has a thickness t, that is, a height of an opposed end surface of several μm to several tens of μm, and a length L, that is, an opposed end surface. The overall length is at most about several tens of millimeters to several tens of millimeters, and many of them are formed on the surface of the substrate and ε _r between the end faces is small. It was difficult.
[0007]
Therefore, the conventional ordinary capacitor is selected in accordance with the required capacitance value as described above, and an interdigital type or the like in which the end surfaces of the conductor layers are opposed to each other in ascending order of the capacitance value. It has been formed and used as a circuit element / circuit component having a structure of a three-dimensional shape including a two-dimensional shape, a 2.5-dimensional shape with parallel plate electrodes facing each other, and a plurality of 2.5-dimensional shapes.
[0008]
[Problems to be solved by the invention]
However, in the conventional capacitor as described above, when the required capacitance value is determined, the dimension for realizing it is determined. Therefore, a large capacitance value with a low-dimensional structure and a practical dimension is required. There is a problem that it is difficult to realize a capacitor capable of obtaining the above. For example, an interdigital two-dimensional capacitor usually has a capacitance value of about 1 pF, and a 2.5-dimensional capacitor with a parallel plate conductor layer built in a multilayer circuit board has a high dielectric constant. Even if a body layer is used, it is usually difficult to realize a layer of about 10 pF.
[0009]
On the other hand, in order to further increase the capacitance value, a method of combining a plurality of parallel plate electrodes or rolling a large area parallel plate electrode into a roll shape to form a capacitor is adopted. In some cases, the shape becomes a three-dimensional shape, resulting in an increase in size, which cannot be used for circuit boards where circuit elements are highly integrated and mounted with high density. There was also a restriction that the production process was complicated.
[0010]
The present invention has been completed as a result of diligent research conducted by the inventor in view of the above circumstances, and the object thereof is a technique that can be easily applied to the manufacture of circuit boards, such as thick film printing technology and thin film forming technology. It can be formed and has a two-dimensional shape suitable for high integration and high-density mounting on various circuit boards, but it is larger than the conventional 2.5-dimensional shape capacitor described above. The object is to provide a capacitor capable of obtaining a capacitance value.
[0011]
[Means for solving problems]
In order to solve the above-described problems, the capacitor of the present invention has a capacitance value equal to or higher than that obtained with a 2.5-dimensional or 3-dimensional capacitor, and a 2-dimensional capacitor with a lower dimension. In addition, it can be obtained with small dimensions. The capacitor of the present invention has a two-dimensional shape similar to an interdigital capacitor, which is a two-dimensional shape capacitor having the smallest dimension, and realizes a capacitance value having a higher dimension.
[0012]
In other words, the capacitor of the present invention includes an outer electrode having an inner circumference in a closed curve shape that satisfies at least one of the following conditions (1) to (3) on the same surface of the dielectric, and an outer circumference in the shape of the closed curve. The inner electrode has an inner peripheral end face and an outer peripheral end face opposed to each other.
(1) It is a closed curve which is arranged in a square frame and is line-symmetric with respect to two diagonal lines of this frame.
(2) The frame is arranged in a large frame in which the four frames are arranged in a square shape, and an opening is formed at a portion where the diagonal line of the large frame of the closed curve arranged in each frame intersects on the center point side of the large frame. The openings of the closed curves adjacent to each other are connected by auxiliary curves that are line symmetric with respect to the two diagonal lines of the large frame, and are closed curves that are line symmetric with respect to the two diagonal lines of the large frame.
(3) A closed curve obtained by reducing or enlarging at least part of the inside of the frame or the large frame and deforming the closed curve of (1) or the closed curve of (2) into a plane or a curved surface.
[0013]
The capacitor according to the present invention has two parallel conductor wires or two conductor films constituting the outer electrode and the inner electrode on the same surface of the dielectric, with a very small gap relative to the surface dimensions. The end surfaces of the predetermined shape are arranged so as to face each other, thereby forming a capacitance between the end surfaces, and these two parallel conductor wires or two conductor films are It can be easily formed and disposed on the same surface of a dielectric such as a dielectric substrate using an appropriate technique such as a thick film printing technique or a thin film forming technique.
[0014]
Then, if the inner circumference of the outer electrode and the outer circumference of the inner electrode are in the shape of a closed curve that satisfies the above conditions, the closed curve can be arbitrarily set on the same surface of the dielectric without intersecting according to the rules shown in the above conditions. Since it is a closed curve that can be lengthened, the end faces of the two electrodes can be arranged to face each other in a two-dimensional shape with a gap of that length, whereby a desired high capacitance value can be easily realized. .
[0015]
As described above, according to the capacitor of the present invention, the end surface of the inner periphery of the outer electrode having the inner periphery in the shape of a closed curve that satisfies at least one of the conditions (1) to (3) on the same surface of the dielectric. And the end face of the outer periphery of the inner electrode having the outer periphery of the same closed-curved shape are arranged so as to face each other, on a square plane of a limited area or on a plane or curved surface obtained by deforming the square, The length at which the end faces of the two electrodes are opposed to each other with a predetermined gap can be set to an extremely long and arbitrary shape as the shape of each of the above-mentioned closed curves. A value can be obtained.
[0016]
Further, according to the capacitor of the present invention, by applying the condition (2) on the basis of the above condition (1), the area of the square frame and the large frame is almost twice as long. The inner peripheral end face of the outer electrode and the outer peripheral end face of the inner electrode can be arranged to face each other, and a capacitor having a higher capacitance value can be easily realized by the capacitance formed between the end faces. Furthermore, by applying the condition (3), a capacitor having a desired capacitance value can be easily realized not only on the flat surface of the dielectric but also on various curved surfaces such as irregularities.
[0017]
Furthermore, according to the capacitor of the present invention, since the end faces of the two electrodes are arranged opposite to each other on the same surface of the dielectric, these electrodes are used as circuit boards such as thick film printing technology and thin film forming technology. Since it can be formed with a technology that can be easily applied to the manufacturing of various circuit boards, it can be formed on various dielectrics on the surface and inside of various circuit boards corresponding to high integration and high-density mounting. In addition, with a two-dimensional shape, which is the smallest dimension, a high capacitance value equivalent to or higher than that of a capacitor with a higher dimension can be realized.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
The capacitor of the present invention will be described below with reference to the drawings.
FIGS. 1A to 1D are plan views for explaining an example of an embodiment of the capacitor of the present invention.
First, as shown in FIG. 1A, a closed curve 3 that is line-symmetric with respect to two diagonal lines 2 (indicated by broken lines) of the frame 1 is arranged in a square frame 1 (indicated by a solid line). Here, a circle is illustrated as the closed curve 3, and in this case, the center point of the frame is the origin and the x-axis is arranged parallel to two opposite sides and the y-axis is arranged perpendicular to the x-axis (each The closed curve 3 is axisymmetric with respect to the x-axis and the y-axis.
[0019]
Here, since such a simple closed curve 3 cannot provide a high capacitance value to be realized by the capacitor of the present invention, this closed curve 3 is assumed to be a 0th-order closed curve.
[0020]
Therefore, as shown in FIG. 1B, when the four frames 1 are arranged in a square shape without gaps to form a square frame 4, the new square frame 4 has an x-axis and an origin at the center. When the y axis is arranged, the closed curve 3 of FIG. 1A is arranged in the first, second, third, and fourth quadrants, respectively.
[0021]
Next, as shown in FIG. 1 (c), the two diagonal lines 5 (shown by broken lines) of the new square frame 4 of each closed curve 3 intersect with the diagonal line 5 around the intersection point at the site where the origin line side intersects. Thus, for example, the length of a quarter circumference is cut out line-symmetrically to form an opening, and the ends of the openings of the closed curved lines 3 adjacent to each other are line-symmetrical with respect to the diagonal 5 A new closed curve 7 is formed by connecting with an auxiliary curve 6, for example, an arc having a radius of ½ of the distance between the ends of the opening of the closed curve 3. If this is a primary closed curve, the length of the closed curve 7 is equal to the sum of the lengths of the four closed curves 3.
[0022]
As a result, a closed curve 7 is obtained which is arranged in the square frame 4 and is symmetrical with respect to the two diagonal lines 5 of the frame 4. For the capacitor of the present invention, for example, the closed curve 7 is a closed curve that satisfies the condition (1).
[0023]
Next, using the closed curve 7 shown in FIG. 1C, as shown in FIG. 1D, four square frames 4 are arranged in a square shape to form a square large frame 8, and this large frame 8 An opening portion is formed symmetrically with respect to the diagonal line 9 at a portion where the diagonal line 9 of the large frame 8 of the closed curve 7 and the central point side of the large frame 8 intersect with each other, and the closed curved lines 7 adjacent to each other. The ends of the openings are connected to each other by four auxiliary curves 10 that are line-symmetric with respect to the two diagonal lines 9 of the large frame 8. This is assumed to be a quadratic closed curve.
[0024]
As a result, a closed curve 11 that is arranged in the square large frame 8 and that is line symmetric with respect to the two diagonal lines 9 of the large frame 8 is obtained. For the capacitor of the present invention, for example, the closed curve 11 is a closed curve that satisfies the condition (2).
[0025]
At this time, the length of one side of the large frame 8 is twice the length of the frame 4, and the length of the closed curve 11 is equal to the sum of the lengths of the four closed curves 7. Therefore, if the large frame 8 is reduced to 1/2 in length and 1/4 in area, the large frame 8 becomes the same size as the original frame 4, and the length of the closed curve 11 is the length of the closed curve 7. Thus, a closed curve having a length twice as large as that of a square having the same area can be arranged with regularity.
[0026]
Therefore, in this case, the end surface of the inner periphery of the outer electrode having the inner periphery of the shape of the closed curve 7 and the end surface of the outer periphery of the inner electrode having the outer periphery of the shape of the closed curve 7 are arranged to face each other, that is, the shape of the shape of the closed curve 7 In contrast to a capacitor in which the end faces of two electrodes are opposed to each other with a gap, a capacitor in which the end faces of two electrodes are similarly arranged to face each other with a gap in the shape of the closed curve 11 is equivalent to two electrodes having the same distance and the same thickness. When the height end faces are arranged to face each other, the capacitance value is almost doubled.
[0027]
Then, by arbitrarily setting the magnification for reducing or enlarging the frame 4 or the large frame 8, the inner peripheral end face of the outer electrode having the inner periphery of the shape of the closed curve obtained as a result and the inner periphery having the outer periphery of the same shape A two-dimensional capacitor having a desired arbitrary capacitance value can be obtained by disposing the end face on the outer periphery of the electrode so as to face each other with a gap in the shape of the closed curve.
[0028]
Further, the closed curve 7 arranged in the frame 4 or the closed curve 11 arranged in the large frame 8 is arranged with a predetermined regularity by reducing or enlarging at least a part of the frame 4 or the large frame 8. The closed curve can be deformed on a plane, and can be a curved curve arranged on a curved surface instead of on a plane. In this case, not only on the flat surface of the dielectric, but also on various curved surfaces such as irregularities. In addition, a capacitor having a desired capacitance value can be easily realized.
[0029]
In addition, the capacitance value of the capacitor can be changed by changing the distance when the electrodes are arranged facing each other with a gap having the same closed curve shape, and also by changing the thickness of the electrodes, that is, the height of the opposite end faces. A capacitor having a desired capacitance value can be obtained by adjusting the capacitance value.
[0030]
Examples of the capacitor of the present invention thus realized are shown in plan views in FIGS. 2 (a) and 2 (b), respectively. In FIG. 2, 12 is a dielectric. Although an example using a square flat dielectric substrate is shown here, various dielectrics such as a surface of a multilayer circuit board and an internal dielectric layer can be used as the dielectric 12. The shape of the surface may be not only a flat surface but also various curved surfaces such as irregularities.
[0031]
Reference numeral 13 denotes a gap of a closed curve corresponding to the closed curve 7 shown in FIG. 1C. In the example of FIG. 2A, a conductor as an outer electrode having an inner periphery of the shape of the closed curve having the gap 13 of the closed curve. A line 14a and a conductor line 14b as an inner electrode having an outer periphery in the shape of a closed curve are disposed on the same surface of the dielectric 12 with their end faces facing each other, whereby the end face of the conductor line 14a. And a capacitance between the end surface of the conductor wire 14b. In the example of FIG. 2B, a conductor layer 16a as an outer electrode having an inner periphery of the closed curve shape and a conductor as an inner electrode having an outer periphery of the shape of the closed curve with a gap 13 of the same closed curve. The layer 16b is disposed on the same surface of the dielectric 12 so that the end surfaces thereof face each other, thereby forming a capacitance between the end surface of the conductor layer 16a and the end surface of the conductor layer 16b.
[0032]
As described above, in the capacitor of the present invention, the two electrodes of the outer electrode and the inner electrode arranged to face each other on the same surface of the dielectric have an inner peripheral shape along the gap 13 of the closed curve as shown in FIG. Two conductor wires 14a and 14b having an outer peripheral shape may be used, or two conductor layers 16a and 16b having two conductor wires as ends as shown in FIG. 2B may be used. In either case, the capacitance of the capacitor is generated at the end face portions facing each other through the gap 13 of the closed curve, and thus functions as the capacitor of the present invention.
[0033]
Further, in order to electrically connect the two electrodes 14a and 14b and 16a and 16b to an external circuit or an electric circuit / electronic circuit formed inside the dielectric 12 as shown in FIGS. In this way, conductor wires 15a and 15b such as lead wires and bonding wires are connected to the electrodes 14a and 14b and 16a and 16b, electrode terminals are attached or pressure-contacted, or disposed inside the dielectric 12, respectively. A through conductor such as a via conductor or a through-hole conductor may be connected, and an appropriate electrical connection means may be used according to specifications.
[0034]
Next, another example of the embodiment of the present invention will be described with reference to FIG. 3A to 3C are plan views for explaining other examples of the embodiment of the capacitor of the present invention.
[0035]
FIG. 3A shows a 0th-order closed curve similar to FIG. 1A, and a closed curve 23 that is line-symmetric with respect to two diagonal lines 22 of the frame 21 is arranged in a square frame 21. . Here, an octagon is illustrated as the closed curve 23. In this case as well, when the center point of the frame is the origin and the x-axis is arranged parallel to two opposite sides and the y-axis is arranged perpendicular to the x-axis (respectively, respectively) This is also axisymmetric with respect to the x-axis and the y-axis. However, it is not a necessary condition that the line is symmetrical with respect to the x-axis and the y-axis as described above, and this is the same in the example of FIG.
[0036]
Even in the case of FIG. 3 (a), such a simple closed curve 23 cannot provide a high capacitance value to be realized by the capacitor of the present invention, so this closed curve 23 is also assumed to be a zero-order closed curve.
[0037]
Next, as shown in FIG. 3B, the four frames 21 are arranged in a square shape without gaps to form a square frame 24, and the two diagonal lines 25 of the new square frame 24 of each closed curve 23 and the origin side The openings are formed by hollowing out the intersections around the intersections in a line-symmetric manner with respect to the diagonal line 25, and the ends of the openings of the closed curves 23 adjacent to each other are line-symmetrical with respect to the diagonal line 25. A new closed curve 27 is formed by connecting four auxiliary curves 26 such as a bent line bent at a right angle. If this is also a primary closed curve, the length of the closed curve 27 is approximately equal to the sum of the lengths of the four closed curves 23.
[0038]
As a result, a closed curve 27 is obtained which is arranged in the square frame 24 and is symmetric with respect to the two diagonal lines 25 of the frame 24. For the capacitor of the present invention, for example, the closed curve 27 is a closed curve that satisfies the condition (1).
[0039]
Next, using the closed curve 27 shown in FIG. 3 (b), as shown in FIG. 3 (c), four square frames 24 are arranged in a square shape to form a square large frame 28, and this large frame 28 An opening is formed symmetrically with respect to the diagonal line 29 at a portion where the diagonal line 29 of the large frame 28 of the closed curve 27 and the central point side of the large frame 28 intersect with each other, and the closed curved lines 27 adjacent to each other. The ends of the openings are connected to each other by four auxiliary curves 30 that are line-symmetric with respect to two diagonal lines 29 of the large frame 28. This is also assumed to be a quadratic closed curve.
[0040]
As a result, a closed curve 31 is obtained which is arranged in the square large frame 28 and is line symmetric with respect to the two diagonal lines 29 of the large frame 28. For the capacitor of the present invention, for example, the closed curve 31 is a closed curve that satisfies the condition (2).
[0041]
Thereby, similarly to the example shown in FIG. 1, by arbitrarily setting a magnification for reducing or enlarging the frame 24 or the large frame 28, or reducing or enlarging at least a part of the frame 24 or the large frame 28. The closed curve arranged with a predetermined regularity is deformed on a plane or a curved curve arranged on a curved surface, so that the inner circumference of the outer electrode having the inner circumference of the resulting closed curve shape is obtained. By arranging the end face and the end face on the outer periphery of the inner electrode having the same outer periphery with a gap in the shape of the closed curve, a two-dimensional capacitor having a desired arbitrary capacitance value can be obtained.
[0042]
Next, still another example of the embodiment of the present invention will be described with reference to FIG. 4A to 4C are plan views illustrating other examples of the embodiment of the capacitor of the present invention.
[0043]
4A shows a first-order closed curve similar to FIGS. 1B and 3B, that is, a closed curve satisfying the condition (1) for the capacitor of the present invention. The closed curve 43 is symmetrical with respect to the two diagonal lines 42 of the frame 41 arranged inside.
[0044]
Next, as shown in FIG. 4B, the four frames 41 are arranged in a square shape without gaps to form a square large frame 44, and two diagonal lines 45 of the new square large frame 44 of each closed curve 43 and the origin side The openings are formed by hollowing out the intersections around the intersection 45 in a line-symmetric manner with respect to the diagonal line 45, and the ends of the openings of the closed curves 43 adjacent to each other are line-symmetric with respect to the diagonal line 45. A new closed curve 47 is formed by connecting four auxiliary curves 46, for example, a curve close to a right angle. This corresponds to a secondary closed curve, and the length of the closed curve 47 is approximately equal to the sum of the lengths of the four primary closed curves 43.
[0045]
As a result, a closed curve 47 is obtained which is arranged within the square large frame 44 and is symmetric with respect to the two diagonal lines 45 of the large frame 44. For the capacitor of the present invention, the closed curve 47 is a closed curve that satisfies the condition (2).
[0046]
Next, using the closed curve 47 shown in FIG. 4 (b), as shown in FIG. 4 (c), the large frame 44 is regarded as a square frame in the condition (1) and arranged in a square shape. Of the closed curve 47 arranged in each of the frames 44 in the large frame 48, and an opening is formed symmetrically with respect to the diagonal 49 at a portion where the diagonal line 49 of the large frame 48 intersects with the central point side of the large frame 48. At the same time, the ends of the openings of the closed curves 47 adjacent to each other are connected by four auxiliary curves 50 that are line-symmetric with respect to the two diagonal lines 49 of the large frame 48. This is a cubic closed curve.
[0047]
As a result, a closed curve 51 that is arranged in the square large frame 48 and is symmetrical with respect to the two diagonal lines 49 of the large frame 48 is obtained. For the capacitor of the present invention, this closed curve 51 is also a closed curve that satisfies the condition (2).
[0048]
Accordingly, as in the example shown in FIGS. 1 and 3, by arbitrarily setting a magnification for reducing or enlarging the frame 41 or the large frames 44, 48, or at least one in the frame 41 or the large frames 44, 48. By reducing or enlarging the part, the closed curve arranged with a predetermined regularity is deformed on the plane, or the curved line is deformed and arranged on the curved surface. An end face on the inner circumference of the outer electrode having the outer circumference and an end face on the outer circumference of the inner electrode having the outer circumference of the same shape are arranged to face each other with a gap in the shape of the closed curve. A capacitor can be obtained.
[0049]
The capacitor of the present invention obtained as described above is not only formed when two electrodes are arranged opposite to each other on the surface of the dielectric and air is interposed in the gap, but the gap is filled with the dielectric. It may be formed on the same surface of the dielectric layer inside the multilayer circuit board, and the gap between the two electrodes may be filled with a dielectric layer located on the dielectric layer or another dielectric material. Needless to say.
[0050]
In addition, this invention is not limited to the above example, A various change and improvement can be added in the range which does not deviate from the summary of this invention. For example, it is possible to further increase the capacitance value by arranging through conductors along the closed curve with respect to the gap having such a closed curve shape.
[0051]
【The invention's effect】
According to the capacitor of the present invention, on the surface of the dielectric, the inner peripheral end face of the outer electrode having the inner periphery of the closed curve shape satisfying at least one of the conditions (1) to (3) and the shape of the closed curve Since the outer end face of the inner electrode having the outer periphery of the inner electrode is arranged to face each other with a gap in the shape of the closed curve, it is on a square plane of a limited area, on a plane obtained by deforming the square, or on a curved surface In addition, the length of the two electrodes facing each other can be set to an extremely long and arbitrary length as the shape of each of the above-mentioned closed curves, and the capacitance is higher than a 2.5-dimensional shape capacitor while being a two-dimensional shape. A value can be obtained.
[0052]
Further, according to the capacitor of the present invention, when the area of the square frame and the large frame is made the same by applying the condition (2) based on the condition (1), the length is almost twice as long. Thus, the end faces of the electrodes can be arranged opposite to each other, and a capacitor having a high capacitance value can be easily realized by appropriately setting the magnification for reduction or enlargement. Furthermore, by applying the condition (3), a capacitor having a desired capacitance value can be easily realized not only on the flat surface of the dielectric but also on various curved surfaces such as irregularities.
[0053]
Furthermore, according to the capacitor of the present invention, since the end faces of the predetermined shape of the two electrodes are arranged opposite to each other on the same surface of the dielectric, these electrodes are formed by thick film printing technology or thin film formation. Because it can be formed with technology that can be easily applied to circuit board manufacturing, such as technology, it is compatible with high integration and high-density mounting on the surface and internal dielectric layer for various circuit boards. A two-dimensional shape that is the smallest dimension can be formed, and a capacitance value equal to or higher than that of a capacitor having a higher dimension can be realized.
[Brief description of the drawings]
FIGS. 1A to 1D are plan views for explaining an example of an embodiment of a capacitor of the present invention, respectively.
FIGS. 2A and 2B are plan views showing an example of an embodiment of a capacitor of the present invention, respectively.
FIGS. 3A to 3C are plan views for explaining another example of the embodiment of the capacitor of the present invention.
FIGS. 4A to 4C are plan views for explaining another example of the capacitor according to the embodiment of the present invention. FIG.
[Explanation of symbols]
4, 24, 41 ... Frames 5, 9, 25, 29, 45, 49 ... Diagonal lines 6, 10, 26, 30, 46, 50 ... Auxiliary curve 7, 11, 27, 31, 43, 47, 51 ... Closed curve 8, 28, 44, 48 ... ... Large frame 12 ... ..Dielectric material 14a ... Conductor wire (outer electrode)
14b ... Conductor wire (inner electrode)
16a ... Conductor layer (outer electrode)
16b ... Conductor layer (inner electrode)

Claims

On the same surface of the dielectric, an outer electrode having an inner periphery in the shape of a closed curve that satisfies at least one of the following conditions (1) to (3), and an inner electrode having an outer periphery in the shape of the closed curve are: A capacitor, wherein a circumferential end face and the outer circumferential end face are arranged to face each other.
(1) A closed curve that is arranged in a square frame and is line-symmetric with respect to two diagonal lines of the frame.
(2) The frame is arranged in a large frame in which the four frames are arranged in a square shape, and an opening is formed at a portion where the diagonal line of the large frame of the closed curve arranged in each frame intersects on the center point side of the large frame. The openings of the closed curves adjacent to each other are connected by auxiliary curves that are line symmetric with respect to the two diagonal lines of the large frame, and are closed curves that are line symmetric with respect to the two diagonal lines of the large frame.
(3) A closed curve obtained by reducing or enlarging at least part of the inside of the frame or the large frame and deforming the closed curve of (1) or the closed curve of (2) into a plane or a curved surface.