JP3599300B2 - Semiconductor storage device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a ferroelectric memory having a nonvolatile operation mode and a volatile operation mode. More specifically, during a normal operation, a read operation and a write operation are performed as a volatile memory (that is, a DRAM), and when power is turned off and on, information is written and written information is read as a non-volatile memory. The present invention relates to a dielectric memory.
[0002]
[Prior art]
In general, a ferroelectric memory uses a ferroelectric capacitor including a ferroelectric film made of a ferroelectric material as a storage element. In the operation of a ferroelectric memory as a nonvolatile memory, a polarization reversal phenomenon, which is a characteristic characteristic of a ferroelectric material, is used when writing and reading data. However, as the number of times of writing increases, fatigue occurs in the ferroelectric film constituting the ferroelectric capacitor, and the polarization retention characteristics of the ferroelectric film may be deteriorated.
[0003]
To overcome this problem, it is conceivable to read and write data without using the polarization inversion phenomenon. Specifically, during a normal operation, the ferroelectric memory functions as a volatile memory (that is, a DRAM), and data is written and read by accumulating and discharging charges without using the polarization inversion phenomenon. On the other hand, when the power is turned on and off, the mode is switched to the non-volatile operation mode, and the ferroelectric memory is caused to function as a non-volatile memory utilizing the polarization inversion phenomenon.
[0004]
In addition, when operating as a normal DRAM in the volatile operation mode, stored information is refreshed to periodically cause domain inversion in the ferroelectric film. The resulting polarization direction is used as non-volatile information together with volatile information based on charge accumulation and release.
[0005]
As described above, by appropriately switching between the non-volatile operation mode and the volatile operation mode to reduce the number of occurrences of the polarization inversion, the fatigue of the ferroelectric film based on the polarization inversion phenomenon and the deterioration of the operation characteristics of the memory due to it. Can be reduced. Hereinafter, switching between the non-volatile operation mode and the volatile operation mode is also simply referred to as “operation mode switching”.
[0006]
A semiconductor memory configured so that a nonvolatile operation mode and a volatile operation mode can be selected in a ferroelectric memory using a ferroelectric capacitor as a storage element is disclosed in, for example, Japanese Patent Application Laid-Open No. 7-182872. I have. In the configuration disclosed in this publication, the rise of the power supply is automatically detected, and the semiconductor memory is set to the nonvolatile operation mode. Thereafter, the semiconductor memory can be operated as a volatile memory like a DRAM by switching to the volatile operation mode by the action of the switching signal.
[0007]
Specifically, FIG. 6 is a configuration diagram of an operation mode switching signal generation circuit 10 included in the semiconductor memory disclosed in the above publication. This circuit 10 includes a power supply voltage level detection circuit 20 therein, and is supplied with a DRAM mode designation signal from a control circuit 30 to be described later. As schematically shown in FIG. 7, the power supply voltage level detection circuit 20 includes a fixed resistor R connected between the power supply voltage Vcc on the high potential side and the node VN8, and a series connection between the node VN8 and the ground potential. , And three inverters INVA, INVB and INVC connected in series between node VN8 and the output.
[0008]
FIG. 8 is a diagram schematically showing output characteristics of the power supply voltage level detection circuit 20. As shown in FIG. 8, while the power supply voltage is at the low level, the output of the power supply voltage level detection circuit 20 is at the low level. On the other hand, when the power supply rises and the power supply voltage exceeds a certain value, as shown by a straight line having a slope 1 in FIG. 8, the power supply voltage level detection circuit 20 outputs a High level signal equal to the current power supply voltage value. An output voltage is generated.
[0009]
When the output of the power supply voltage level detection circuit 20 switches to the high level, the potential of the node A included in the operation mode switching signal generation circuit 10 goes to the high level via the capacitor C6A. In response, the operation mode switching signal F / DSig supplied from the node B becomes Low level, and the semiconductor memory is set to the non-volatile operation mode. On the other hand, when switching from the non-volatile operation mode thus set to the volatile operation mode, a high-level DRAM mode designation signal is output from the control circuit 30 to the operation mode switching signal generation circuit 10. As a result, the transistor connected to the node A is turned on, and the node A goes to the low level. In response, the operation mode switching signal F / DSig supplied from the node B becomes High level, and the semiconductor memory is set to the volatile operation mode.
[0010]
As described above, in the configuration disclosed in the above publication, the operation mode is automatically switched according to the change in the power supply voltage level.
[0011]
[Problems to be solved by the invention]
When evaluating the operation characteristics of the ferroelectric memory, an operation test of the ferroelectric memory may be performed by applying a power supply voltage in a wider range than in normal use. For example, to evaluate how much margin is secured from the design specification value of the power supply voltage value and confirm the design accuracy, arbitrarily set the volatile operation mode independently of the power supply voltage level change. In some cases, margin evaluation accompanying this may be performed.
[0012]
However, in the prior art ferroelectric memory disclosed in the above publication having the above-described configuration, the operation mode is automatically switched according to a change in the power supply voltage. Therefore, the evaluation (operation test) in which the volatile operation mode needs to be arbitrarily set independently of the change in the power supply voltage level as described above cannot be performed.
[0013]
Furthermore, the upper limit value and the lower limit value of the power supply voltage that can be actually applied to the ferroelectric memory are determined depending on the polarization reversal characteristics and the charge retention characteristics of the ferroelectric material forming the ferroelectric film. . For example, in a ferroelectric capacitor configured using a ferroelectric material, if the amount of charge stored in the capacitor is too large, that is, the thickness of the ferroelectric film varies greatly (generally, When the thickness becomes thin, the charge of the ferroelectric capacitor is discharged to the bit line via the switching transistor, and the bit line is charged by the discharged charge. As a result, the potential difference between the charged potential of the bit line and the electrode plate of the ferroelectric capacitor is reduced, so that it may not be possible to rewrite the capacitor included in the memory cell. Therefore, there is an upper limit on the power supply voltage level that can be applied.
[0014]
For such a reason, there is a possibility that a power supply voltage in a range given as a specification value to be realized cannot be actually applied to the ferroelectric memory.
[0015]
The present invention has been made to solve the above-described problem, and an object of the present invention is to switch between a volatile operation mode and a non-volatile operation mode according to an operation condition, and to change a power supply voltage level under a certain condition. An object of the present invention is to provide a semiconductor memory device which is configured to perform the operation automatically in response to a change and to be forcibly performed under a different condition by a control signal independently of a change in a power supply voltage level.
[0016]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes a ferroelectric memory having a nonvolatile operation mode and a volatile operation mode, first and second input terminals to which first and second input signals are respectively applied, A first signal generation circuit for outputting a first control signal for controlling activation and deactivation of the sexual operation mode to the ferroelectric memory, and based on the first input signal and the second input signal And a second signal generation circuit for outputting a second control signal for controlling activation and deactivation of the nonvolatile operation mode to the first signal generation circuit. The circuit, based on a second control signal output from the second signal generation circuit, For activating and deactivating the nonvolatile operation mode The first operating condition or To deactivate the nonvolatile operation mode. A first control signal corresponding to a second operation condition is output, and in the first operation condition, the nonvolatile operation mode and the volatile operation in response to a change in the voltage level of the power supply voltage. Mode is automatically switched, and in the second operating condition, only the volatile operating mode is activated, thereby achieving the above object.
[0017]
In one embodiment, the second signal generation circuit includes a holding circuit for holding information indicating whether the nonvolatile operation mode is activated or deactivated. An output signal from the holding circuit may be provided to the first signal generation circuit as the second control signal. The second signal generation circuit is First and second If the voltage level of the input signal Respectively Above a certain voltage level A first and a second output of a predetermined signal, respectively. A voltage level detection circuit is further included, and an output signal from the voltage level detection circuit is provided to the holding circuit.
[0018]
Hereinafter, the operation will be described.
[0019]
In order to achieve the above-described object, it is necessary to automatically switch the operation mode in response to a change in the power supply voltage under one operation condition, while, under other operation conditions, for example, In the operation of (1), it is necessary to ensure that only the volatile operation is performed without performing the nonvolatile operation. Therefore, according to the present invention, in a semiconductor memory device including a ferroelectric memory having a nonvolatile operation mode and a volatile operation mode, a first control signal for controlling activation and deactivation of the nonvolatile operation mode is provided. A first signal generation circuit for outputting to the ferroelectric memory and a second control signal for controlling activation and deactivation of the nonvolatile operation mode based on an input signal indicating a voltage level of a power supply voltage; And a second signal generation circuit that outputs the signal to the second signal generation circuit. Then, under the first operation condition, the nonvolatile operation mode and the volatile operation mode are automatically switched according to the change in the voltage level of the power supply voltage. Under the second operation condition, only the volatile operation mode is activated. I do.
[0020]
Specifically, an operation mode switching signal generation circuit is provided as the first signal generation circuit included in the operation mode switching signal generation circuit system. The second signal generation circuit included in the circuit system may include two power supply voltages for detecting that the power supply voltage level has become higher than a predetermined voltage level (for example, a power supply voltage level Vcc on the high potential side). A level detection circuit and a latch circuit (holding circuit) for receiving output signals from these detection circuits are provided. However, these two power supply voltage level detection circuits can be omitted. An output signal from the latch circuit becomes an operation mode switching signal. With such a configuration, the volatile operation mode can be forcibly set, and the operation margin test of the power supply voltage can be performed.
[0021]
As described above, according to the present invention, the combination of two external input signals respectively input to the two power supply voltage level detection circuits included in the operation mode switching signal generation circuit system enables the power supply voltage level to be independent from the change in the power supply voltage level. In addition, the nonvolatile operation mode can be forcibly activated or deactivated. Information indicating whether the nonvolatile operation mode is activated or deactivated is held by the latch circuit. This makes it possible to forcibly and reliably implement the volatile operation mode at a desired time, in addition to the automatic switching of the operation mode due to the fluctuation of the power supply voltage level.
[0022]
The power supply voltage level detection circuit used in the operation mode switching signal generation circuit system outputs the external input signal only when the external input signal indicating the power supply voltage level has a voltage higher than a predetermined voltage level. This is a circuit that recognizes that the signal is at a high level. If the power supply voltage level detection circuit having such a function is combined with an external input signal indicating the power supply voltage level, the input terminal for the external input signal can be shared with the input terminal used for other purposes. And the circuit configuration can be simplified.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0024]
FIG. 1 is a circuit diagram showing a configuration of an operation mode switching signal generation circuit system 100 according to the principle of the present invention.
[0025]
The circuit system 100 shown in FIG. 1 supplies an operation mode switching signal F / DSig to a ferroelectric memory (not shown in FIG. 1, hereinafter also referred to as a semiconductor memory). Specifically, a first signal generation circuit 40 that actually supplies an operation mode switching signal F / DSig (first control signal) to the semiconductor memory, and a first signal generation circuit 40 that receives two external input signals and And a second signal generation circuit 50 for providing an output. When external input signals IN1 and IN2 indicating the power supply voltage level are input to second signal generation circuit 50, activation / inactivation of first signal generation circuit 40 is controlled, and the operation mode of semiconductor memory is accordingly adjusted. Is set.
[0026]
The detailed configuration of the first signal generation circuit 40 will be described later.
[0027]
The second signal generation circuit 50 includes power supply voltage level detection circuits 5 and 6, a holding circuit (latch circuit) 4, and inverter circuits 11 and 12. When each of the external input signals IN1 and IN2 indicating the power supply voltage level becomes higher than a predetermined voltage level, for example, the power supply voltage level Vcc on the high potential side, the power supply voltage level detection circuits 5 and 6 output the signals from the output terminals 1 and 2 to High. It has a function of supplying level output signals SET and RESET. For example, when the external input signal IN1 to the power supply voltage level detection circuit 5 becomes equal to or higher than a predetermined voltage level, a high-level output signal SET is supplied from the output terminal 1 of the power supply voltage level detection circuit 5. Similarly, when the external input signal IN2 to the power supply voltage level detection circuit 6 becomes equal to or higher than a predetermined voltage level, a high-level output signal RESET is supplied from the output terminal 2 of the power supply voltage level detection circuit 6.
[0028]
The output signals SET and RESET are input to the input terminals of the NOR type latch circuit 4, respectively. An output signal PMT is output from the output terminal 3 of the latch circuit 4 and supplied to the first signal generation circuit 40 via the inverter circuits 11 and 12 connected in series.
[0029]
The output signal PMT (second control signal) from the latch circuit 4 activates or deactivates the first signal generation circuit 40, that is, automatically switches the operation mode based on the power supply voltage level. This signal indicates whether the operation is to be performed dynamically or the volatile operation mode is forcibly set. In some cases, the first signal generation circuit 40 automatically switches between the nonvolatile operation mode and the volatile operation mode of the semiconductor memory according to the power supply voltage level in response to the received second control signal PMT. Is generated as an operation mode switching signal F / DSig and supplied to the semiconductor memory. Alternatively, instead of automatically switching the operation mode based on the power supply voltage level, a signal for forcibly switching the operation mode may be generated as the operation mode switching signal F / DSig and supplied to the semiconductor memory. . The operation mode switching signal F / DSig given from the first signal generation circuit 40 to the semiconductor memory for the operation mode switching control is also referred to as a first control signal.
[0030]
Whether the operation mode is switched automatically or forcibly set is determined by the external input signals IN1 and IN2. Specifically, for example, when the external input signal IN1 is at a high level (a super-voltage level higher than the power supply voltage Vcc as described later) and the external input signal IN2 is at a low level, the volatile operation mode is forcibly applied. , And when the external input signal IN1 is at a low level and the external input signal IN2 is at a high level (super voltage level), automatic switching can be enabled.
[0031]
The operation of the circuit system 100 having the above configuration will be described more specifically below.
[0032]
The external input signal IN1 to the power supply voltage level detection circuit 5 has a voltage level equal to or higher than a predetermined level, and the external input signal IN2 to the power supply voltage level detection circuit 6 has a voltage level equal to or lower than the predetermined level (for example, ground potential). (GND), the output signal SET from the power supply voltage level detection circuit 5 becomes High level, while the output signal RESET from the power supply voltage level detection circuit 6 maintains Low level. At this time, the output signal PMT from the latch circuit 4 becomes High level, the nonvolatile operation mode is deactivated, and the volatile operation mode is activated. Therefore, after the above operation of the circuit system 100 is completed, evaluation of the normal operation mode of the semiconductor memory, that is, evaluation of the volatile operation mode can be started.
[0033]
After the end of the normal operation, when the voltage level of the external input signal IN2 to the power supply voltage level detection circuit 6 becomes higher than a predetermined level, the output signal RESET from the power supply voltage level detection circuit 6 changes to High level. As a result, the output signal PMT from the latch circuit 4 changes to Low level, activating the nonvolatile operation mode of the semiconductor memory. At this time, the switching of the operation mode does not depend on the state of the external input signal IN1 to another power supply voltage level detection circuit 5.
[0034]
As described above, in the circuit system 100 shown in FIG. 1, by inputting the external input signals IN1 and IN2 indicating the power supply voltage level to the two power supply voltage level detection circuits 5 and 6, respectively, the nonvolatile operation mode of the semiconductor memory Control the activation / inactivation of. As the external input signals IN1 and IN2, a voltage signal having a voltage level equal to or higher than a predetermined level when the power supply voltage becomes higher than a predetermined voltage level (typically, the power supply voltage level Vcc on the high potential side). , Should be supplied. Therefore, the input terminals of the external input signals IN1 and IN2 are input terminals for other uses (for example, an address input terminal or a control signal) to which a voltage signal having a voltage level corresponding to between the power supply voltage Vcc and the ground potential GND is input. Input terminal).
[0035]
FIG. 2 is a configuration diagram of the circuit system 100 showing the specific circuit configuration of the power supply voltage level detection circuits 5 and 6 in further detail.
[0036]
In the power supply voltage level detection circuit 5, three transistors Tr1 to Tr3 are connected in series between an input terminal to which an external input signal IN1 is supplied and a ground potential GND. The transistor Tr2 is supplied with a boosted power supply voltage Vpp having a higher voltage level than the power supply voltage Vcc on the high potential side as a substrate voltage. On the other hand, the gates of the transistors Tr2 and Tr3 are connected to the power supply voltage Vcc on the high potential side, respectively. The output signal SET is output to the outside from an output terminal 1 provided between the transistors Tr2 and Tr3.
[0037]
Similarly, in the power supply voltage level detection circuit 6, three transistors Tr4 to Tr6 are connected in series between the input terminal to which the external input signal IN2 is supplied and the ground potential GND. The transistor Tr5 is supplied with a boosted power supply voltage Vpp having a higher voltage level than the power supply voltage Vcc on the high potential side as a back gate voltage. On the other hand, the gates of the transistors Tr5 and Tr6 are respectively connected to the power supply voltage Vcc on the high potential side. The output signal RESET is output from an output terminal 2 provided between the transistors Tr5 and Tr6.
[0038]
Here, the transistors Tr1, Tr3, Tr4 and Tr6 are N-channel transistors, and the transistors Tr2 and Tr5 are P-channel transistors. Accordingly, assuming that the threshold voltages of the N-channel transistor and the P-channel transistor are Vtn and Vtp, respectively, in the power supply voltage level detection circuit 5, the external input signal IN1 is supplied with the power supply voltage Vcc and the respective threshold voltages Vtn and Vtp. (That is, Vcc + Vtn + Vtp), all three transistors Tr1 to Tr3 are turned ON. At this time, by appropriately setting the ON resistance ratio of each of the transistors Tr1 to Tr3, the output signal SET is set to a high level. On the other hand, when the external input signal IN1 to the power supply voltage level detection circuit 5 goes low, the transistors Tr1 and Tr2 are turned off, while Tr3 is kept on. As a result, the output signal SET changes to Low level.
[0039]
Similarly, in power supply voltage level detection circuit 6, if external input signal IN2 becomes higher than the sum of power supply voltage Vcc and respective threshold voltages Vtn and Vtp (that is, Vcc + Vtn + Vtp), three transistors Tr4 To Tr6 are all turned on. At this time, by appropriately setting the ON resistance ratio of each of the transistors Tr4 to Tr6, the output signal RESET is set to the high level. When the external input signal IN2 to the power supply voltage level detection circuit 6 goes low, the transistors Tr4 and Tr5 are turned off, while Tr6 is kept on. As a result, the output signal SET changes to Low level.
[0040]
The configuration of the operation mode switching signal generation circuit system 100 according to the present invention described above is only an embodiment of the present invention. Modifications to other configurations can be easily made. For example, the method of latching the information indicating the active or inactive state of the nonvolatile operation mode, the method of detecting the power supply voltage level, or the method of setting the operation mode based on the detection result are different from those described above. It can be implemented in different ways.
[0041]
Alternatively, in the operation mode switching signal generation circuit system 200 shown in FIG. 3, the second signal generation circuit 55 corresponding to the second signal generation circuit 50 of FIG. The configuration is such that the level detection circuits 5 and 6 are omitted, and the external input signals IN1 and IN2 are directly input to the latch circuit 4. Even with such a configuration, the same effects as those of the circuit system 100 described above can be obtained.
[0042]
However, in the case of the configuration of the circuit system 200, the input terminals of the external input signals IN1 and IN2 need to be provided independently of the input terminals for other uses. This is to prevent the non-volatile operation mode of the semiconductor memory from being activated or deactivated by external input signals IN1 and IN2 having normal power supply voltage levels (Vcc and Vss).
[0043]
FIG. 4 is a diagram schematically illustrating a configuration of a first signal generation circuit 40 that can be included in the circuit systems 100 and 200.
[0044]
The first signal generation circuit 40 includes an operation mode switching signal generation circuit 10, a control circuit 30, and a pair of transistors. Among these components, the operation mode switching signal generation circuit 10 and the control circuit 30 have the same configuration as that disclosed in JP-A-7-182872 described with reference to FIGS. be able to.
[0045]
Specifically, a control circuit 30 that supplies a DRAM mode instruction signal is connected to the operation mode switching signal generation circuit 10. A node C is provided between control circuit 30 and operation mode switching signal generating circuit 10, an N-channel transistor 7 is provided between power supply voltage Vcc and node C, and ground potential GND and node C are provided. A P-channel transistor 8 is provided therebetween. The output signal PMT of the latch circuit 4 described above is input to the gates of these transistors 7 and 8, respectively.
[0046]
As is clear from the configuration of FIG. 4, when output signal PMT from latch circuit 4 attains a high level, N-channel transistor 7 conducts and the potential of node C attains a high level. As a result, the DRAM mode designating signal is at a high level. Become a level. As a result, the switching signal output from the operation mode switching signal generation circuit 10 is set to activate the volatile operation mode. On the other hand, when the output signal PMT from the latch circuit 4 goes to a low level, the P-channel transistor 8 conducts and the potential of the node C goes to a low level. As a result, the DRAM mode designation signal goes to a low level. As a result, the switching signal output from the operation mode switching signal generation circuit 10 is set to inactivate the volatile operation mode.
[0047]
As described above, in the circuit configuration of FIG. 4, when the output signal PMT from the latch circuit 4 goes high, the DRAM mode designation signal automatically goes high, and the volatile operation mode is activated.
[0048]
FIG. 5 is a diagram schematically showing a configuration of another first signal generation circuit 45 in which a circuit component is connected to the operation mode switching signal generation circuit 10 in a manner different from that in FIG. .
[0049]
Also in this case, a control circuit 30 for supplying a DRAM mode instruction signal is connected to the operation mode switching signal generation circuit 10. A node D is provided between operation mode switching signal generating circuit 10 and its output terminal, an N-channel transistor 7 is provided between power supply voltage Vcc and node D, and a ground potential GND and node D are provided. A P-channel transistor 8 is provided therebetween. The output signal PMT of the latch circuit 4 described above is input to the gates of these transistors 7 and 8, respectively.
[0050]
As is apparent from the configuration of FIG. 5, when the output signal PMT from the latch circuit 4 goes high, the N-channel transistor 7 conducts and the potential of the node D goes high. As a result, the mode switching signal output from the operation mode switching signal generating circuit 10 becomes High level, activating the volatile operation mode. On the other hand, when the output signal PMT from the latch circuit 4 goes low, the P-channel transistor 8 conducts and the potential of the node D goes low. As a result, the mode switching signal output from the operation mode switching signal generation circuit 10 becomes Low level, and the volatile operation mode is deactivated.
[0051]
As described above, in the circuit configuration of FIG. 5, when the output signal PMT from the latch circuit 4 goes to the high level, the mode switching signal automatically goes to the high level, and the volatile operation mode is activated. In particular, in the configuration of FIG. 5, switching between the nonvolatile operation mode and the volatile operation mode can be automatically performed without being affected by the switching signal generation circuit 10.
[0052]
【The invention's effect】
As described above, the semiconductor memory device of the present invention includes the operation mode switching signal generation circuit system which receives the external input signal indicating the power supply voltage level and switches between the nonvolatile operation mode and the volatile operation mode. I have. Specifically, the operation mode switching signal generation circuit system includes an operation mode switching signal generation circuit as a first signal generation circuit, and further includes, for example, a power supply voltage detection circuit and a latch circuit (holding circuit) as a second signal generation circuit. ). This makes it possible to select between a case where the nonvolatile operation mode and the volatile operation mode are automatically switched according to the level of the power supply voltage and a case where the nonvolatile operation mode and the volatile operation mode are used only in the volatile operation mode.
[0053]
As a result, during a normal operation, the volatile operation mode is selected, the semiconductor memory functions as a volatile memory (for example, DRAM), and writing and reading of information can be performed by accumulation and release of electric charge. Thus, the number of times of polarization reversal of the ferroelectric film is reduced, so that effects such as suppression of deterioration of the operation characteristics of the ferroelectric film and extension of the life of the semiconductor memory are achieved.
[0054]
Further, according to the above configuration, the volatile operation mode can be arbitrarily set independently of the change in the power supply voltage level. Therefore, it is possible to perform an operation test of the semiconductor memory performed for an applied voltage in a range wider than a power supply voltage applied in a normal operation, for example, an evaluation test for confirming a margin from a design specification value.
[0055]
As the external input signal used for controlling the switching of the operation mode, a voltage signal that can have a predetermined level, for example, a voltage level higher than the power supply voltage Vcc on the high potential side according to a change in the power supply voltage level is used. do it. At this time, if a power supply voltage level detection circuit is provided, an input to which a voltage signal for another use having a voltage level between the power supply voltage Vcc and the ground voltage GND is input without providing another input terminal. The terminal can also be used as an input terminal for this input signal.
[Brief description of the drawings]
FIG. 1 is a circuit diagram schematically showing an example of a configuration of an operation mode switching signal generation circuit system included in a ferroelectric memory which is a semiconductor memory device of the present invention.
FIG. 2 is a circuit diagram showing an example of a detailed circuit configuration of the operation mode switching signal generation circuit system of FIG. 1;
FIG. 3 is a circuit diagram schematically showing another example of the configuration of the operation mode switching signal generation circuit system included in the ferroelectric memory as the semiconductor storage device of the present invention.
FIG. 4 is a circuit diagram schematically illustrating an example of a configuration of a first signal generation circuit included in a ferroelectric memory which is a semiconductor storage device of the present invention.
FIG. 5 is a circuit diagram schematically showing another example of the configuration of the first signal generation circuit included in the ferroelectric memory as the semiconductor storage device of the present invention.
FIG. 6 is a circuit diagram schematically illustrating an example of a configuration of an operation mode switching signal generation circuit of the ferroelectric memory.
7 is a circuit diagram schematically illustrating an example of a configuration of a power supply voltage level detection circuit included in the operation mode switching signal generation circuit of FIG. 6;
8 is a graph schematically showing output characteristics of the power supply voltage level detection circuit of FIG.
[Explanation of symbols]
1, 2, 3 output terminals
4 Latch circuit
5, 6 power supply voltage level detection circuit
7 N-channel transistor
8 P-channel transistor
10. Operation mode switching signal generation circuit
11, 12 Inverter element
20 Power supply voltage level detection circuit
30 control circuit
40, 45 First signal generation circuit
50, 55 second signal generation circuit
100, 200 operation mode switching signal generation circuit system
IN1, IN2 External input signal
SET, RESET Output signal of power supply voltage level detection circuit
Output signal of PMT latch circuit (second control signal)
Vcc High potential power supply voltage
Vss Low potential side power supply voltage
GND Ground potential
F / DSig operation mode switching signal
Vpp boosted power supply voltage
Tr1, Tr3, Tr4, Tr6 N-channel transistor
Tr2, Tr5 P-channel transistor

Claims (4)

A ferroelectric memory having a non-volatile operation mode and a volatile operation mode,
First and second input terminals to which first and second input signals are respectively applied;
A first signal generation circuit for outputting a first control signal for controlling activation and deactivation of the nonvolatile operation mode to the ferroelectric memory;
A second control signal for controlling activation and deactivation of the nonvolatile operation mode based on the first input signal and the second input signal; and outputting a second control signal to the first signal generation circuit. A signal generation circuit;
With
The first signal generating circuit, based on said second control signal output from the second signal generating circuit, the first operating condition or said to activate and deactivate the non-volatile mode of operation Outputting a first control signal corresponding to a second operation condition for inactivating the nonvolatile operation mode ;
Under the first operation condition, the nonvolatile operation mode and the volatile operation mode are automatically switched according to a change in the voltage level of the power supply voltage. Under the second operation condition, only the volatile operation mode is used. Is activated, the semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein said second signal generation circuit includes a holding circuit for holding information indicating whether said nonvolatile operation mode is activated or inactivated. 3. The semiconductor memory device according to claim 2, wherein an output signal from said holding circuit is provided to said first signal generation circuit as said second control signal. The second signal generation circuit further includes a first and a second voltage level detection circuit for outputting a predetermined signal when a voltage level of the first and second input signals is higher than a predetermined voltage level, respectively. 3. The semiconductor memory device according to claim 2, wherein an output signal from said voltage level detection circuit is provided to said holding circuit. 4.

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