JP3594198B2 - マルチレベル最少論理ネットワーク - Google Patents

マルチレベル最少論理ネットワーク Download PDF

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JP3594198B2
JP3594198B2 JP50682297A JP50682297A JP3594198B2 JP 3594198 B2 JP3594198 B2 JP 3594198B2 JP 50682297 A JP50682297 A JP 50682297A JP 50682297 A JP50682297 A JP 50682297A JP 3594198 B2 JP3594198 B2 JP 3594198B2
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message
nodes
interconnect
level
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JP2000500253A (ja
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コーク エス． リード，
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コーク エス． リード，
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17393—Indirect interconnection networks non hierarchical topologies having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/803—Three-dimensional arrays or hypercubes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/02—Topology update or discovery
    • H04L45/06—Deflection routing, e.g. hot-potato routing

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computing Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Computer And Data Communications (AREA)
  • Logic Circuits (AREA)
  • Multi Processors (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Medicines Containing Material From Animals Or Micro-Organisms (AREA)
  • Small-Scale Networks (AREA)
  • Selective Calling Equipment (AREA)
  • Communication Control (AREA)
JP50682297A 1995-07-21 1996-07-19 マルチレベル最少論理ネットワーク Expired - Fee Related JP3594198B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/505,513 US5996020A (en) 1995-07-21 1995-07-21 Multiple level minimum logic network
US505,513 1995-07-21
PCT/US1996/011828 WO1997004399A2 (en) 1995-07-21 1996-07-19 Multiple level minimum logic network

Publications (2)

Publication Number Publication Date
JP2000500253A JP2000500253A (ja) 2000-01-11
JP3594198B2 true JP3594198B2 (ja) 2004-11-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP50682297A Expired - Fee Related JP3594198B2 (ja) 1995-07-21 1996-07-19 マルチレベル最少論理ネットワーク

Country Status (14)

Country Link
US (5) US5996020A (de)
EP (3) EP1058194A3 (de)
JP (1) JP3594198B2 (de)
KR (1) KR100401682B1 (de)
AT (1) ATE327537T1 (de)
AU (1) AU725826B2 (de)
CA (1) CA2227271C (de)
DE (2) DE69636165D1 (de)
ES (1) ES2160556T1 (de)
GR (1) GR20010300054T1 (de)
HK (1) HK1010926A1 (de)
MX (1) MX9800626A (de)
NZ (2) NZ503094A (de)
WO (1) WO1997004399A2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5996020A (en) 1995-07-21 1999-11-30 National Security Agency Multiple level minimum logic network
US6289021B1 (en) * 1997-01-24 2001-09-11 Interactic Holdings, Llc Scaleable low-latency switch for usage in an interconnect structure
US6754207B1 (en) * 1998-01-20 2004-06-22 Interactic Holdings, Llc Multiple-path wormhole interconnect
US6661816B2 (en) 1998-06-11 2003-12-09 University Of Central Florida Multiwavelength modelocked lasers
US6314115B1 (en) 1998-05-15 2001-11-06 University Of Central Florida Hybrid WDM-TDM optical communication and data link
US6801551B1 (en) 1998-05-15 2004-10-05 University Of Central Florida Programmable multiwavelength modelocked laser
US6247061B1 (en) * 1998-06-09 2001-06-12 Microsoft Corporation Method and computer program product for scheduling network communication packets originating from different flows having unique service requirements
US6807667B1 (en) * 1998-09-21 2004-10-19 Microsoft Corporation Method and system of an application program interface for abstracting network traffic control components to application programs
US6842788B1 (en) * 2000-10-11 2005-01-11 Nortel Networks Limited Computing and using resource colors for composite links
US7016363B1 (en) * 2000-10-19 2006-03-21 Interactic Holdings, Llc Scaleable interconnect structure utilizing quality-of-service handling
US7221677B1 (en) * 2000-10-19 2007-05-22 Interactic Holdings, Llc Scalable apparatus and method for increasing throughput in multiple level minimum logic networks using a plurality of control lines
US20030035371A1 (en) * 2001-07-31 2003-02-20 Coke Reed Means and apparatus for a scaleable congestion free switching system with intelligent control
KR20070007769A (ko) * 2003-10-29 2007-01-16 인터랙틱 홀딩스 엘엘시 에러 정정을 이용하는 높은 병렬 스위칭 시스템
US20050132089A1 (en) * 2003-12-12 2005-06-16 Octigabay Systems Corporation Directly connected low latency network and interface
DE602005020756D1 (de) * 2004-03-08 2010-06-02 Interactic Holdings Llc Hochparallele schaltsysteme mit fehlerkorrektur ii
US20060171386A1 (en) * 2004-09-01 2006-08-03 Interactic Holdings, Llc Means and apparatus for a scaleable congestion free switching system with intelligent control III
WO2006069197A2 (en) * 2004-12-20 2006-06-29 Interactic Holdings, Llc Scaleable controlled interconnect with optical and wireless applications
US8559443B2 (en) 2005-07-22 2013-10-15 Marvell International Ltd. Efficient message switching in a switching apparatus
US20070076761A1 (en) * 2005-09-15 2007-04-05 Coke Reed Apparatus for interconnecting multiple devices to a synchronous device
US7895560B2 (en) * 2006-10-02 2011-02-22 William Stuart Lovell Continuous flow instant logic binary circuitry actively structured by code-generated pass transistor interconnects
KR20090110291A (ko) 2006-10-26 2009-10-21 인터랙틱 홀딩스 엘엘시 병렬 컴퓨팅시스템을 위한 네트워크 인터페이스 카드
US7957400B2 (en) * 2009-03-26 2011-06-07 Terascale Supercomputing Inc. Hierarchical network topology
US20100250784A1 (en) * 2009-03-26 2010-09-30 Terascale Supercomputing Inc. Addressing Scheme and Message Routing for a Networked Device
US7957385B2 (en) * 2009-03-26 2011-06-07 Terascale Supercomputing Inc. Method and apparatus for packet routing
WO2016054264A1 (en) 2014-09-30 2016-04-07 Interactic Holdings, Llc Matrix vector multiply techniques
WO2016057783A1 (en) 2014-10-08 2016-04-14 Interactic Holdings, Llc Fast fourier transform using a distributed computing system
CA3123224C (en) 2018-12-12 2023-10-31 Interactic Holdings, Llc Method and apparatus for improved data transfer between processor cores

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814980A (en) * 1986-04-01 1989-03-21 California Institute Of Technology Concurrent hypercube system with improved message passing
US4933836A (en) * 1986-10-29 1990-06-12 United Technologies Corporation n-Dimensional modular multiprocessor lattice architecture
JP2509947B2 (ja) * 1987-08-19 1996-06-26 富士通株式会社 ネットワ−ク制御方式
US5339396A (en) * 1987-11-18 1994-08-16 Hitachi, Ltd. Interconnection network and crossbar switch for the same
US5181017A (en) * 1989-07-27 1993-01-19 Ibm Corporation Adaptive routing in a parallel computing system
DE69029239T2 (de) * 1989-09-18 1997-03-27 Fujitsu Ltd Übertragungsteuerungssystem zwischen Parallelrechnern
US5313590A (en) * 1990-01-05 1994-05-17 Maspar Computer Corporation System having fixedly priorized and grouped by positions I/O lines for interconnecting router elements in plurality of stages within parrallel computer
US5253248A (en) * 1990-07-03 1993-10-12 At&T Bell Laboratories Congestion control for connectionless traffic in data networks via alternate routing
US5471623A (en) * 1991-02-26 1995-11-28 Napolitano, Jr.; Leonard M. Lambda network having 2m-1 nodes in each of m stages with each node coupled to four other nodes for bidirectional routing of data packets between nodes
US5224100A (en) * 1991-05-09 1993-06-29 David Sarnoff Research Center, Inc. Routing technique for a hierarchical interprocessor-communication network between massively-parallel processors
US5524082A (en) * 1991-06-28 1996-06-04 International Business Machines Corporation Redundancy removal using quasi-algebraic methods
JPH0581216A (ja) * 1991-09-20 1993-04-02 Hitachi Ltd 並列プロセツサ
US5533198A (en) * 1992-11-30 1996-07-02 Cray Research, Inc. Direction order priority routing of packets between nodes in a networked system
DE4307174A1 (de) * 1993-03-08 1994-09-15 Philips Patentverwaltung Lokales Netzwerk
US5617413A (en) * 1993-08-18 1997-04-01 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Scalable wrap-around shuffle exchange network with deflection routing
US5546596A (en) * 1993-08-24 1996-08-13 Intel Corporation Method and apparatus for integrated local and express routing in a multiprocessor
GB9323329D0 (en) * 1993-11-11 1994-01-05 Philips Electronics Uk Ltd Communications system
US5583990A (en) * 1993-12-10 1996-12-10 Cray Research, Inc. System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel
US5485455A (en) * 1994-01-28 1996-01-16 Cabletron Systems, Inc. Network having secure fast packet switching and guaranteed quality of service
US5544163A (en) * 1994-03-08 1996-08-06 Excel, Inc. Expandable telecommunications system
EP0691769A1 (de) * 1994-07-07 1996-01-10 International Business Machines Corporation System zur Emulation geschalteter Sprachverbindungen in einem Paketvermittlungsnetz
US5781551A (en) * 1994-09-15 1998-07-14 Texas Instruments Incorporated Computer communications system with tree architecture and communications method
US5606551A (en) * 1994-12-21 1997-02-25 Lucent Technologies Inc. Bidirectional mesh network
US5684959A (en) * 1995-04-19 1997-11-04 Hewlett-Packard Company Method for determining topology of a network
US5577029A (en) * 1995-05-04 1996-11-19 Interwave Communications Cellular communication network having intelligent switching nodes
US6578010B1 (en) * 1995-06-05 2003-06-10 George A. Teacherson Multi-node network marketing computer system
US5996020A (en) * 1995-07-21 1999-11-30 National Security Agency Multiple level minimum logic network

Also Published As

Publication number Publication date
US20070186008A1 (en) 2007-08-09
CA2227271A1 (en) 1997-02-06
WO1997004399A2 (en) 1997-02-06
MX9800626A (es) 1998-11-30
US6272141B1 (en) 2001-08-07
EP0842473B1 (de) 2006-05-24
ES2160556T1 (es) 2001-11-16
GR20010300054T1 (en) 2001-10-31
DE1058195T1 (de) 2001-10-25
US5996020A (en) 1999-11-30
CA2227271C (en) 2002-12-31
ATE327537T1 (de) 2006-06-15
DE69636165D1 (de) 2006-06-29
KR19990035759A (ko) 1999-05-25
EP0842473A2 (de) 1998-05-20
EP1058195A2 (de) 2000-12-06
JP2000500253A (ja) 2000-01-11
US7068671B2 (en) 2006-06-27
US7426214B2 (en) 2008-09-16
EP1058194A3 (de) 2010-03-10
US20010034798A1 (en) 2001-10-25
EP1058194A2 (de) 2000-12-06
US20010021192A1 (en) 2001-09-13
AU6498896A (en) 1997-02-18
KR100401682B1 (ko) 2004-02-05
NZ313016A (en) 2000-05-26
NZ503094A (en) 2001-11-30
EP1058195A3 (de) 2010-03-10
AU725826B2 (en) 2000-10-19
HK1010926A1 (en) 1999-07-02
WO1997004399A3 (en) 1997-04-10

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