JP3589861B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a technique effectively applied to drive a signal line having a large load such as a word line of a memory at a high speed.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the increase in memory integration, the number of memory cells connected to word lines and bit lines has increased, and stray capacitances of word lines and bit lines have increased. In order to shorten the memory access time, it is important to reduce the charge / discharge time of these stray capacitances. For this reason, in a bipolar RAM (Random Access Memory), many high-speed word line discharge circuits as described in JP-A-59-132490 have been proposed. However, these discharge circuits are of a circuit type in which a current is always supplied to the word line when the signal of the word line is at a high potential, so that the potential of the word line is reduced.
[0003]
In order to solve this problem, the inventors have already proposed a semiconductor integrated circuit shown in FIG. 7 (Japanese Patent Laid-Open No. Hei 2-265095). In the figure, W is a word line, QW is a word line driving transistor, QDC is a discharging transistor, MN is a switching MOS transistor for controlling on / off of the discharging transistor QDC, and IDC is a current source for discharging current. And the emitters of the plurality of discharging transistors QDC are connected. DR is a logic gate for driving the word line driving transistor QW and the switching MOS transistor MN. Here, the logic gate DR shows an ECL (Emitter Coupled Logic) circuit that outputs complementary signals (OR, NOR) as an example. The output signal NOR drives the word line driving transistor QW, and the output signal OR drives the switching MOS transistor MN.
[0004]
FIG. 8 shows the operating potential of the conventional circuit. The operation of the conventional circuit will be described with reference to FIGS. The conditions are as follows: the signal amplitude of the word line is 2 V, the signal amplitude of the complementary output of the logic gate is 2 V, the base-emitter voltage of the bipolar transistor is 0.8 V, and the withstand voltage of the MOS transistor is 3.0 V. Here, when the inputs XD1 and XD2 of the logic gate DR are at a low potential (for example, -2.8V), the word line W is at a high potential (-0.8V), and the gate of the MOS transistor MN is at a low potential (-2.0V). ), The discharge transistor QDC is also turned off, and no discharge current flows to the word line. On the other hand, when the word line W switches from the high potential to the low potential and when the word line is at the low potential (−2.8 V), the MOS transistor MN is driven at the high potential (0 V) and turned on. QDC is also turned on, and a discharge current flows to the word line.
[0005]
As described above, when the word line is at a high potential, no discharge current flows through the word line, so that there is no problem that the potential of the selected word line decreases. In addition, since the discharge current flows when the word line switches from the high potential to the low potential, the switching of the word line from the high potential to the low potential can be speeded up.
[0006]
[Problems to be solved by the invention]
However, as shown in FIG. 8, in the conventional semiconductor integrated circuit, when the word line W is at a low potential (−2.8 V), the voltage applied between the gate and the drain of the MOS transistor MN is as large as 2.8 V. On the other hand, there is no problem if the withstand voltage of the MOS transistor is 2.8 V or more. However, in recent years, there is a tendency to reduce the thickness of the gate oxide film in order to improve the load driving performance of the MOS transistor (to speed up the switching operation). Accordingly, the withstand voltage of the MOS transistor tends to decrease. For example, when the withstand voltage of the MOS transistor is 2.8 V or less, it becomes difficult to use the conventional semiconductor integrated circuit having the configuration shown in FIG. As a countermeasure, there is a method of reducing the signal amplitude of the word line, but in this case, it is difficult to speed up the write characteristics of the memory cell. It is also possible to adopt a special high withstand structure only for some MOS transistors such as MN, but this requires a complicated manufacturing process such as an increase in the number of photomasks used for manufacturing. It is advisable to take process measures only when circuit measures cannot be taken.
[0007]
The above-described configuration of the word line discharge by the MOS transistor MN is also employed in the configuration of the discharge to the control line of the column switch for selecting the bit line. In this case, there is also the problem of the withstand voltage of the switch MOS transistor as described above.
[0008]
An object of the present invention is to reduce the signal amplitude of a signal line such as a word line without reducing the signal level of a control signal of a switch for selectively discharging a signal line lower than the withstand voltage of the switch, and It is to ensure that no discharge current flows through the signal line during the non-discharge period of the signal line.
[0009]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0011]
That is, a first bipolar transistor (QDC) having an emitter connected to the current source (IDC), a collector connected to the load (W), and one end connected to the load and the other end connected to the base of the transistor. A logic circuit (DR) that controls a current flowing to the load via the first bipolar transistor by controlling on / off of the switch. A level shift circuit (LS) for receiving an output of the circuit is provided, and an output of the level shift circuit is connected to a control terminal of the switch. The switch can employ a first MOS transistor (MN). The load is a signal line such as a word line to which a selection terminal of a memory cell is connected or a selection control line of a column switch for selecting a bit line to which a data terminal of the memory cell is connected. The level shift circuit includes, for example, a second MOS transistor (MN2) disposed between an output of the logic circuit and a control terminal of a switch, and a diode (QD) having an anode connected to the control terminal of the switch. And a bias current source (IDC2) connected to the cathode of the diode. The diode can be replaced by a so-called diode-connected third MOS transistor having its own drain and gate connected.
[0012]
According to the above means, the signal level of the switch control signal for selectively discharging the signal line such as the word line is lowered by the level shift circuit, and the gate / drain of the switch such as the first MOS transistor is lowered. It works so that the inter-voltage is lower than the withstand voltage of the transistor. At this time, it is not necessary to reduce the signal amplitude of a signal line such as a word line. Since it is guaranteed that no discharge current flows through the signal line during the non-discharge period of the signal line, the potential of the signal line set to the selected level is not changed, as represented by the word line driven to the selected level. There is no problem of a desired reduction. Further, when a signal line represented by a word line switches from a high potential which is a selection level to a low potential which is a non-selection level, a discharge current flows through the first bipolar transistor. Switching of the line from a high potential to a low potential (that is, a selected level to a non-selected level) can be speeded up. Therefore, when the present invention is applied to a word line of a semiconductor memory, the access time of the memory can be reduced.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 6 shows a semiconductor memory such as a bipolar RAM as an example of a semiconductor integrated circuit according to the present invention. The semiconductor memory 1 shown in FIG. 1 includes a memory cell array 2, a row decoder and word driver 3, a row address buffer 4, a sense circuit 5, a column decoder and driver 6, a column address buffer 7, a read / write control circuit 8, and an output buffer 9. Having. The memory cell array 2 has a large number of memory cells whose selection terminals are connected to word lines and whose data input / output terminals are connected to complementary bit lines, and these memory cells are arranged in a matrix. The row address buffer 4 converts the row address signal into an internal complementary address signal, and the row decoder and the word driver 3 receiving the signal decode the internal complementary address signal and drive the word line selected thereby to a selected level. The column address buffer 7 converts the column address signal into an internal complementary address signal, which is decoded by the column decoder and driver 6. The complementary bit line is selected according to the result of decoding by the column decoder and driver 6. Thus, the memory cell specified by the row address signal and the column address signal is selected.
[0014]
The read / write control circuit performs read or write control on the selected memory cell in response to a write enable signal WEb and a data input signal DI. The signal read from the selected memory cell is output to the outside of the memory as a data output signal DO via the sense circuit 5 and the output buffer 9. The chip selection signal CSb inhibits reading and writing via the read / write control circuit 8 and the output buffer 9 when the chip is not selected.
[0015]
Although DI and DO are shown as one bit in the example of FIG. 6, it is understood that the memory cell array 2 is actually divided into a plurality of groups, and DI and DO are provided for each group. I want to be.
[0016]
The semiconductor memory 1 is formed on one semiconductor substrate such as single crystal silicon.
[0017]
FIG. 1 shows a detailed example of a word line drive circuit in the semiconductor memory of FIG. The word line drive circuit is incorporated in the row decoder and word driver 3, and FIG. 1 illustrates a configuration for one word line. A level shift circuit LS is added as compared with the configuration of FIG.
[0018]
In FIG. 1, W is a word line, QW is a word line driving transistor (npn bipolar transistor), QDC is a discharging transistor (npn bipolar transistor), and MN is an n-channel type that controls on / off of the discharging transistor QDC. The switching MOS transistor IDC is a current source for discharging current, and the emitters of a plurality of discharging transistors QDC are connected. DR is a logic gate as a logic circuit for driving the word line driving transistor QW and the switching MOS transistor MN. The logic gate DR is shown as an ECL (Emitter Coupled Logic) circuit that outputs complementary signals (OR, NOR). That is, the logic gate DR is composed of npn-type bipolar transistors Q1 to Q3, load resistors RCL and RCR, and a current source ICS, and calculates a logical sum and a negative logical sum with respect to the inputs XD1 and XD2. Are output as signals OR and NOR. Then, the word line driving transistor QW is driven by the output signal NOR, and the switching MOS transistor MN is driven by the output signal ORs of the level shift circuit LS receiving the output signal OR. The signals XD1 and XD2 can be positioned as decode signals of a row address signal corresponding to one word line W, and are not particularly limited, but the signal amplitude is -2.8V to -2.2V. .
[0019]
The configuration of the level shift circuit LS will be described. MN2 is a MOS transistor, QD is a diode, and IDC2 is a bias current source. Here, the source (or drain) of the MOS transistor MN2 is connected to the output signal OR output of the logic gate DR, the drain (or source) is connected to the gate of the switching MOS transistor MN, and the gate is ground GND. It is connected to the. The output signal of the level shift circuit LS is shown as ORs. The drain (or source) of the MOS transistor MN2 is connected to the anode of a diode QD, and the bias current source IDC2 is connected to a plurality of cathodes of the diode QD.
[0020]
FIG. 2 shows an example of the operating potential of the circuit of FIG. The operation of the level circuit LS will be described with reference to FIGS. The conditions are as follows: the signal amplitude of the word line W is 2 V, the signal amplitude of the complementary outputs OR and NOR of the logic gate DR is 2 V, and the base-emitter voltage of the bipolar transistor is 0.8 V. This is the same as in the conventional example, but it is assumed that the withstand voltage of the MOS transistor is reduced from 3.0 V in the prior art to 2.0 V.
[0021]
Here, when the inputs XD1 and XD2 of the logic gate DR have a low potential (for example, -2.8 V), the word line W has a high potential (-0.8 V). Further, the output signal OR of the logic gate DR becomes low potential (−2.0 V) by the drive current ICS of the logic gate DR. At the same time, the gate potential (level of the output signal ORs) of the switching MOS transistor MN becomes low potential (−2.0 V) because it is discharged by the driving current ICS through the MOS transistor MN2. Therefore, since the switching MOS transistor MN is turned off, the discharging transistor QDC is also turned off, and no discharging current flows to the word line.
[0022]
On the other hand, when the word line W switches from the high potential to the low potential and when the word line is at the low potential (−2.8 V), the output signal OR of the logic gate DR becomes the high potential (0 V). At this time, a potential difference corresponding to the threshold voltage of the MOS transistor MN2 of 0.8 V is generated between the gate and the source of the MOS transistor MN2 due to the bias current IDC2. Therefore, the gate level (level of the output signal ORs) of the switching MOS transistor MN becomes a high potential (-0.8 V). Here, in the case of the conventional example, since the gate potential of the switching MOS transistor MN is 0 V, the voltage applied between the gate and the drain is 2.8 V, which cannot satisfy the withstand voltage of the MOS transistor of 2.0 V. . However, if the configuration of FIG. 1 is adopted, the voltage applied between the gate and the drain of the switching MOS transistor MN is 2.0 V, so that the withstand voltage of 2.0 V can be satisfied. Also in this case, since the switching MOS transistor MN is turned on, the discharging transistor QDC is also turned on, and a discharging current flows to the word line.
[0023]
As described above, according to the configuration of FIG. 1, the voltage applied between the gate and the drain of the switching MOS transistor MN is 2.0 V, which can satisfy the withstand voltage of the MOS transistor of 2.0 V. In addition, when the word line is at a high potential, the discharge current does not flow through the word line, and there is no problem that the potential of the selected word line decreases. Further, when a word line switches from a high potential to a low potential, a discharge current flows, so that the switching of the word line from a high potential to a low potential can be speeded up.
[0024]
The diode QD is replaced with a so-called diode-connected MOS transistor having its own gate and drain short-circuited, and a bias current source (or any voltage source) is connected to the source of the MOS transistor. May be.
[0025]
FIG. 3 shows still another example of the word line drive circuit in the semiconductor memory of FIG. The configuration of FIG. 3 is different from that of FIG. 1 in the configuration of the level shift circuit LS. In the level shift circuit LS shown in FIG. 3, the base of the npn-type bipolar transistor QEF receives the output signal OR of the logic gate DR, the emitter is connected to the current source IDC3, and the signal ORs is output from the emitter. That is, the gate of the switching MOS transistor MN is driven by the emitter follower circuit. In this configuration, the same number of current sources IDC3 as the number of word lines are required, and it should be noted that when the number of word lines is large, the current consumption due to the emitter follower current increases. According to the circuit configuration of FIG. 3, the high potential of the gate (ORs output) of the switching MOS transistor MN is set to −0. 8V, and the same operation and effect can be obtained.
[0026]
Note that the current source IDC3 may be a resistor. Further, a diode-connected MOS transistor may be used, and the transistor QEF may have a configuration in which the gate and the drain are connected to the emitter, and an arbitrary voltage source is connected to the source. Also, in order to reduce the current consumption due to the emitter follower current, the emitter follower current may be reduced as much as possible, and a configuration may be adopted in which a speed-up capacitor is provided between the base and the emitter.
[0027]
FIG. 4 shows still another example of the level shift circuit LS. The circuit configuration of FIG. 4 is almost the same as the circuit configuration of FIG. The difference is that an n-channel MOS transistor MN3 is newly provided. The drain of the MOS transistor MN3 is connected to the base of the discharging transistor QDC, the gate is connected to the word line W, and the source is connected to an arbitrary voltage source (for example, a -3V voltage source).
[0028]
It is clear that the same operation and effect as those of FIG. 1 can be obtained in the configuration of FIG. Further, when the word line W is at a high potential, the MOS transistor MN3 is turned on, so that the base of the discharging transistor QDC has low impedance and noise resistance is enhanced. That is, when the word line W is at a high potential, for example, in the circuit configuration of FIG. 1, the source from the MOS transistor MN to the base of the transistor QDC is in a floating state (high impedance state), and the transistor QDC May be undesirably increased. On the other hand, in the configuration of FIG. 4, when the word line W is at a high potential, the source of the MOS transistor MN is connected to a power source such as -3 V by the MOS transistor MN3 from the source of the MOS transistor MN3 to be in a low impedance state. Therefore, it is hardly affected by noise due to crosstalk. The MOS transistor MN3 can be applied to the circuit configuration shown in FIG.
[0029]
FIG. 5 shows another example of the level shift circuit LS. In the circuit configuration described so far, the logic gate DR is a circuit that generates a complementary output. On the other hand, in FIG. 5, the output of the logic gate DR is a signal OR of one polarity. In this case, the output signal OR of the logic gate DR is input to the level shift circuit LS as in the above-described circuit configuration. However, as is clear from the description of FIGS. 1 to 4, the word line driving transistor QW needs to be driven by a signal having a polarity opposite to that of the input of the level shift circuit LS. Therefore, the output signal OR output of the logic gate DR is inverted by the inverter INV to drive the word line driving transistor QW. The inverter INV is, for example, an inverter formed of complementary MOS transistors. As described above, the word line driving transistor QW and the level shift circuit LS can be driven under the same conditions as the configuration in FIG. Therefore, the same operation and effect as in the case where the circuit configuration of FIG. 1 is adopted can be obtained.
[0030]
Although the MOS transistor shown in the above-described circuit is an n-channel type and the bipolar transistor is an npn type, the conductivity type of the transistor is not limited thereto and can be changed as appropriate with the circuit configuration. In the above description, an example in which the present invention is applied to a word line discharge circuit of a memory has been described. However, the present invention is not limited to this, and can be similarly applied to a circuit that drives a large load. For example, the present invention can be applied to a circuit for driving a control line of a switch transistor for selectively connecting a complementary bit line to a sense circuit. The present invention is not limited to the case where the present invention is applied to a bipolar RAM, but can be widely applied to a semiconductor memory on-chip in a logic LSI such as a MOS memory and a microcomputer.
[0031]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
[0032]
That is, the signal level of the control signal of the switch for selectively discharging the signal line such as the word line can be reduced by the level shift circuit without reducing the signal amplitude of the signal line such as the word line. The gate-drain voltage of a switch such as the MOS transistor can be made lower than the withstand voltage of the transistor. Since it is guaranteed that no discharge current flows through the signal line during the non-discharge period of the signal line, the potential of the signal line set to the selected level is not changed, as represented by the word line driven to the selected level. There is no problem of a desired reduction. Further, when a signal line represented by a word line switches from a high potential which is a selected level to a low potential which is a non-selected level, a discharge current flows through the first MOS transistor. Switching of the line from a high potential to a low potential (that is, a selected level to a non-selected level) can be speeded up. Therefore, when the present invention is applied to a word line of a semiconductor memory, the access time of the memory can be reduced.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first example of a level shift circuit of a word line drive circuit included in a semiconductor memory such as a bipolar RAM, which is an example of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a potential diagram showing an example of an operating potential of the circuit of FIG.
FIG. 3 is a circuit diagram showing a second example in which an emitter follower circuit is used for a level shift circuit included in a word line drive circuit.
FIG. 4 is a circuit diagram showing another example of the word line discharge circuit included in the word line drive circuit.
FIG. 5 is a circuit diagram showing another example of the logic circuit included in the word line drive circuit.
FIG. 6 is a block diagram generally showing a semiconductor memory such as a bipolar RAM as an example of a semiconductor integrated circuit according to the present invention.
FIG. 7 is a circuit diagram showing an example of a conventional word line drive circuit.
FIG. 8 is a potential diagram showing an operating potential of the circuit shown in FIG. 7;
[Explanation of symbols]
LS Level shift circuit MN Switching MOS transistor W Word line QW Word line driving transistor QDC Discharging transistor IDC Discharge current source DR Logic gate 1 Semiconductor memory 2 Memory cell array 3 Row decoder and word driver

Claims (2)

A semiconductor integrated circuit including a switch circuit connected to each of the plurality of signal lines to selectively discharge and drive one of the plurality of signal lines to a low potential, wherein each of the switch circuits is
A first bipolar transistor for charging a corresponding one of the plurality of signal lines, a collector connected to the high potential power supply, and an emitter connected to the corresponding one of the plurality of signal lines;
A second bipolar transistor for discharging the corresponding signal line whose emitter is connected to a common current source and whose collector is connected to the corresponding signal line;
A switch having one end connected to the corresponding signal line and the other end connected to the base of the second bipolar transistor;
A positive output terminal for controlling a discharge operation of the corresponding signal line via the second bipolar transistor by controlling on / off of the switch; and controlling on / off of the first bipolar transistor by controlling on / off of the first bipolar transistor. A logic circuit having a negative output terminal for controlling the charging operation of the corresponding signal line,
A MOS transistor disposed between the positive output terminal of the logic circuit and the control terminal of the switch, and a diode having an anode connected to the control terminal of the switch and a cathode connected to a common bias current source. And a level shift circuit configured. 2. The semiconductor according to claim 1, wherein the diode is constituted by a second MOS transistor having a drain and a gate connected to a control terminal of the switch, and a source connected to the common bias current source. Integrated circuit.

Images