JP3586993B2 - Semiconductor nonvolatile storage device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor nonvolatile memory device such as a NAND flash memory which performs a page program in word line units.
[0002]
[Prior art]
In a semiconductor nonvolatile memory device such as a NAND flash memory or a DINOR flash memory, data programming is performed on all memory transistors connected to a selected word line at a time.
That is, the page program is performed for each word line.
[0003]
FIGS. 4A and 4B are diagrams showing memory array structures in NAND type and DINOR type flash memories, respectively.
[0004]
The NAND flash memory of FIG. 4A is a diagram showing a memory array in which four memory transistors are connected to one NAND string connected to one bit line for convenience.
In FIG. 4A, BL indicates a bit line, and a NAND string in which two selection transistors ST1 and ST2 and four memory transistors MT1 to MT4 are connected in series is connected to the bit line BL. .
The select transistors ST1 and ST2 are controlled by select gate lines SL1 and SL2, respectively, and the memory transistors MT1 and MT4 are controlled by word lines WL1 and WL4, respectively.
[0005]
The DINOR type flash memory shown in FIG. 4B is a diagram showing a memory array when four memory transistors are connected to one sub-bit line connected to one main bit line for convenience.
In FIG. 4B, MBL indicates a main bit line, and SBL indicates a sub-bit line. These main bit line MBL and sub-bit line SBL are connected via a select transistor ST1 controlled by a select gate line SL. You.
The sub-bit line SBL intersects with the four word lines WL1 to WL4, and four memory transistors MT1 to MT4 are arranged at each intersection.
[0006]
[Problems to be solved by the invention]
By the way, in a nonvolatile semiconductor memory device such as the above-mentioned NAND type, DINOR type flash memory, etc., which performs page programming in units of word line sectors, data programming is performed as follows.
That is, a data latch circuit for temporarily latching page program data is provided for each bit line (or main bit line), a data transfer step of transferring page program data to the data latch circuit, and a selection according to the page program data. Data programming is performed by continuously performing a two-step process of a data programming process of performing a page program on the memory transistors connected to the word line at a time.
[0007]
FIG. 5 is a diagram showing a timing chart at the time of data programming of the above-described conventional semiconductor nonvolatile memory device which performs page programming in units of word line sectors, for example, a NAND flash memory.
[0008]
In FIG. 5, a period from time t1 to t3 is a step of performing the first page program.
First, at time t1 to t2, the first page program data [D1] 1 to [D1] m are transferred to the data latch circuit of each bit line in synchronization with the data transfer clock signal φCL. Here, in the case of a general NAND flash memory, the page size is usually 512 bytes, and the data transfer is also performed in byte units. Therefore, the number of pulses of the data transfer clock signal φCL is generally m = 512. .
Next, from time t2 to time t3, the first page program data [D1] 1 to [D1] m are synchronized with the data program signal φPRG to collectively perform page programming on the memory transistors connected to the first selected word line. I do.
[0009]
Similarly, during the period from time t3 to time t5, the second page program is performed, and the second page program data [D2] 1 to [D2] m are connected to the second selected word line. The page program is performed on the memory transistors at once.
Similarly, the period from time t5 to t7 is a step of performing the third page program, and the third page program data [D3] 1 to [D3] m are connected to the third selected word line. The page program is performed on the memory transistors at once.
[0010]
In the data programming operation of such a conventional NAND flash memory, the data programming for each page is divided into two steps of a data transfer process and a data programming process.
In the case of a general NAND flash memory, the data transfer clock signal φCL is driven 512 times by a burst pulse of about 100 nanoseconds, so that the time required for the data transfer is about 50 microseconds.
On the other hand, in the case of a general NAND flash memory, the time required for data programming for one page is about 200 microseconds because a pulse of about 40 microseconds is applied by applying several pulses.
[0011]
Therefore, in the case of the above-described conventional NAND flash memory, the time required to transfer the program data occupies a considerable proportion of the actual data programming time, and the actual data programming speed is sacrificed.
Further, as the capacity of the NAND flash memory increases in the future, the page size may inevitably increase. In that case, it is expected that the actual data programming time and the time required for the transfer of the program data will be about the same.
Further, in the case of the above-described conventional NAND flash memory, for example, in a case where a page program is continuously performed over a plurality of page regions as in an application example for recording image information data, the plurality of page program data are continuously stored. It is impossible to transfer the data to the NAND flash memory in synchronization with the burst pulse, and it is necessary to divide and transfer each page program data.
In the case of a general NAND flash memory, the division transfer for each page program data is performed under the control of an external controller.
Therefore, there is a disadvantage that the data program operation cannot be performed without the control of the external controller.
[0012]
The present invention has been made in view of the above circumstances, and an object of the present invention is to increase the speed of data programming in a semiconductor nonvolatile memory device that performs page programming in units of word lines, and furthermore, without controlling an external controller. An object of the present invention is to provide a semiconductor nonvolatile memory device capable of performing a data program.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor nonvolatile memory device according to the present invention includes a data transfer step of transferring page program data in units of word lines to a data latch circuit provided for each bit line, and selecting according to the page program data. By continuously performing a data programming process of performing a page program on memory transistors connected to a word line at a time, a first memory array in which memory transistors electrically performing data programming in page units are arranged in a matrix. (A) a data transfer step of transferring page program data for each word line to a data latch circuit provided for each bit line, and performing a page program for memory transistors connected to the selected word line in accordance with the page program data Continue the data programming process By performing the data to the second memory array and, wherein the data transfer to the first memory array a second memory array in which memory transistors electrically data programs page by page is carried out are arranged in a matrix The first memory array and the second memory are simultaneously and alternately repeated by repeatedly performing a step of simultaneously performing a program and a step of simultaneously performing data transfer to the second memory array and data programming to the first memory array. Means for executing a data program for the array in parallel.
[0014]
In the semiconductor nonvolatile memory device, data transfer of page program data to the first memory array and data transfer of page program data to the second memory array are continuously performed in synchronization with a predetermined clock pulse. Done.
[0015]
According to the semiconductor nonvolatile memory device of the present invention, the semiconductor memory device includes two memory arrays that are paired with each other and are page-programmed in units of word lines, and a data transfer operation and a data program are performed on the two memory arrays. The operations take place mutually and in parallel.
Therefore, data programming can be performed at twice the normal speed.
[0016]
Further, according to the semiconductor nonvolatile memory device of the present invention, data transfer of page program data to the two memory arrays is continuously performed in synchronization with a fixed clock pulse.
Therefore, even when a page program is continuously performed over a plurality of page areas, there is no need to divide and transfer each page program data. As a result, the data program operation is possible without the control of the external controller, which is preferable.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a diagram showing a specific configuration example of a semiconductor nonvolatile memory device according to the present invention, for example, a NAND flash memory.
[0018]
In FIG. 1, reference numeral 10 denotes a first memory array. The first memory array 10 includes a memory array main body 11, a row decoder 12, and a data latch provided with data latch circuits SAa1 to SAam for each bit line. It is composed of a circuit group 13 and a column selection unit 14.
Further, m (about 1024 bytes to 2048 bytes in this embodiment) bit lines B1 to Bm are wired in the memory array main body 11. FIG. 1 illustrates a case where a word line WLn is selected and page programming is performed on the memory transistors MTn, 1 to MTn, m.
[0019]
Similarly, reference numeral 20 denotes a second memory array. The second memory array 20 includes a memory array main body 21, a row decoder 22, and a data latch circuit provided with data latch circuits SAb1 to SAbm for each bit line. It comprises a group 23 and a column selection unit 24.
Similarly, m (about 1024 bytes to 2048 bytes in this embodiment) bit lines B1 to Bm are wired in the memory array main body 21. FIG. 1 illustrates a case where a word line WLn is selected and page programming is performed on the memory transistors MTn, 1 to MTn, m.
[0020]
Reference numeral 30 denotes a program data input circuit. The program data input circuit 30 is a page program to be programmed in the first memory array 10 from an external data bus to a data bus inside the chip in synchronization with the basic data transfer clock signal φCL. The data [Da] and the page program data [Db] to be programmed in the second memory array 20 are alternately and continuously transferred.
[0021]
Reference numeral 40 denotes a control circuit. The control circuit 40 receives the basic data transfer clock signal φCL and receives a first data transfer clock signal φCLa, a second data transfer clock signal φCLb, a first data program signal φPRGa, And four types of data program signal φPRGb.
[0022]
The first data transfer clock signal φCLa is supplied to the column selection unit 14, and the operation of the column selection unit 14 in synchronization with the first data transfer clock signal φCLa causes the data latch circuits SAa <b> 1 to SAa <b> 1 in the first memory array 10. The page program data [Da] is shift-transferred to SAam.
Further, the second data transfer clock signal φCLb is supplied to the column selection unit 24, and the data latch circuit SAb1 in the second memory array 20 is operated by the operation of the column selection unit 24 synchronized with the second data transfer clock signal φCLb. Page program data [Db] is shift-transferred to .about.SAbm.
Further, the first data program signal φPRGa is supplied to the first memory array 10, and the first data program signal φPRGa is supplied to the memory transistors MTn, 1 to MTn, m in the first memory array 10 under the control of the first data program signal φPRGa. Thus, the page program data latched by the data latch circuits SAa1 to SAam is programmed.
Further, the second data program signal φPRGb is supplied to the second memory array 20, and the second data program signal φPRGb controls the memory transistors MTn, 1 to MTn, m in the second memory array 20 under the control of the second data program signal φPRGb. Thus, the page program data latched by the data latch circuits SAb1 to SAbm is programmed.
[0023]
FIG. 2 is a diagram showing a specific circuit configuration of the control circuit 40 in the semiconductor nonvolatile memory device of FIG.
[0024]
As shown in FIG. 2, the control circuit 40 includes a frequency dividing circuit 41, inverters INV1 and INV2, and AND gates AND1 to AND4.
The frequency dividing circuit 41 outputs a signal φout obtained by dividing the frequency f of the basic data transfer clock signal φCL by 1/512.
As shown in FIG. 2, the first data transfer clock signal φCLa is generated by ANDing the logical product of the inverted output of the frequency-divided signal φout by the inverter INV1 and the basic data transfer clock signal φCL by the AND gate AND1. .
The second data transfer clock signal φCLb is generated by ANDing the frequency-divided signal φout and the basic data transfer clock signal φCL by the AND gate AND2.
The first data program signal φPRGa is generated by ANDing the frequency-divided signal φout with the program enable signal φPE shown in FIG. 3 by the AND gate AND3.
The second data program signal φPRGb is generated by ANDing the inverted output of the frequency-divided signal φout of the inverter INV2 with the program enable signal φPE shown in FIG. 3 by the AND gate AND4.
[0025]
FIG. 3 is a diagram showing a timing chart of a data program operation in the semiconductor nonvolatile memory device of the present invention.
Hereinafter, the timing chart of FIG. 3 will be described step by step with reference to FIGS.
[0026]
First, at time t1, a data programming operation is started for the semiconductor nonvolatile memory device of FIG. 1, and thereafter, basic data transfer clock signal φCL is continuously output.
In the step between times t1 and t2, the 1a-th page program data [Da1] is shift-transferred to the data latch circuits SAa1 to SAam in the first memory array 10 in synchronization with the first data transfer clock signal φCLa. I do.
[0027]
Next, in a step between times t2 and t3, the 1b-th page program data [Db1] is stored in the data latch circuits SAb1 to SAbm in the second memory array 20 in synchronization with the second data transfer clock signal φCLb. Simultaneously with the shift transfer, the first memory array 10 is programmed with the 1a-th page program data [Da1] in synchronization with the first data program signal φPRGa.
[0028]
Next, in a step between times t3 and t4, the 2a-th page program data [Da2] is supplied to the data latch circuits SAa1 to SAam in the first memory array 10 in synchronization with the first data transfer clock signal φCLa. Simultaneously with the shift transfer, the 1st b page program data [Db1] is programmed in the second memory array 20 in synchronization with the second data program signal φPRGb.
[0029]
Similarly, in the step between times t4 and t5, the 2b-th page program data [Db2] is shift-transferred and, at the same time, the 2a-th page program data [Da2] is programmed.
Similarly, in the step between times t5 and t6, the 3a-th page program data [Da3] is shift-transferred, and at the same time, the 2b-th page program data [Db2] is programmed.
Similarly, in the step between the times t6 and t7, the 3b-th page program data [Db3] is shift-transferred, and at the same time, the 3a-th page program data [Da3] is programmed.
The above timing operation is repeatedly performed until all page programs are completed.
[0030]
As described above, according to the semiconductor nonvolatile memory device of the present invention, the semiconductor memory device includes two memory arrays that are paired with each other and are page-programmed in word line units. Since the data transfer operation and the data program operation are configured to be performed mutually and in parallel, data programming can be performed at twice the normal speed.
Further, according to the semiconductor nonvolatile memory device of the present invention, the data transfer of the page program data is continuously performed to the two memory arrays in synchronization with a constant clock pulse, so that the data transfer is performed over a plurality of page regions. Even in the case where the page program is continuously performed, it is not necessary to divide and transfer each page program data, and therefore, the data program operation can be performed without the control of the external controller, which is preferable.
[0031]
Note that, in the detailed description of the present invention, a case has been mainly described where two memory arrays forming a pair exist in one semiconductor chip, but the two memory arrays forming a pair are separate semiconductor chips. It is needless to say that the present invention can be applied to the case where it is within the range.
[0032]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a semiconductor nonvolatile memory device that can perform a page program in units of word lines at a high speed and can perform a data program without control of an external controller. be able to.
[Brief description of the drawings]
FIG. 1 is a diagram showing a specific configuration example of a semiconductor nonvolatile memory device according to the present invention.
FIG. 2 is a diagram showing a specific circuit configuration of a control circuit in the semiconductor nonvolatile memory device of FIG. 1;
FIG. 3 is a diagram showing a timing chart of a data program operation in the semiconductor nonvolatile memory device of the present invention.
FIG. 4 is a diagram showing a memory array structure in NAND type and DINOR type flash memories.
FIG. 5 is a diagram showing a timing chart of a data programming operation of a conventional nonvolatile semiconductor memory device that performs page programming in units of word line sectors.
[Explanation of symbols]
BL1 to BLm: bit line, WLn: selected word line, MTn, 1 to MTn, m: selected memory transistor, [Da]: first page program data, [Db]: second page program data, φCL: basic Data transfer clock signal, φCLa: first data transfer clock signal, φCLb: second data transfer clock signal, φPRGa: first data program signal, φPRGb: second data program signal, φout: divider circuit output signal , ΦPE: program enable signal, AND1 to AND4, AND gate, INV1 to INV2, inverting circuit, 10: first memory array a, 11: first memory array main unit, 12: row decoder, 13: data latch circuit Group, 14 column selection unit, 20 second memory array, 21 second memory array Ray body section, 22 row decoder, 23 data latch circuit, 24 column selection section, 30 program data input circuit, 40 control circuit, 41 frequency divider circuit.

Claims (7)

A data transfer process of transferring page program data in word line units to a data latch circuit provided for each bit line, and a data program process of performing page program for memory transistors connected to a selected word line in accordance with the page program data by performing in succession, the first and Memoriare Lee memory transistor electrically data program is executed are arranged in a matrix in units of pages,
A data transfer process of transferring page program data in word line units to a data latch circuit provided for each bit line, and a data program process of performing page program for memory transistors connected to a selected word line in accordance with the page program data A second memory array in which memory transistors for electrically programming data in page units are arranged in a matrix,
The step of simultaneously performing the data transfer to the first memory array and the data program to the second memory array and the step of simultaneously performing the data transfer to the second memory array and the data program to the first memory array are alternately performed. A nonvolatile memory device comprising: means for repeatedly executing a data program for the first memory array and the second memory array in parallel. 2. The semiconductor nonvolatile memory device according to claim 1, wherein said first memory array and said second memory array are symmetric. 2. The semiconductor nonvolatile memory device according to claim 1, wherein in the first memory array and the second memory array, the time required for the data transfer process and the time required for the data program process are the same. 2. The semiconductor nonvolatile memory according to claim 1, wherein data transfer of page program data to said first memory array and data transfer of page program data to said second memory array are continuously performed in synchronization with a predetermined clock pulse. Storage device. 2. The semiconductor nonvolatile memory device according to claim 1, wherein the first memory array and the second memory array in which the memory transistors are arranged in a matrix form have a NAND type structure in which memory transistors are connected in series. The first memory array and the second memory array in which the memory transistors are arranged in a matrix form a NOR type structure, and main bit lines are hierarchized into a plurality of sub-bit lines via operative connection means. The nonvolatile semiconductor memory device according to claim 1, wherein: A data transfer process of transferring page program data in word line units to a data latch circuit provided for each bit line, and a data program process of performing page program for memory transistors connected to a selected word line in accordance with the page program data by performing in succession, a first semiconductor chip to the memory transistor electrically data programs page by page is carried out by integrating each memory array arranged in a matrix,
A data transfer process of transferring page program data in word line units to a data latch circuit provided for each bit line, and a data program process of performing page program for memory transistors connected to a selected word line in accordance with the page program data A second semiconductor chip in which memory transistors in each of which a memory transistor in which data is electrically programmed in a page unit are arranged in a matrix are integrated,
Simultaneously performing a data transfer to a memory array in the first semiconductor chip and a data program to a memory array in the second semiconductor chip; a data transfer to a memory array in the second semiconductor chip; The data program for the memory array in the first semiconductor chip and the data program for the memory array in the second semiconductor chip are performed in parallel by alternately repeating the process of simultaneously performing the data program for the memory array in the semiconductor chip. Semiconductor memory system comprising:

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