JP3586946B2 - Semiconductor storage device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and particularly to a layout arrangement of peripheral circuits such as an address buffer circuit and a decoder circuit.
[0002]
[Prior art]
As an example of a peripheral circuit layout arrangement of a conventional semiconductor memory device, there is one disclosed in Japanese Patent Application Laid-Open No. 4-89695. The gist is to arrange the address buffer circuit for receiving the address signal supplied from the external terminal and the predecoder circuit close to each other, thereby shortening the wiring between the address buffer circuit and the predecoder circuit to speed up the signal propagation. That is. FIG. 1 shows the arrangement of pads in a general semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 63-244658.
[0003]
FIG. 5 shows a schematic chip arrangement of a semiconductor memory device using the above-mentioned two conventional techniques. As an example, a schematic chip arrangement of a 1 Mbit SRAM (static random access memory) having a 128K word × 8 bit configuration is shown. Is shown. This semiconductor memory device is sealed in a 32-pin package shown in, for example, EPSON '93 CMOS LSI data books P-85 and P-86, and its terminal arrangement is as shown in the P-81 terminal arrangement diagram. In FIG. 5, although the memory cell is not particularly limited, as an example, it is divided into 16 blocks of 1024 rows × 64 columns of sub-arrays MA1 to MA16, and the bit lines BL and BLb are arranged in the vertical direction of FIG. In the wiring layer, 64 pairs are wired per sub-array, and 1024 word lines SWL are wired in the left-right direction, for example, in a polysilicon wiring layer per sub-array. Further, a sub-word line decoder circuit SWD, a column gate CG, a bit line equalizing circuit BLEQ, a sense amplifier circuit SA, and a block selection circuit SB are arranged in proximity to each sub-array as shown in FIG. A line decoder circuit MWD is provided. Here, a divided word line decoding system composed of a sub word line and a main word line is disclosed in, for example, Japanese Patent Application Laid-Open No. Sho 59-72698. The main word line MWL uses, for example, a second metal wiring layer in the left-right direction of the chip. Wired on the cell. In FIG. 5, X2 and X3 are upper row address circuits, X1 is a lower row address circuit, Z is an upper column address circuit for selecting a block, and Y is a lower column address circuit for selecting a column gate. Placed at Bonding pads are arranged on two sides of the semiconductor memory device so as to conform to the above-described terminal arrangement diagram, as in FIG. 1 of JP-A-63-244658, so that the wiring of the address circuit from the address pad is relatively short. Are connected as shown in FIG. Here, in order to simplify the description, a control circuit, a write / read circuit, and a data output circuit are omitted.
[0004]
FIG. 6 shows a schematic equivalent circuit of FIG. 5. The upper column address circuit Z simply comprises an address buffer circuit comprising inverters 31 and 32 for forming complementary internal address signals, a 4-input NAND 33 and an inverter 34. , And outputs 16 predecode signals PDZ (only one is shown in FIG. 5). The configuration of the address circuits X1, X2, X3, and Y is substantially the same as that of Z, and the description thereof is omitted. However, each address circuit includes predecode signals PDX1 (four), PDX21 / 22, (each eight), PDX3. (4 lines) and PDY (8 lines) are output. Here, in all the address circuits, the address buffer circuit and the predecoder circuit are arranged close to each other. The main word line decoder circuit MWD includes 256 sets of 3-input NANDs to which predecode signals PDX21, PDX22, and PDX3 are input, and an inverter. Here, FIG. 6 illustrates only the NAND 11 and the inverter 12 that select the MWL 1 wired at the top of the chip and the NAND 21 and the inverter 22 that select the MWL 256 wired at the bottom of the chip. The block selection circuit BS is composed of two sets of two-input NANDs to which the predecode signals PDZ and PDX1 are input and four sets of inverters (only one set is described in FIG. 6), and four block row lower signals BX (one in FIG. 6). (Only the book is described). The sub-word line decoder circuit SWD is composed of 1024 sets of 2-input NANDs and inverters to which a main word line MWL and a block row lower signal BX are inputted. In FIG. 6, a NAND 13, which selects a word line SWL1 arranged at the top of the chip, Only the NAND 23 and the inverter 24 that drive the inverter 14 and the word line SWL1024 wired at the bottom of the chip are described. The sub-array MA is a memory cell array of 1024 rows × 64 columns, and a memory cell MC1 (uppermost bit line) to which a pair of bit lines BL and BLb and SWL1 are connected and a memory cell MC2 (bit) to which SWL1024 is connected. Only the bottom of the line) is described. The column gate CG disposed below the bit line selectively connects read data of a memory cell appearing on the bit line to the sense amplifier SA, and the sense amplifier SA performs an operation of amplifying the minute potential difference. Further, the read data is output to the outside of the storage device via an output circuit (not shown).
[0005]
In the conventional device arranged as described above, a wiring to which particularly large parasitic capacitance and parasitic resistance are added in the device is a wiring in a cell array or a repetitive circuit close to the cell array, and includes bit lines BL and BLb and word lines. The line SWL, the main word line MWL, the block row lower signal BX, and the row upper predecode signals PDX21, PDX22, PDX3 form wiring with a large time constant. This is because, in order to reduce the chip size of the device, the wiring width is fined, and the wiring pitch and the interlayer insulating film thickness are reduced, thereby increasing the resistance and line-to-line capacitance. For example, the gate capacitance and the drain capacitance of a repetitive circuit are large. FIG. 6 illustrates a parasitic resistance and a parasitic capacitance component connected to the above-described wiring. For example, the row upper predecode signal PDX21 includes a parasitic resistance R11 and a parasitic capacitance C11 / 12, and the bit lines BL and BLb include Parasitic resistances R15 and R16 and parasitic capacitances C19 to C22 are connected.
[0006]
[Problems to be solved by the invention]
Since the conventional semiconductor memory device is configured as described above, there are the following problems.
[0007]
5 and 6, the delay time from the memory cell to the input of the sense amplifier SA at the time of reading is determined by MC1 (chip) arranged at the uppermost part of the bit line due to the bit line parasitic resistances R15 and R16 and the parasitic capacitances C19 to C22. The top is the slowest, and the MC2 near the sense amplifier (the bottom of the chip) is the fastest. On the other hand, among the row upper predecode signals, PDX21 and PDX22 are slowest on the MWL256 side far from the address circuit X2, and conversely PDX3 is slow on the MWL1 side because the address circuit X3 is arranged at the bottom of the device. Accordingly, the timing from the input of the row upper address circuit X2 or X3 to the selection of the main word line is substantially the same at the top and bottom of the chip, and the selection timing of the word line SWL in the case of row upper address control is wired at the top of the chip. SWL1 and SWL1024 wired below are the slowest. Comparing the delay times from the upper row address input to the sense amplifier input in the memory cells MC1 and MC2, the selection timing of the word line SWL is the same in both cells. , The delay time is increased by the amount of the parasitic capacitance.
[0008]
When the block selection circuit BS in FIG. 6 is arranged on the sense amplifier side as shown in FIG. 1 of Japanese Patent Application Laid-Open No. 4-89695 and FIG. X1, the upper column address circuit Z is arranged at the lower part of the chip), and the block row lower signal BX is slowest on the upper part SWL1 side due to the parasitic resistance R14 and the parasitic capacitances C17 and C18, and the influence on the lower part SWL1024 side is small. . Therefore, for example, when comparing the delay time from the input of the row lower address to the input of the sense amplifier, the MC2 disposed at the lower part of the chip is not affected by the parasitic resistance of both the bit lines BL and BLb and the block row lower signal BX. On the other hand, the delay time of the MC1 arranged on the upper part of the chip is increased due to the influence of the bit lines BL and BLb, the block row lower signal BX, the parasitic resistance and the parasitic capacitance of both wirings. This is the same when the column upper address changes.
[0009]
In the design example of the sub-array configuration of 1024 rows × 64 columns shown in FIG. 5, the difference in the data delay time between the memory cells above and below the chip due to the parasitic resistance and the parasitic capacitance of the bit pair is about 3 ns, The word line delay difference caused by the parasitic resistance and capacitance of the signal BX and the row upper predecode signals PDX21, PDX22, PDX3 is about 2 ns. As described above, in the conventional semiconductor memory device, the influence of the bit line, the parasitic resistance of the predecode signal, and the parasitic capacitance differs depending on the method of selecting the row address and the arrangement position of the memory cell. If both are not affected, the memory cell data output time at the sense amplifier input differs by a maximum of 5 ns. This means that, when viewed from the sense amplifier amplification operation, the input signal potential difference at the start of the sense amplifier operation differs depending on the row address selection method, and there is a danger that the sense amplifier may malfunction, especially when the memory cell data output is slow. For this reason, the operation start timing of the sense amplifier cannot be shortened, which has been an obstacle to speeding up.
[0010]
As described above, in the conventional semiconductor memory device, the access time differs depending on the arrangement position of the memory cell due to the parasitic resistance and the parasitic capacitance in the device. In particular, the data output of the memory cell far from the sense amplifier is slow and the speed is increased. Had a problem that it could not be realized.
[0011]
The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor memory device capable of high-speed operation without delay in access time due to a memory cell arrangement position.
[0012]
[Means for Solving the Problems]
A semiconductor memory device according to the present invention includes: a memory cell array in which a plurality of memory cells are arranged in a matrix; a plurality of word line decoder circuits arranged in close proximity to the memory cell array to select word lines of the memory cells; A sense amplifier circuit which is arranged close to the cell array and amplifies data of a memory cell; a plurality of address buffer circuits for receiving an address signal supplied from an external terminal; and a complementary address signal output from the plurality of address buffer circuits. In a semiconductor memory device including a plurality of predecoder circuits for decoding, an address buffer circuit related to the word line selection and a predecoder related to the word line selection among the plurality of address buffer circuits and the plurality of predecoder circuits. All of the circuits are the memory cell array A semiconductor memory device, characterized in that it is arranged in the opposite region and the region in which the sense amplifiers are disposed across the range.
[0013]
An input buffer circuit comprising a bonding pad provided corresponding to an external address terminal and at least one or more gate circuits arranged in proximity to the bonding pad; Is connected to the input buffer circuit via a relatively long wiring.
[0014]
[Action]
In the semiconductor memory device of the present invention, since all of the address buffer circuit and the predecoder circuit related to the word line selection of the memory cell are arranged on the opposite side of the sense amplifier region across the memory cell array region, the memory cell far from the sense amplifier is located. Since the memory cell having the faster word line selection timing and the slower word line selection timing is closer to the sense amplifier, the overall access time from the address input to the sense amplifier input is shortened.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a schematic chip arrangement of a semiconductor memory device showing a first embodiment according to the present invention. As shown in FIG. 5, as an example, a schematic chip arrangement of a 1M-bit SRAM having a 128K word.times.8 bit configuration is shown. Is shown. In FIG. 1, an upper row address circuit X3 is arranged above a chip, and is connected to an address pad A11 and an address pad A10 arranged on the opposite side of the chip. The upper column address circuit Z for selecting a block is connected to address pads A4, A5, A6 and an address pad A3 arranged on the opposite side of the chip. The lower row address circuit X1 is connected to address pads A7, A12, and the upper row address circuit X2 is connected to A14, A16, A15, A13, A6, A9. The other circuit arrangement and signal wiring are the same as in FIG. 5 of the conventional device, and the description is omitted. A feature of the first embodiment of the present invention is that all the address circuits related to the selection of the word line SWL of the memory cell, that is, the upper row address circuits X2 and X3, the lower row address circuit X1, and the upper column address circuit Z for selecting a block. Are arranged on the opposite side (upper part of the chip) from the area (lower part of the chip) where the sense amplifiers SA are arranged with the memory cell array area MA interposed therebetween.
[0016]
FIG. 2 shows a schematic equivalent circuit of FIG. 1, which is the same as FIG. 6 of the conventional device except that the arrangement of the upper row address circuit X3 and the connection order of the address pad and the address circuit are different. Omitted.
[0017]
In FIG. 2, as in the conventional device, the row upper predecode signals PDX21, PDX22, PDX3 and the block row lower signal BX include the wiring resistance, the wiring capacitance, the drain capacitance of the repetitive circuit, the parasitic resistance due to the gate capacitance, and the parasitic capacitance. Are connected as shown in FIG. In the first embodiment of the present invention, since the upper row address circuits X2 and X3 for selecting the main word line MWL are all arranged at the upper part of the chip, the main word line is selected faster at the upper part MWL1 of the chip and at the lower part MWL256 of the chip. It becomes slow under the influence of the parasitic resistance. In addition, since the lower row address circuit X1, the upper column address circuit Z, and the block selection circuit BS for selecting the block row lower signal BX are also arranged at the top of the chip, the selection of the block row low signal BX is fast at the top of the chip. The lower part becomes slow. Therefore, the selection timing of the main word line MWL and the block row lower signal BX, which are signal wirings related to the word line selection SWL of the memory cell, is faster in the upper part of the chip and slower in the lower part of the chip. Regarding the timing, the SWL 1024 wired at the lower part of the chip is the latest and the wiring is wired at the upper part of the chip even when any of the upper row address (X2, X3), the lower row address (X1), and the upper column address (Z) changes. SWL1 will be the fastest. On the other hand, the delay time from the memory cell at the time of reading to the input of the sense amplifier is the slowest for MC1 at the top of the chip and the fastest for MC2 at the bottom of the chip due to the parasitic resistance and parasitic capacitance of the bit line, as in the conventional device. Therefore, the delay from the address input to the sense amplifier input is greatly affected only by the parasitic resistance and the parasitic capacitance of the bit line in the memory cell (for example, MC1) arranged on the upper part of the chip, and is affected by the memory cell (for example, MC1) arranged on the lower part of the chip. In MC2), only the parasitic resistance and the parasitic capacitance of the predecoder wiring related to the word line selection have a large effect.
[0018]
As described above, the conventional semiconductor memory device is affected by the parasitic resistance and the parasitic capacitance of both the bit line and the predecode signal line depending on the selection method of the row address and the arrangement position of the memory cell. Although the memory cell data output time differs by a maximum of 5 ns, by using the circuit arrangement of the first embodiment of the present invention, only the influence of one of the bit line and the predecode signal is required, and the difference is a delay. There is only 1 ns which is the difference between the differences. Accordingly, the operation timing can be increased without making the operation of the sense amplifier unstable, and a high-speed access time can be realized. This is the same in the write operation. As in the first embodiment of the present invention, by arranging the memory cell write circuit in the sense amplifier side region, the write pulse width can be increased.
[0019]
In general, in a semiconductor memory device, a sense amplifier circuit and a write circuit, which have a large number of circuit elements and a repetitive arrangement, and an input / output circuit having a complicated circuit scale occupy a large proportion of the chip area. In the embodiment, by arranging the address circuits mainly in the upper part of the chip as shown in FIG. 1, the arrangement area of the circuit group can be secured in the lower part of the chip, and the chip size can be reduced.
[0020]
FIG. 3 shows a schematic chip arrangement of a semiconductor memory device according to a second embodiment of the present invention. The difference between FIG. 3 of the second embodiment of the present invention and FIG. 1 of the first embodiment of the present invention is that, of the plurality of address circuits related to the word line selection, the distance between the bonding pads corresponding to the address circuits is large. In this case, the input buffer circuit is arranged near the corresponding bonding pad, and the output of the input buffer is connected to the address buffer circuit via a long wiring. In FIG. 3, an input buffer circuit A10I is arranged between the upper row address circuit X3 and the address pad A10 in close proximity to the pad A10, and a long wiring necessary for transmitting the signal of the address pad A10 to X3 is provided in the input buffer A10I. And X3. Similarly, between the upper column address circuit Z and the address pad A3, an input buffer circuit A3I is arranged close to the A3 pad. FIG. 4 shows a schematic equivalent circuit of FIG. 3, in which the input buffer circuits A10I and A3I are each composed of two stages of inverters. The other circuit arrangements and connections are the same as in FIG. 2 of the first embodiment of the present invention, and a description thereof will be omitted.
[0021]
In FIG. 4, an address input signal A10 is supplied from an address pad A10 to an address buffer circuit of an address circuit X3 arranged on the opposite side of the chip via an input buffer circuit A10I and a relatively long wiring A10S. Here, as shown in FIG. 3, the wiring A10S is arranged on the outer periphery of the chip by, for example, a second metal layer. However, it is not necessary to reduce the wiring width and the wiring pitch unlike the above-described bit line and predecode signal. This is a region where the interlayer capacitance is small, and the parasitic resistance and the parasitic capacitance do not increase because the gate of the repetitive circuit is not connected. For example, in a design example of a chip size of about 10 mm, the delay due to the two inverters of the input buffer A10I and the wiring A10S can be suppressed to about 1 ns by adjusting the wiring layout and the inverter size. The same applies to the address input signal A3. Since other configurations are the same as those of the first embodiment of the present invention, the delay time from the input of the address circuit to the input of the sense amplifier is large depending on the method of selecting the row address and the arrangement position of the memory cells as described above. There is no difference. Only when the address A3 or A10 changes, the access time increases by the delay of 1 ns of the input buffer and the signal wiring, but it is still faster than the conventional device.
[0022]
In the second embodiment of the present invention, compared to the first embodiment, the wiring capacity inside the device added to the address pad can be reduced, and the terminal capacitance seen from the outside of the device can be reduced. Particularly, in a system using a semiconductor memory device, when an address bus is commonly connected to a plurality of semiconductor memory devices, it is required to reduce the terminal capacity of each memory device. An example is an effective means for such a request. Further, in a general semiconductor memory device, as described in, for example, JP-A-63-244658, an arrangement position of a bonding pad in the device is often determined by an arrangement of a package lead and an internal lead. When a circuit arrangement is adopted, an address circuit may not always be arranged near a bonding pad. Even in such a case, by using the second embodiment of the present invention, it is possible to minimize the delay at the input unit without increasing the terminal capacitance.
[0023]
In the embodiments of the present invention described above, an example of an SRAM has been described. However, a DRAM (Dynamic Random Access Memory) or a ROM (Read Only Memory) may be arranged in a matrix and selected by a word line. The present invention is applicable to any semiconductor memory device including a memory cell array, a sense amplifier, an address buffer circuit, and a predecoder circuit. In the embodiment of the present invention, an example of a 1M bit capacity of 128K words × 8 bits has been described. However, any combination of row / column addresses can be used regardless of the memory capacity and the word configuration. Needless to say, it can be adapted. In the above embodiment, the description has been made using the divided word line selection method as the memory cell word line selection. However, the present invention is not limited to this, and any method including a word line decoder and a predecoder circuit arranged near the memory cell array is used. Can also be used. Further, the pad arrangement has been described with an example in which the pads are arranged on two short sides of the chip. However, the present invention is not limited to this, and the pads may be arranged on the long side or on the four sides of the chip.
[0024]
In the embodiment of the present invention, an example was described in which the address buffer circuit and the predecoder circuit were arranged close to each other using the address buffer circuit and the predecoder circuit having the configurations shown in FIGS. The present invention is not limited thereto, and can be modified without departing from the spirit of the invention. Further, the two-stage inverter circuit shown in FIG. 4 has been described as an example of the input buffer circuit of the second embodiment, but the number of stages may be one, three or more, and the invention is not limited to the inverter circuit.
[0025]
【The invention's effect】
As described above, in the semiconductor memory device of the present invention, all of the address buffer circuit and the predecoder circuit related to the word line selection of the memory cell are arranged on the opposite side to the sense amplifier region with the memory cell array region therebetween. Since the word line selection timing of a memory cell farther from the amplifier can be made faster, the operation timing of the sense amplifier can be increased without making the operation of the sense amplifier unstable, and a high-speed access time can be realized. Further, by arranging it in the memory cell write circuit sense amplifier side region, a higher write pulse width can be realized. Further, a sense amplifier circuit having a large number of circuit elements and a repetitive arrangement and an input / output circuit having a complicated circuit scale can be efficiently arranged, and a reduction in chip size can be realized.
[0026]
As in the second embodiment, by arranging the input circuit close to the pad between the address buffer circuit for word line selection and the bonding pad, the terminal capacitance of the device can be reduced while minimizing the delay at the input section. The invention can be practiced without any increase. Further, the present invention can be implemented while dramatically improving the degree of freedom regarding the layout arrangement of the bonding pads.
[0027]
The present invention is more effective for a semiconductor memory device having a configuration in which the number of memory cells connected to a bit line is larger, and is particularly suitable for an SRAM having a large memory cell, a large bit line capacity per cell, and a large resistance.
[Brief description of the drawings]
FIG. 1 is a schematic layout diagram of a semiconductor memory device according to a first embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of the semiconductor memory device according to the first embodiment of the present invention.
FIG. 3 is a schematic layout diagram of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 4 is an equivalent circuit diagram of a semiconductor memory device according to a second embodiment of the present invention.
FIG. 5 is a schematic layout diagram of a conventional semiconductor memory device.
FIG. 6 is an equivalent circuit diagram of a conventional semiconductor memory device.
[Explanation of symbols]
A0 to A16 Address input X1 Lower row address circuit X2, X3 Upper row address circuit,
Z Upper column address circuit Y Lower column address circuit MWD Main word line decoder circuit SWD Sub word line decoder circuit CG Column gate BLEQ Bit line equalizer circuit SA Sense amplifier circuit BS Block selection circuit MWL Main word line SWL Word line BL, BLb Bit line MC1, MC2 Memory cell PDX Row upper predecode signal BX Block row lower signal

Claims (2)

A memory cell array in which a plurality of memory cells are arranged in a matrix; a plurality of word line decoder circuits arranged in close proximity to the memory cell array to select word lines of the memory cells; and a memory arranged in close proximity to the memory cell array A sense amplifier circuit for amplifying cell data, a plurality of address buffer circuits for receiving an address signal supplied from an external terminal, and a plurality of predecoder circuits for decoding complementary address signals output from the plurality of address buffer circuits. A semiconductor memory device comprising:
Of the plurality of address buffer circuits and the plurality of predecoder circuits, all of the address buffer circuits related to the word line selection and the predecoder circuits related to the word line selection are connected to the sense cell via the memory cell array region. It is located in the area opposite to the area where the amplifier is located,
A semiconductor memory device, wherein at least a row address signal line and a block address signal line among address signals related to the word line selection are wired from the opposite area. 2. The semiconductor memory device according to claim 1, further comprising: a bonding pad provided corresponding to an external address terminal; and an input buffer circuit comprising at least one or more gate circuits arranged in close proximity to said bonding pad, A semiconductor memory device, wherein an input of an address buffer circuit related to line selection is connected to the input buffer circuit via a relatively long wiring.

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