JP3585262B2 - Liquid crystal display - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a thin film transistor array element for realizing a highly reliable and excellent display quality liquid crystal display device.
[0002]
[Prior art]
2. Description of the Related Art A liquid crystal display device (hereinafter abbreviated as LCD) using an amorphous silicon thin film transistor (hereinafter abbreviated as a-SiTFT) as a switching element is a flat display having a display performance comparable to a CRT, such as a pocket television, a viewfinder of a video camera, It is applied in various fields such as personal computers and word processors.
[0003]
At present, a structure which is widely put into practical use as an a-Si TFT of such an LCD is a so-called inverted stagger type structure in which a gate electrode is disposed in a lower layer. This structure is a self-aligned type in which the protective insulating film pattern of the channel portion is formed by exposing from the back surface of the substrate. Since the gate insulating layer and the semiconductor layer can be continuously formed in a vacuum, the structure is relatively stable. There is an advantage that a transistor can be formed.
[0004]
The structure of a general TFT (thin film transistor) -LCD using such an inverted staggered a-Si TFT as a switching element will be described with reference to FIG. 9A is a sectional view showing the structure of the LCD, and FIG. 9B is a plan view of the TFT. In the figure, 1 is a gate electrode formed on an insulating substrate 12a, 2 is a gate insulating film, 3 is an a-Si (amorphous silicon) semiconductor layer, and 4 is an insulating film for protecting the semiconductor layer 3. Reference numeral 5 denotes an n-type a-Si layer doped with phosphorus as an impurity, and reference numerals 7a and 7b denote a source electrode and a drain electrode, respectively. Reference numeral 6 denotes a pixel electrode electrically connected to the drain electrode 7b. Reference numeral 8 denotes an overcoat insulating film for protecting the thin film transistor, which is generally made of silicon nitride (SiNx). 9a and 9b are alignment films, and 10 is a liquid crystal layer. Reference numeral 11 denotes a counter electrode formed on the insulating substrate 12b.
[0005]
Next, a driving method of the TFT-LCD will be described. FIG. 8 shows a drive signal waveform supplied to each electrode of the TFT-LCD. Vg is a scanning signal applied to the gate electrode 1 of the TFT, Vs is a display signal applied to the source electrode 7a of the TFT, and when the TFT is turned on, the display signal Vs is applied to the pixel electrode 6 as a drain voltage Vd through the TFT. Is done. Vsc indicates the midpoint of the display signal voltage amplitude. A DC voltage Vc is applied to the counter electrode 11. Ton indicates an ON period of the TFT, and Toff indicates an OFF period.
[0006]
[Problems to be solved by the invention]
By the way, at present, when the TFT-LCD panel having the above-described configuration is driven at a high temperature for a long time, it is known that the following image phenomenon appears. One is the phenomenon of burning, in which the same fixed pattern is displayed as an afterimage when the same fixed pattern is displayed for a long time, and the other is the phenomenon of a decrease in contrast caused by the deterioration of TFT off characteristics. It is. Hereinafter, these problems will be described in detail with reference to FIGS. 8 and 9.
[0007]
First, the burning phenomenon will be described. As shown in FIG. 9, in the TFT having such a structure, a parasitic capacitance Cgd between the gate and the drain electrode is formed in a region where the gate electrode 1 and the drain electrode 7b overlap in a plane. As can be seen from the signal waveforms in FIG. 8, when the TFT-LCD is driven, a potential drop ΔVd of the drain voltage Vd applied to the pixel electrode 6 occurs due to the parasitic capacitance Cgd, and the liquid crystal 10 on the pixel electrode 6 A DC voltage is applied to the layer. This potential drop ΔVd is
ΔVd = Cgd (Vgt−Vgb) / (Clc + Cst + Cgd)
And increases as the parasitic capacitance Cgd increases. Here, Clc is a liquid crystal capacitance, Cst is an additional capacitance, Vgt is a potential when the scanning signal Vg is on, and Vgb is a potential when the scanning signal Vg is off.
[0008]
Therefore, as the potential drop ΔVd increases, the DC voltage component to the layer of the liquid crystal 10 also increases. Such a DC voltage component to the layer of the liquid crystal 10 induces an internal charge in the layer of the liquid crystal 10, and as a result, causes image quality problems such as printing.
Next, deterioration of the off characteristics of the TFT will be described. As shown in FIG. 9, in the TFT-LCD, an alignment film 9a and a liquid crystal layer 10 exist on the channel of the TFT. As shown in FIG. 8, the gate electrode 1 of the TFT has an off-state off-time Toff to which the negative gate bias Vgb is applied except for a slight on-period Ton when the TFT is in an on-state due to its operation. During this period, the drain voltage Vd supplied to the pixel electrode 6 through the TFT is held. In other words, a DC voltage is applied between the counter electrode 11 and the gate electrode 1 for most of the time, with the counter electrode 11 side being positive and the gate electrode 1 side being negative. Thereby, the alignment film 9a causes polarization on the a-Si semiconductor on the upper side of the TFT, electrons are induced in the upper layer of the a-Si semiconductor layer 3, and the off characteristic of the TFT is deteriorated (reference: Ogawa). Others 1989 Kansai Chapter Association Conference on Electrical Relations G313, G10-30).
[0009]
FIG. 10 shows Id-Vg representing the switching performance of the TFT in the relationship between the current Id flowing between the source electrode 7a and the drain electrode 7b of the TFT in the TFT-LCD configuration and the voltage Vg applied to the gate electrode 1. It is the result of measuring the change over time of the characteristic. As it can be seen from FIG. 10, the characteristics P ₂ after 24 hours operation as compared with the initial characteristics P ₁ is, an increase in current in the sub-threshold region which is a boundary portion of the off-state from the ON state is seen. Due to such deterioration of the switching characteristics, the voltage holding characteristics of the liquid crystal 10 in the TFT-LCD deteriorates, and as a result, image quality problems such as a decrease in contrast and point defects are caused.
[0010]
The present invention has been made in view of such a problem. First, it is necessary to reduce the deterioration of the off characteristic of the TFT caused by driving for a long time, and secondly, to reduce the parasitic capacitance between the gate electrode and the drain electrode. This prevents a reduction in reliability and the occurrence of a burning phenomenon due to the application of a DC voltage to the liquid crystal layer, and further increases the aperture ratio of the TFT-LCD, that is, the ratio of the area displayed by the pixel electrode to the entire area of the screen. It is an object of the present invention to provide a thin film transistor array element having high reliability and excellent performance, which can improve brightness.
[0011]
[Means for Solving the Problems]
The liquid crystal display apparatus comprising, a first insulating and the substrate, signal Line a scanning line of the first insulating substrate having a scanning line and signal lines arranged in a matrix on one main surface a pixel electrode formed corresponding to each intersection, and a protective insulating film pattern of the channel portion from the one main surface different from the other surface of the first insulating substrate and the gate electrode as a mask formed by performing exposure A self-aligned inverted staggered structure, a thin film transistor provided between the pixel electrode and the signal line and the scanning line, an alignment film formed on the first insulating substrate so as to cover the pixel electrode and the thin film transistor, a thin film transistor array device having,
A second insulating substrate having a counter electrode facing the thin film transistor array element and sandwiching a liquid crystal layer between the thin film transistor array element;
The alignment film is located closer to the semiconductor layer than the upper surface of the source electrode and the upper surface of the drain electrode via a protective insulating film at a position between the source electrode and the drain electrode of the thin film transistor,
The width of the semiconductor layer in the path of current flowing from the source electrode of the thin film transistor through the semiconductor layer to the drain electrode, planar overlapping portion of the gate electrode formation region so as to protrude toward the drain electrode of the source electrode And at least 4 μm narrower than at least one of the width of the drain electrode and the width of the planar overlapping portion with the gate electrode.
[0013]
[Action]
According to the liquid crystal display device of the first aspect, the scanning signal is applied to the scanning line, the display signal is applied to the signal line, the thin film transistor is turned on, the voltage is applied to the pixel electrode, and the liquid crystal on the pixel electrode is displayed. In this case, the width of the semiconductor layer in the path of the current flowing from the source electrode of the thin film transistor to the drain electrode through the semiconductor layer is smaller than at least one of the width of the source electrode and the width of the drain electrode. The potential near the alignment film is less affected by the potential of the counter electrode, and is controlled by the potentials of the source electrode and the drain electrode. This stabilizes the potential in the vicinity of the alignment film and suppresses the induction of electrons in the upper layer of the a-Si semiconductor due to the above-mentioned polarization. For this reason, deterioration of the off characteristics of the thin film transistor caused by driving for a long time can be reduced, and image quality can be maintained.
[0015]
【Example】
FIG. 1 shows a thin film transistor array element according to a first embodiment of the present invention. That is, FIG. 1 shows a structure of a thin film transistor array element, (a) is a sectional view thereof, and (b) is a plan view. In the figure, 1 is a gate electrode, 2 is a first insulating film (gate insulating film), 3 is a semiconductor layer, 4 is a second insulating film (protective insulating film), 5 is a P-doped semiconductor layer, and 6 is a transparent electrode. (Pixel electrode), 7a is a source electrode, 7b is a drain electrode, and 8 is a third insulating film (overcoat insulating film).
[0016]
Here, a specific manufacturing method of the thin film transistor array element of the first embodiment will be briefly described with reference to FIGS. In (1) to (9) of FIG. 7, the left side is a plan view, and the right side is a cross-sectional view. In the thin-film transistor array element of the first embodiment, an inverted staggered a-Si TFT in which the pattern of the second insulating film 4 is formed by exposing the back surface of the insulating substrate 12a to light is used as a switching element.
[0017]
(1) After forming a Cr film as a gate electrode 1 on a transparent insulating substrate 12a and patterning it, (2) SiNx as a first insulating film 2, a-Si as a semiconductor layer 3, and a second insulating film As the film 4, SiNx is continuously formed. (3) In the photolithography process, after a positive photoresist 15 is applied to the entire insulating substrate 12a, only the second insulating film 4 is gated from the back surface of the insulating substrate 12a using the pattern of the gate electrode 1 as a mask. A portion other than the electrode 1 is exposed from the direction of the arrow. (4) Subsequently, a portion other than the mask 16 is exposed from the surface of the insulating substrate 12a by using another mask 16 in the direction of the arrow. (5) As a result, the pattern of the gate electrode 1 and the mask 16 are planarized. The resist 15 remains in the overlapped portion, and the second insulating film 4 is patterned using the resist 15 as a mask. (6) After forming n + a-Si as the P-doped semiconductor layer 5, the semiconductor layer 3 and the P-doped semiconductor layer 5 are patterned. (7) After forming an ITO film as the pixel electrode 6 and patterning it, the first insulating film 2 is patterned. (8) Al is formed as a source electrode 7a and a drain electrode 7b and patterned. The drain electrode 7b and the pixel electrode 6 are electrically connected. (9) Finally, SiNx was formed as the third insulating film 8 and patterned to complete the thin film transistor array element of the first embodiment.
[0018]
Next, characteristics of the thin film transistor array element of the first embodiment will be described. First, the width W1 of the semiconductor layer 3 in the path of the current flowing from the source electrode 7a of the thin film transistor to the drain electrode 7b via the semiconductor layer 3 is smaller than the width W2 of the source electrode 7a and the width W3 of the drain electrode 7b. The difference between the width W2 of the source electrode 7a and the width W3 of the drain electrode 7b and the width W1 of the semiconductor layer 3 is 4 μm or more. That is, W2−W1 ≧ 4 μm and W3−W1 ≧ 4 μm. With respect to the TFT-LCD using the thin film transistor array element having such a configuration, the change over time of the TFT characteristics was evaluated. The operation test was performed at 60 ° C. Figure 2 shows a characteristic _{Q 2} in the Id-Vg characteristic of TFT initial characteristics _{Q 1} and 24 hours after the operation. As shown in FIG. 2, in this embodiment, the width W1 of the semiconductor layer 3 of the thin-film transistor array is narrower than the width W2 of the source electrode 7a and the width W3 of the drain electrode 7b. It can be seen that the change is sufficiently suppressed.
[0019]
FIG. 3 shows a second embodiment of the present invention. That is, this thin film transistor array element has a channel portion of a TFT formed on a scanning line serving as a gate wiring as a gate electrode 1, and is otherwise the same as the first embodiment including characteristics. Therefore, in the second embodiment, as in the first embodiment, the width W1 of the semiconductor layer 3 in the path of the current flowing from the source electrode 7a of the thin film transistor to the drain electrode 7b via the semiconductor layer 3 is determined by the source electrode The width W2 of the drain electrode 7a is smaller than the width W3 of the drain electrode 7b, and the difference is 4 μm or more. With this configuration, the off characteristics are improved.
[0020]
In the second embodiment, since the thin film transistor is formed on the gate wiring, the area occupied by the pixel electrode 6 can be increased as compared with the first embodiment. This has the effect of improving the rate and improving the brightness of the screen of the TFT-LCD.
A third embodiment of the present invention will be described with reference to FIG. In this embodiment, the width W1 of the semiconductor layer 3 of the thin film transistor is smaller than the width W3 of the drain electrode 7b, and the difference is 4 μm or more. Also in the thin film transistor array element having such a configuration, an operation test was performed in the same manner, and as a result, the off characteristic of the thin film transistor was almost the same as that of the first and second embodiments.
[0021]
A thin-film transistor array element according to a fourth embodiment of the present invention will be described with reference to FIG. In the thin film transistor array element of this embodiment, as shown in FIG. 5, a source electrode 7a and a drain electrode 7b are formed so as to be arranged in the direction of a scanning line with respect to a gate electrode 1 protruding from a gate wiring serving as a scanning line. The tip of the gate electrode 1, that is, the edge of the gate electrode pattern along the drain electrode 7b from the source electrode 7a is located inside the source electrode 7a and the drain electrode 7b, and the width W1 of the semiconductor layer 3 is equal to the width of the source electrode 7a. The width is smaller than W2 and the width W3 of the drain electrode 7b, and the difference is 4 μm or more.
[0022]
Also in this thin film transistor array element, as a result of performing an operation test in the same manner as in the first embodiment, the off characteristic of the thin film transistor is almost the same as that of the first, second and third embodiments. The results were obtained, and the change with time of the off-characteristics was suppressed.
Further, by adopting the configuration as in the fourth embodiment, the area of the gate electrode 1 can be reduced as compared with the first and third embodiments. The aperture ratio can be increased, and the aperture ratio can be improved. Further, with such a configuration, the area of the gate electrode 1 and the drain electrode 7b that overlap in a plane is reduced. That is, the parasitic capacitance (Cgd) between the gate electrode 1 and the drain electrode 7b decreases. Therefore, the DC component to the layer of the liquid crystal 10 of the TFT-LCD can be reduced, the burning phenomenon and the flicker characteristics can be improved, and the reliability can be improved.
That is, the source electrode and the drain electrode are formed so as to be arranged in the direction of the scanning line with respect to the gate electrode protruding from the scanning line, and the tip of the gate electrode is located inside at least one of the source electrode and the drain electrode. In addition, since the area of the gate electrode can be further reduced without changing the ON current of the thin film transistor, the parasitic capacitance between the gate electrode and the drain electrode is reduced, the DC applied component to the liquid crystal layer is reduced, and the potential of the pixel electrode is reduced. Descent can be suppressed. For this reason, it is possible to prevent a reduction in reliability and the occurrence of a burn-in phenomenon, and to improve the aperture ratio, that is, the brightness of the screen accompanying the improvement in the ratio of the area displayed by the pixel electrodes to the entire area of the screen. Excellent performance can be achieved with reliability.
[0023]
A thin film transistor array device according to a fifth embodiment of the present invention will be described with reference to FIG. That is, in this thin film transistor array element, the pattern end of the gate electrode 1 along the source electrode 7a to the drain electrode 7b of the thin film transistor is located inside the drain electrode 7b , and the width W1 of the semiconductor layer 3 is equal to the width of the drain electrode 7b . It is narrower than W3, and the difference is 4 μm or more. Also in this thin film transistor array element, as a result of performing an operation test in the same manner as in the first embodiment, the off characteristics of the thin film transistor were almost the same as those in the first to fourth embodiments. In addition, the change with time of the off characteristic is suppressed.
[0024]
Also in such a configuration, the brightness and reliability of the TFT-LCD can be improved as in the fourth embodiment.
Therefore, in any of the above-described embodiments, a thin film transistor array element having high reliability and excellent performance capable of reducing deterioration of off characteristics under driving (voltage) stress, which is an important issue in reliability of a-Si TFTs, is provided. be able to.
[0025]
Note that the method of making the second to fourth embodiments is the same as that of the first embodiment. In the third embodiment (FIG. 4) and the fifth embodiment (FIG. 6), the width W1 of the semiconductor layer 3 is smaller than the width W3 of the drain electrode 7b, but the width W1 of the semiconductor layer 3 is smaller than the source electrode 7a. The same result can be obtained with a configuration narrower than the width W2.
[0026]
【The invention's effect】
According to the liquid crystal display device of the first aspect, the width of the semiconductor layer in the path of the current flowing from the source electrode of the thin film transistor to the drain electrode via the semiconductor layer is smaller than at least one of the widths of the source electrode and the drain electrode. Therefore, the potential in the vicinity of the alignment film on the channel of the thin film transistor is less affected by the potential of the counter electrode, and is controlled by the potentials of the source electrode and the drain electrode. This stabilizes the potential in the vicinity of the alignment film and suppresses the induction of electrons in the upper layer of the a-Si semiconductor due to the above-mentioned polarization. For this reason, it is possible to reduce the deterioration of the off characteristic of the thin film transistor caused by driving for a long time, and to maintain the image quality.
[Brief description of the drawings]
FIGS. 1A and 1B show the structure of a thin film transistor array element according to a first embodiment of the present invention, wherein FIG. 1A is a cross-sectional view and FIG.
FIG. 2 is a characteristic diagram showing a change over time of an Id-Vg characteristic indicating a switching performance of a thin film transistor in the TFT-LCD.
FIG. 3 is a plan view of a thin film transistor array element according to a second embodiment.
FIG. 4 is a plan view of a thin film transistor array element according to a third embodiment.
FIG. 5 is a plan view of a thin film transistor array element according to a fourth embodiment.
FIG. 6 is a plan view of a thin film transistor array element according to a fifth embodiment.
FIG. 7 is a drawing showing a manufacturing process of a thin film transistor array element according to each embodiment of the present invention.
FIG. 8 is a waveform diagram of an applied signal when driving a TFT-LCD.
9A and 9B show the structure of a conventional TFT-LCD, wherein FIG. 9A is a cross-sectional view and FIG. 9B is a plan view.
FIG. 10 is a characteristic diagram showing a change over time of an Id-Vg characteristic of the thin film transistor.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 gate electrode 2 first insulating film 3 semiconductor layer 4 second insulating film 5 P-doped semiconductor layer 6 pixel electrode 7 a source electrode 7 b drain electrode 8 third insulating films 9 a and 9 b alignment film 10 liquid crystal 11 counter electrode 12 a 12b insulating substrate

Claims (1)

A first insulating substrate having a signal line arranged in a matrix on one principal surface and the scanning line, which is formed corresponding to the intersections between the signal lines of the first insulating substrate and the scan line a pixel electrode, a protective insulating film pattern of the channel portion in a reverse stagger structure in a self-aligned formed by performing exposure using the gate electrode as a mask from the one main surface different from the other surface of said first insulating substrate A thin film transistor provided between the pixel electrode and the signal line and the scanning line, and an alignment film formed on the first insulating substrate so as to cover the pixel electrode and the thin film transistor. An array element ;
A second insulating substrate having a counter electrode facing the thin film transistor array element and sandwiching a liquid crystal layer with the thin film transistor array element;
The alignment film is located between the source electrode and the drain electrode of the thin film transistor, via the protective insulating film, closer to the semiconductor layer than the upper surface of the source electrode and the upper surface of the drain electrode,
A width of the semiconductor layer in the path of current flowing from the source electrode of the thin film transistor to the drain electrode through the semiconductor layer, and said gate electrode region formed to protrude toward said drain electrode of said source electrode A liquid crystal display device having a width which is at least 4 μm narrower than at least one of a width of a planar overlap portion and a width of a planar overlap portion of the drain electrode with the gate electrode.

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