JP3579194B2 - Driving method of solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device using an amplifying MOS sensor, and particularly to a solid-state imaging device capable of simplifying a cell configuration and obtaining high resolution. Set The present invention relates to a driving method.
[0002]
[Prior art]
In recent years, solid-state imaging devices have been developed in which the potential of a signal charge storage unit is modulated by signal charges generated by photoelectric conversion, and an amplification transistor inside the pixel is modulated by the potential, thereby providing an amplification function inside the pixel. . This device is called an amplifying solid-state image pickup device, and is expected as a solid-state image pickup device suitable for reducing the pixel size by increasing the number of pixels or reducing the image size.
[0003]
FIG. 14 is a diagram illustrating a configuration of a conventional solid-state imaging device.
In FIG. 14, the unit cell includes a photodiode 1, a read transistor 2, an amplification transistor 3, a reset transistor 4, and an address transistor 5, and a load transistor 7 connected to a source line 6 is connected to the amplification transistor 3 through a signal line 8. A source follower circuit is configured. The amplification transistor 3 and the address transistor 5 are connected by a source / drain (S / D) section 9.
[0004]
From the vertical register 10, an address line 11, a read line 12, and a drain line 13 are wired. The address line 11 is the gate of the address transistor, the read line 12 is the gate of the read transistor 2, and the drain line 13 is The drains of the address transistor 5 and the reset transistor 4 are connected. The signal line 8 is connected to the storage capacitor 16 via a sample / hold transistor (SHTr) 15 to which the sample / hold line 14 is connected. The signal charge is output to the signal output line 19 by applying a read pulse from the horizontal register 17 to the horizontal transistor 18.
[0005]
FIG. 15 is a timing chart for driving such a conventional solid-state imaging device. T in horizontal blanking HBLK ₁ ~ T ₁₁ This will be described separately. First, the selected address line 11 'is set to the high (Hi) level (t ₂ ) When the readout line 12 ′ is set to Hi and the reset transistor 4 and the readout transistor 2 are turned on, the pixel column B one line before is reset, and at the same time, the signal of the currently selected pixel column A is Read out (t ₃ ).
[0006]
Thereafter, the sample hold line 14 is turned on (t ₇ ), The signal is stored in the storage capacitor 16. Then, a read pulse is applied from the horizontal register 17 to the horizontal transistor 18 during the signal valid period, whereby a signal is output to the signal output line 19.
[0007]
FIG. 16 is a diagram showing a cross-sectional shape of the cell portion in which the read transistor 7, the amplification transistor 3, and the address transistor 5 are formed in one cross section.
Charge is injected from the source line 6, passes through the read transistor 7, the signal line 8, and the amplification transistor 3, and is further discharged to the drain line 13 through the S / D unit 9 and the address transistor 5. Reference numeral 20 denotes a substrate.
[0008]
[Problems to be solved by the invention]
FIG. 17 is a potential distribution diagram of the cross section of FIG. 16, and (a) and (b) are diagrams showing the cell selection time and the non-selection time, respectively.
As shown in FIG. 17A, when a cell is selected, electric charge is injected from the source line 6, passes through the read transistor 7, the signal line 8, and the amplification transistor 3, and further, the S / D section 9, It is discharged to the drain line 13 through the address transistor 5. At this time, since a signal voltage is applied to the amplification transistor 3, an output corresponding to the voltage is output to the signal line 8.
[0009]
On the other hand, as shown in FIG. 17B, when the cell is not selected, the address transistor 5 is turned off, so that charge is injected from the source line 6 and flows to the read transistor 7 and the signal line 8. The signal line 8, the amplification transistor 3, and the S / D unit 9 are in a floating state without flowing through the drain line 13. For this reason, the potential of this portion varies depending on the signal potential of other selected cells.
[0010]
As described above, since the conventional cell structure uses the address transistor, there is a problem that the aperture ratio of the photodiode cannot be increased.
Therefore, the present invention has been made in view of the above circumstances, and a solid-state imaging device capable of simplifying the cell configuration by reducing the number of transistors used in the cell and increasing the aperture ratio of the photoelectric conversion unit. Driving method The purpose is to provide.
[0011]
[Means for Solving the Problems]
That is, the present invention selects an imaging region in which unit cells each having at least a photodiode, a reset transistor, an amplification transistor, and a signal charge readout transistor are arranged in a two-dimensional matrix on a semiconductor substrate, and a readout row of the imaging region. A plurality of vertical signal lines arranged in the column direction for reading out the detection signals of the photodiodes corresponding to the selected row, and horizontal signal lines arranged in the row direction from the vertical signal lines. In a driving method of a solid-state imaging device having a horizontal transistor for sequentially reading detection signals, the unit cell is selected by turning on reset transistors in all cells in only a selected row. The drain voltage of the reset transistor is applied to the gate of the amplification transistor. Applied, To a voltage higher than the gate voltage of the amplification transistor of the non-selected row It is characterized by setting.
[0014]
In the driving method of the solid-state imaging device according to the present invention, selection and non-selection of the cell are performed via the reset transistor.
In addition, according to the present invention, the channel width of the read transistor is larger on the amplifier circuit side than on the photodiode side. As a result of the narrow channel effect, the channel potential below the gate of the read transistor is higher on the amplifier circuit side. Get higher. Therefore, since the signal charge passing through the channel of the read transistor moves also due to this potential difference, the read time is shorter than when it flows only by diffusion.
[0015]
Further, according to the present invention, the aperture ratio of the photodiode is limited only by one wiring width among the signal current reading wiring and the signal charge discharging wiring. It is possible to increase the aperture ratio.
Further, in the same multilayer image sensor, the drain line and the signal line can be wired even if the element is miniaturized.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram showing the configuration of the solid-state imaging device according to the first embodiment of the present invention.
[0017]
In FIG. 1, the unit cell includes a photodiode 21, a read transistor 22, an amplification transistor 23, and a reset transistor 24. A read transistor 26 connected to a source line 25 is connected to the amplification transistor 23 through a signal line 27. A source follower circuit is configured.
[0018]
From the vertical register 28, a read line 29, a drain line 30, and a reset address line 31 are wired. The read line 29 is connected to the gate of the read transistor 22, and the drain line 30 is connected to the drains of the amplifying transistor 23 and the reset transistor 24. The reset address line 31 is connected to the gate of the reset transistor 24. The signal line 27 is connected to the storage capacitor 34 via a sample / hold transistor (SHTr) 33 connected to the sample / hold line 32. The signal charge is output to the signal output line 37 when a read pulse is applied from the horizontal register 35 to the horizontal transistor 36.
[0019]
Next, the operation when driving the device in the first embodiment will be described with reference to the timing chart shown in FIG.
T in horizontal blanking HBLK ₂₁ ~ T ₃₁ Divide into First, the drain line 30 'of the pixel column A to be selected is set to Hi (t ₂₂ Thereafter, the reset address line 31 'is turned off (t ₂₃ ). Then, the readout line 29 'is set to Hi (t ₂₄ ). At this time, in the unselected pixel column B, the reset address line 31 is set to Hi and the drain line 30 is set to low level.
[0020]
Thereafter, the sample / hold line 32 is turned on (t ₂₆ ), The signal is stored in the storage capacitor 34. A signal is output to the signal output line 37 by applying a read pulse from the horizontal register 35 to the horizontal transistor 36 during the signal valid period.
[0021]
FIG. 3 is a diagram showing a cross-sectional shape of the cell portion in which the reading transistor 26 and the amplifying transistor 23 are configured in one cross section.
Charge is injected from the source line 25, passes through the read transistor 26, the signal line 27, and the amplification transistor 23, and is discharged to the drain line 30.
[0022]
FIG. 4 is a potential distribution diagram of the cross section of FIG. 3, and (a) and (b) are diagrams showing the cell selection time and the non-selection time, respectively.
As shown in FIG. 4A, when a cell is selected, charges are injected from the source line 25 and discharged to the drain line 30 through the read transistor 26, the signal line 27, and the amplification transistor 23. The At this time, since a signal voltage is applied to the amplification transistor 23, an output corresponding to the voltage is output to the signal line 27.
[0023]
On the other hand, as shown in FIG. 4B, when the cell is not selected, the amplification transistor 23 is turned off, so that charge is injected from the source line 25 and flows to the read transistor 26 and the signal line 27. The signal line 27 is in a floating state without flowing through the drain line 30. For this reason, the potential of this portion varies depending on the signal potential of other selected cells.
[0024]
As described above, according to the first embodiment, since an address transistor is not required in the cell, a large aperture ratio can be obtained.
Here, a basic pattern example of the solid-state imaging device is shown in FIG. 5, and FIG. 6 is a circuit configuration diagram of a unit cell of the solid-state imaging device shown in FIG.
[0025]
In FIG. 6, the signal charge is read from the photodiode 40 through the read transistor 41 to the gate of the amplification transistor 42, and when the vertical selection transistor 43 is selected by the vertical selection signal Y, the amplified signal is read out. The The signal charge read from the photodiode 40 is discarded to the drain through the charge / discharge transistor 44 before the signal charge of the next field is read.
[0026]
This can be explained as follows using the plane pattern shown in FIG.
That is, the horizontal address line 45 wired in the horizontal direction from the vertical shift register is connected to the gate of the vertical selection transistor 43 and selects a line for reading a signal. Similarly, the reset line 46 and the readout line 47 wired in the horizontal direction from the vertical shift register are connected to the gate of the reset transistor 44 and the gate of the readout transistor 41, respectively. The drain of the amplifying transistor 42 is connected to a vertical signal line arranged in the vertical direction via an interlayer contact 48.
[0027]
The signal charge accumulated in the photodiode 40 is read to the drain when the read transistor 41 is turned on. Since this drain is electrically connected to the gate 50 of the amplification transistor 42 through the interlayer contact 49, the potential of the gate 50 changes. When the vertical selection transistor 43 is turned on, the amplified signal is read to the vertical signal line via the interlayer contact 48.
[0028]
In addition, the signal charge modulating the gate of the amplification transistor 42 read from the photodiode 40 is discarded to the drain through the charge / discharge transistor 44 before the signal charge of the next field is read. The drain of the charge / discharge transistor 44 is common with the drain of the amplification transistor of the adjacent unit cell, and is connected to the power supply line via the interlayer contact 51.
[0029]
In FIG. 5, for the sake of simplicity, only the element formation region, the gate polysilicon, and the interlayer contact pattern are shown, but in reality, the second layer polysilicon and aluminum wiring are also present.
[0030]
At this time, looking at the channel width of the read transistor 41, the channel width on the photodiode 40 side and the channel width on the drain side are the same.
Thus, in the basic solid-state imaging device, the channel potential of the readout transistor is constant in the channel direction with respect to the MOS readout transistor between the photodiode and the amplifier circuit. For this reason, the signal charge traveling in the channel moves only by diffusion, and it takes time until the reading is completed, which is one of the factors that hinders the increase in the number of pixels in the element. Therefore, in order to shorten the readout time of signal charges from the photodiode using the readout transistor, it is conceivable that the channel width of the readout transistor is made larger on the amplifier circuit side than on the photodiode side.
[0031]
FIG. 7 is a plan view of a solid-state imaging device according to the second embodiment of the present invention. Since the configuration diagram of the unit cell of the solid-state imaging device shown in FIG. 7 is the same as that of FIG. 6, the description thereof is omitted here.
[0032]
In FIG. 7, a horizontal address line 45 wired in the horizontal direction from the vertical shift register is connected to the gate of the vertical selection transistor 43 to select a line for reading a signal. Similarly, the reset line 46 and the readout line 47 wired in the horizontal direction from the vertical shift register are connected to the gate of the reset transistor 44 and the gate of the readout transistor 41 ', respectively. The drain of the amplifying transistor 42 is connected to a vertical signal line arranged in the vertical direction via an interlayer contact 48.
[0033]
The signal charge accumulated in the photodiode 40 is read to the drain when the read transistor 41 'is turned on. Since this drain is electrically connected to the gate 50 of the amplification transistor 42 through the interlayer contact 49, the potential of the gate 50 changes.
[0034]
When the vertical selection transistor 43 is turned on, the amplified signal is read to the vertical signal line through the interlayer contact 49. The signal charge modulating the gate 50 of the amplification transistor 42 read from the photodiode 40 is discarded to the drain via the charge / discharge transistor 44 before the signal charge of the next field is read.
[0035]
The drain of the charge / discharge transistor 44 is common to the drain of the amplification transistor 42 of the adjacent unit cell, and is connected to the power supply line via the interlayer contact 51. In FIG. 7, for the sake of simplicity, only the element formation region, the gate polysilicon, and the interlayer contact pattern are shown, but there are actually second-layer polysilicon and aluminum wiring.
[0036]
At this time, looking at the channel width of the read transistor 41 ′, the channel width on the drain side is formed wider than the channel width on the photodiode 40 side.
[0037]
8A and 8B briefly explain the effects of the second embodiment. FIG. 8A is a plan view showing a pattern of the read transistor 41 ', and FIG. 8B is taken along line II in FIG. Sectional view (c) shows the channel potential.
[0038]
8A and 8B, the photodiode 40 is the source, and the first layer polysilicon is the gate electrode 53. The signal charge generated in the photodiode 40 is read to the drain 54 when the transistor is turned on. Reference numeral 55 denotes a contact for connecting the drain of the read transistor and an upper wiring (not shown), 56 is a P-type substrate, 57 is an N-type impurity diffusion layer, 58 is a gate oxide film, and 59 is a LOCOS region.
[0039]
In FIG. 8C, below the gate electrode 53, the channel width increases in the direction from I to I '(W ₁ <W ₂ ). Therefore, the channel potential is lowered by the narrow channel effect (upward in FIG. 8C). As a result, the signal charge passing through the channel is accelerated in the drain direction due to the potential difference. Therefore, it is possible to shorten the readout time as compared with the conventional example that flows only by diffusion.
[0040]
Thus, according to the second embodiment, since the channel width of the read transistor is larger on the amplifier circuit side than on the photodiode side, as a result of the narrow channel effect, the channel potential under the gate of the read transistor is The amplifier circuit side is higher. Therefore, since the signal charge passing through the channel of the read transistor moves also by this potential difference, the read time is shorter than when it flows only by diffusion.
[0041]
By the way, in order to increase the aperture ratio of the photodiode, the signal line and the drain line may be overlapped.
That is, the basic configuration of the pixel in the amplification type solid-state imaging device is a photodiode, a reset transistor, an amplification transistor, a line selection transistor, or capacitive coupling, and a wiring connecting the photodiode and the amplification transistor gate.
[0042]
In addition, in the case of temporarily storing signal charges obtained by photoelectric conversion, a storage diode is provided in a region different from the photodiode, and a transfer gate is provided between the photodiode and the storage diode.
[0043]
Further, a signal line for reading the signal amplified by the amplification transistor and a drain line for resetting and discharging the signal charge are wired. Usually, two signal lines and two drain lines are wired independently.
[0044]
In a solid-state imaging device with a structure in which the element is miniaturized and the photoelectric conversion unit is accumulated on top of the transistor, signal line, and drain line, in order to obtain electrical continuity between the pixel electrode and the accumulation unit, A metal cap must be formed from the same layer as the layer to be formed and the layer to form the drain line. For this reason, when forming a signal line and a drain line, there is a restriction that electrical contact with the metal cap is avoided.
[0045]
In such an amplification type solid-state imaging device, signal lines and drain lines are wired independently. However, in the structure in which the wirings are independent, the aperture ratio of the photodiode portion is limited by the two wirings of the signal line and the drain line when the element is miniaturized.
[0046]
In addition, the imaging device having a structure in which the photoelectric conversion unit is stacked on the uppermost portion has a problem that there is no space for independent wiring so that the signal line and the drain line do not overlap. That is, when forming a fine element, it becomes impossible to wire without overlapping the signal line and the drain line.
[0047]
Therefore, in the embodiment described below, an example in which the aperture ratio of the photodiode is increased by a configuration in which the signal line and the drain line are overlapped will be described.
FIG. 9 shows a third embodiment of the present invention, in which a wiring (signal line) for reading an amplified signal current and a signal charge are discharged for one pixel of an amplification type solid-state imaging device. It is the figure which showed the arrangement configuration of the wiring (drain line) for this. FIG. 10 is a diagram showing a half-surface layout of the wiring layout of the amplification type solid-state imaging device of FIG. Further, FIG. 11 is an equivalent circuit diagram of the amplification type solid-state imaging device.
[0048]
In this amplification type solid-state imaging device, p-type silicon semiconductor substrate 61 has a p-type surface layer. ⁺ Layer (element isolation region) 62, p ⁺⁺ A layer (photodiode) 63 is formed. In the photodiode 63, signal charges are generated. Then, after a contact hole for electrical contact with the photodiode 63 is formed, it is formed so as to obtain electrical contact between the photodiode 63 and the gate of the amplification transistor 64. At this time, an n layer is formed in a region where the amplification transistor 64 and the reset transistor 65 for discharging signal charges are formed.
[0049]
Then, a source and a drain are formed, and a contact hole for making electrical contact is formed. Thereafter, polysilicon is deposited to form the gate of the transistor and processed into a desired shape to form an amplifying transistor 64 and a reset transistor 65. Furthermore, in order to accumulate signal charges, polysilicon and SiO ₂ / SiN / SiO ₂ The capacitor 66 is formed by the (insulating layer).
[0050]
In this way, the element portion of the amplification type solid-state imaging element is formed.
Next, after the element portion of the amplification type solid-state imaging device is formed, a signal line 67 that is a wiring for reading a signal current and a drain line 68 that is a wiring for discharging signal charges are wired. At this time, since the drain line 68 is formed, for example, an aluminum (Al) thin film is formed by sputtering. Then, the drain line 68 is formed by processing into a desired shape by patterning, RIE (reactive ion etching), or the like.
[0051]
Next, a silicon oxide film 69 is laminated. This silicon oxide film 69 serves to protect the drain line 68 as an insulating layer and prevent electrical contact with other parts. Then, in order to form the signal line 67, for example, an Al thin film is deposited by sputtering or the like. Thereafter, the resist is patterned so as to overlap the drain line 68 formed previously, and the signal line 67 is processed by the RIE method.
[0052]
As a result, as shown in FIG. 10, the signal line 67 is formed so as to overlap the upper portion of the drain line 68. Reference numeral 70 is an address line, and 71 is a reset line.
[0053]
Further, when patterning the resist, it is also preferable to pattern the signal line 67 so that the width of the signal line 67 is smaller than the width of the drain line 68. The reason for this is that when the resist covering the signal line 67 is patterned, the signal line 67 protrudes outside the drain line 68 due to misalignment, thereby causing a step and causing a poor electrical conduction. Because it can.
[0054]
As described above, as shown in FIG. 9, the wiring for reading out the signal current (signal line 67) and the wiring for discharging the signal charge (drain line 68) are arranged to overlap each other. As a result, the width of the wiring that limits the aperture ratio of the photodiode 63 can be set to one width. As a result, the aperture ratio of the photodiode 68 can be improved, so that the sensitivity can be increased.
[0055]
In the third embodiment described above, Al (aluminum) is used as the wiring material, but other metals such as tungsten (W), molybdenum (Mo), titanium (Ti), or the like are used. It is also possible to use a metal alloy including at least one kind or a compound such as a silizide compound.
[0056]
Next explained is the fourth embodiment of the invention.
12 and 13 show an amplification type solid-state imaging device having a structure in which photoelectric conversion portions are stacked. FIG. 12 shows an arrangement configuration of signal lines and drain lines for one pixel of the amplification type solid-state imaging device. FIG. 13 is a diagram showing a half-surface layout of the wiring layout of the amplification type solid-state imaging device of FIG.
[0057]
As in the third embodiment described above, the element portion is first formed. At this time, a part of the charge can be accumulated even in the portion that becomes the photoelectric conversion unit of the third embodiment.
[0058]
Then, in order to carry the signal charge to the storage portion 73, the public is formed on the insulating layer 74 using RIE or the like, and a metal column (plug) 75 is formed by tungsten CVD or the like. Thereafter, an Al (aluminum) film is deposited, for example, by 400 nm by sputtering or the like, and is formed into a desired shape by resist patterning, RIE, or the like. Thereby, the drain line 76 and the metal cap 77 are formed simultaneously.
[0059]
Thereafter, a silicon oxide film 74 is deposited, and resist patterning, RIE, metal film deposition, and the like are repeated again to form a signal line 79 and a metal cap 80 on the metal plug 78. At this time, since the metal cap 80 is formed in the same layer as the signal line 79, it is necessary to prevent the signal line 79 and the metal cap 80 from being in electrical contact. For this reason, the risk of electrical contact between the signal line 79 and the metal cap 80 is maintained with an interval of 0.6 μm or more.
[0060]
Therefore, as can be seen from FIG. 12, the signal line 79 cannot be wired so as not to overlap the drain line 76. That is, the signal line 79 and the drain line 76 must be stacked.
[0061]
After the formation of the signal lines, the silicon oxide film 74 is deposited again, and processing by RIE and metal film deposition are performed to form the metal plug 81. Thereafter, for example, a metal such as Ti is deposited, and shape processing by RIE or the like is performed to form the pixel electrode 82.
[0062]
Finally, an amorphous Si film, for example, is deposited as the photoelectric conversion layer 83, and a transparent electrode 84 made of, for example, ITO is deposited on the photoelectric conversion layer 83, that is, the uppermost portion.
[0063]
Incidentally, 85 is an amplification transistor, 86 is an address line, and 87 is a reset line.
Thus, according to the fourth embodiment, since the photoelectric conversion unit is disposed above the wiring such as the signal line and the drain line, the aperture ratio is not limited.
[0064]
【The invention's effect】
As described above, according to the present invention, a solid-state imaging device capable of simplifying the cell configuration by reducing the number of transistors used in the cell and increasing the aperture ratio of the photoelectric conversion unit. Driving method Can be provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a timing chart for explaining an operation when driving a device in the first embodiment;
FIG. 3 is a diagram showing a cross-sectional shape of a cell portion in which a read transistor and an amplifying transistor are configured in one cross section.
FIGS. 4A and 4B are potential distribution diagrams of a cross-sectional portion of FIG. 3, and FIGS. 4A and 4B are diagrams showing a cell selection time and a non-selection time, respectively.
FIG. 5 is a diagram illustrating a pattern example of a basic solid-state imaging device.
6 is a circuit configuration diagram of a unit cell of the solid-state imaging device shown in FIG.
FIG. 7 is a plan view of a solid-state imaging device according to a second embodiment of the present invention.
8A and 8B briefly explain the effects of the second embodiment, in which FIG. 8A is a plan view showing a pattern of a read transistor 41 ′, and FIG. 8B is along the line II in FIG. 8A; Sectional view (c) shows the channel potential.
FIG. 9 illustrates a third embodiment of the present invention, and discharges a signal charge and wiring for reading an amplified signal current for one pixel of an amplification type solid-state imaging device; It is the figure which showed the arrangement configuration of the wiring (drain line) for this.
10 is a diagram showing a half-surface layout of the wiring layout of the amplification type solid-state imaging device of FIG. 9. FIG.
FIG. 11 is an equivalent circuit diagram of the amplification type solid-state imaging device.
FIG. 12 is a diagram showing an arrangement configuration of signal lines and drain lines for one pixel of an amplification type solid-state imaging device having a structure in which photoelectric conversion units are stacked.
13 is a diagram illustrating an amplification type solid-state imaging device having a structure in which photoelectric conversion units are stacked, and is a diagram illustrating a half-surface layout of the wiring configuration of the amplification type solid-state imaging device in FIG. 12;
FIG. 14 is a diagram illustrating a configuration of a conventional solid-state imaging device.
FIG. 15 is a timing chart when driving a solid-state imaging device having a conventional structure;
16 is a diagram showing a cross-sectional shape of a cell portion in which a read transistor 7, an amplification transistor 3, and an address transistor 5 are formed in one cross section. FIG.
FIGS. 17A and 17B are potential distribution diagrams of the cross-sectional portion of FIG. 16, and FIGS. 17A and 16B are diagrams showing a cell selection time and a non-selection time, respectively.
[Explanation of symbols]
21, 40 photodiode,
22 read transistor,
23, 42 Amplifying transistor,
24 reset transistor,
25 source lines,
26, 41, 41 'read transistor,
27 signal lines,
28 vertical registers,
29, 47 readout line,
30 drain wire,
31 Reset address line,
32 sample / hold lines,
33 sample / hold transistor,
34 Storage capacity,
35 horizontal registers,
36 horizontal transistors,
37 signal output line,
43 vertical select transistor,
44 charge / discharge transistor,
45 horizontal address lines,
46 Reset line,
48, 49, 51 Interlayer contact,
50 gate.

Claims (3)

An imaging region in which unit cells having at least a photodiode, a reset transistor, an amplifying transistor, and a signal charge readout transistor are arranged on a semiconductor substrate in a two-dimensional matrix; and a vertical selection means for selecting a readout row of the imaging region; The detection signals are sequentially read from a plurality of vertical signal lines arranged in the column direction for reading out the detection signals of the photodiodes corresponding to the selected row and the horizontal signal lines arranged in the row direction from the vertical signal lines. In a driving method of a solid-state imaging device having a horizontal transistor to be output,
In selecting the unit cell, in all the cells of only a selected row, the reset transistor is turned on , the drain voltage of the reset transistor is applied to the gate of the amplification transistor, and the amplification transistor of the non-selected row is selected. A method for driving a solid-state imaging device, wherein the driving is performed by setting a voltage higher than a gate voltage . In order to deselect the unit cell, in all cells in only a selected row, the reset transistor is turned on, and the drain voltage of the reset transistor is applied to the gate of the amplification transistor. 2. The method for driving a solid-state imaging device according to claim 1, wherein the voltage is set to a voltage lower than the voltage of the gate of the amplification transistor . In the horizontal effective period, connected to the drain of the reset transistor and the drain of the amplifier transistor, the drain line connected to the drain of the reset transistor in the selected row is at a high level,
During the reset operation, the reset address line and the drain line connected to the gate of the reset transistor in the selected row are at a high level,
2. The method of driving a solid-state imaging device according to claim 1, wherein the vertical signal line is at a low level only in a selected row during a read operation.

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