JP3577818B2 - Optimal timing detection method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for detecting an optimum timing of a modulator used for digital communication, for example.
[0002]
[Prior art]
FIG. 5 is a diagram showing a conventional apparatus for measuring the bit error rate of a two-phase phase shift keying signal wave modulator. In the figure, 1 is a data generator, 2 is a clock generator, 4 is a demodulator, 5 is a bit error rate measuring device, and 9 is a test sample (modulator).
[0003]
Next, the operation of the conventional measuring device will be described. In the conventional device, the data generator 1 sends out data of a random pattern to the modulator 9 as a test object according to a clock signal supplied from the clock generator 2. The clock generator 2 also sends the data to the modulator, which is the specimen, in addition to the data generator 1. After the demodulator 4 demodulates the output signal of the modulator into a baseband signal, the code error rate measuring device 5 measures the bit error rate of the demodulated baseband signal.
[0004]
[Problems to be solved by the invention]
Generally, the timing relationship between data and clock at the input terminal of the waveform shaping circuit in the modulator is as shown in FIG. The 50% level point of the clock rising transient is adjusted to be at the center of the data section. However, even if the timing relationship between the data and the clock slightly deviates from the point at which the clock rising transient 50% level point indicates the data 50% level as shown in FIG. 6, the data identification and waveform shaping operation in the waveform shaping circuit is not performed. Normally done. Therefore, even if the timing relationship between the data and the clock at the input terminal of the waveform shaping circuit in the modulator is erroneously set as shown in FIG. 6, the conventional measuring device obtains data having no problem in the bit error rate, There was a high possibility that the modulator was determined to pass without noticing the error in the timing relationship. In the modulator adjusted with the wrong timing relation, when the clock timing shifts due to the noise on the input clock signal, the time point of the clock rising 50% coincides with the time point of the data 50% level in the figure. In this case, the identification of the data 1 and 0 in the waveform shaping circuit becomes inaccurate. As a result, there is a problem that the bit error rate rapidly deteriorates and the transmission quality of the transmission path deteriorates.
[0005]
Modulator waveform shaping circuit Check the modulator performance including the fact that the data and clock timing at the input end are at the specified timing, judge it to be acceptable, and ship it to realize a line that satisfies the required transmission quality. This was a problem to be solved.
[0006]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and confirms that data and clock timing in a waveform shaping circuit in a modulator are adjusted as specified, and that the modulator performs required modulation. The purpose is to be able to confirm that.
[0007]
[Means for Solving the Problems]
An optimal timing detection method according to the present invention measures a data generator that generates a data signal for a modulator of a two-phase shift keying signal wave, a clock generator that generates a clock signal, and measures a bit error rate of a modulator output signal. A bit error rate measuring device, a phase shifter for shifting a phase of a clock signal generated by the clock generator, a central processing unit for adjusting a phase shift amount of the phase shifter, and a phase shift amount of the clock signal and corresponding A data display device for displaying the bit error rate of the modulator output signal to be modulated, and measuring the bit error rate of the modulator output signal at a specified clock timing and when the phase of the clock is shifted from the specified value. To determine whether the same bit error rate is obtained when the clock phase is shifted from the specified value, as in the case of timing. More, located in the phase shift is specified range of clock timing, and in which the modulator operates normally is able to see.
[0008]
Further, according to the optimum timing detecting method of the present invention, the phase of the clock is shifted from the prescribed value until the bit error rate becomes the worst value, and the phase shift amount of the clock at which the code error rate becomes the worst value is the section length of one bit of data. By determining whether or not the value is half of the value, it is possible to confirm whether or not the clock timing adjustment in the modulator is performed as prescribed.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1
FIG. 1 shows a first embodiment of the present invention, in which a phase shifter 3 is provided between an output of a clock generator 2 and a clock signal input end of a modulator 9 which is a test object. And a central processing unit 6 for recording the code error rate of the demodulated baseband signal and making a pass judgment. 7 is a data display device and 8 is a keyboard. FIG. 2 is a flowchart of a program loaded in the central processing unit 6 in advance.
[0010]
In the optimal timing detecting device configured as described above, the central processing unit 6 operates the phase shifter 3, the data generator 1, the clock generator 2, the demodulator 4, and the code error rate measuring device 5 according to the flowchart shown in FIG. Let it. In step 11 of FIG. 2, the modulator 9 as a test sample is operated at the clock timing specified in FIG. 4 in relation to the data and the clock, and demodulated by the demodulator 4 in step 12. The code error rate of the baseband signal is measured by the code error rate measuring device 5. The measurement result is discriminated in step 13 as to whether or not the value is equal to or smaller than the standard value. If the measured result is equal to or smaller than the standard value, the process proceeds to the next step. Step 24), and the fact is displayed on the data display device 7 (step 25).
[0011]
In steps 14 to 20, the clock timing is shifted from the specified timing by the phase shift amount according to the external input value from the specified timing, and the demodulation baseband code error rate is measured. Identify and judge whether it is a value. If the value is larger than the standard value, it is determined that the clock timing in the modulator is abnormal (step 24). If it is determined in step 20 that the bit error rate measurement result is equal to or smaller than the standard value, it is determined that the modulator functions normally even if the phase shift of the clock timing is at the limit of the standard range (step 21). This is displayed on the data display device (step 22). By performing the above operation, the timing relationship between the data and the clock at the input terminal of the waveform shaping circuit in the modulator slightly deviates from the point at which the clock rising transient 50% level point shows the data 50% level as shown in FIG. Can be detected, and it is possible to avoid erroneously making a pass determination.
[0012]
Embodiment 2
FIG. 3 is a flowchart of a program loaded in the central processing unit 6 in the embodiment shown in FIG.
In the optimal timing detection device shown in FIG. 1, the central processing unit 6 operates the phase shifter 3, the data generator 1, the clock generator 2, the demodulator 4, and the code error rate measuring device 5 according to the flowchart shown in FIG. In FIG. 3, at step 28, the modulator 9 as a test object is operated at the clock timing specified in FIG. 4, and at step 29, the code error rate of the baseband signal demodulated by the demodulator 4 is determined by the code error. It is measured by the ratio measuring device 5. The measurement result is determined in step 30 as to whether the value is equal to or less than the standard value. If the value is equal to or smaller than the standard value, the process proceeds to the next step. 39), the fact is displayed on the data display device 7 (step 40).
[0013]
If not, the clock phase is shifted in steps 31 and 32, the bit error rate is measured in step 33, and the process proceeds to step 34. In step 34, it is determined whether the value is larger than the previously obtained bit error rate. If the value is larger, the process returns to step 31. In steps 34, the operations in steps 31 to 33 are performed until a value not larger than the value obtained in the previous measurement is detected. repeat. If a value that is not large is detected, in step 35, the clock phase amount at the time of the previous measurement of the bit error rate is recorded, and it is determined whether the clock phase amount recorded in step 36 is equal to half the data section length. I do. If the clock phase amount is determined to be half the length of the data section, the clock timing in the modulator is determined to be normal in step 37 and the CRT terminal 7 determines in step 38 that the clock timing in the modulator is normal. To be displayed. If it is determined that the clock phase amount does not correspond to half the length of the data section, the clock timing in the modulator is determined to be abnormal in step 39, and data indicating that the clock timing in the modulator is abnormal is determined in step 40. It is displayed on the display device 7.
[0014]
【The invention's effect】
According to the present invention, the central processing unit 6 adjusts the phase shift amount of the phase shifter 3 and determines the code error rate of the demodulated baseband at the specified clock timing and when the timing is shifted from the specified clock error rate. By confirming that there is no change in the bit error rate by measuring in step 5, if the timing difference between the data and the clock in the modulator waveform shaping circuit is within the standard, does the modulator operate normally? It is possible to determine whether or not.
[0015]
Further, according to the present invention, the phase shift amount at which the code error rate of the demodulated baseband has the worst value is measured and recorded, and the phase shift amount is confirmed to be half of the data section length, so that the modulator is improved. It can be confirmed that the clock timing of the internal waveform shaping circuit is set as specified.
[Brief description of the drawings]
FIG. 1 is a diagram showing Embodiments 1 and 2 of an optimum timing detection device according to the present invention.
FIG. 2 is a flowchart of a program loaded into a central processing unit in the first embodiment of the optimum timing detection device according to the present invention;
FIG. 3 is a flowchart of a program loaded into a central processing unit according to a second embodiment of the optimum timing detection device according to the present invention;
FIG. 4 is a diagram showing a timing relationship between data and a clock in a normal state at an input terminal of a waveform shaping circuit in a modulator.
FIG. 5 is a diagram showing a conventional optimal timing detection device.
FIG. 6 is a diagram illustrating a timing relationship between data and a clock when an abnormality occurs at an input end of a waveform shaping circuit in the modulator.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Data generator 2 Clock generator 3 Phase shifter 4 Demodulator 5 Code error rate 6 Central processing unit (CPU)
7 Data display device 8 Keyboard 9 Specimen (modulator)

Claims (2)

A data generator for generating a data signal for a modulator of a two-phase phase shift keying signal wave, a clock generator for generating a clock signal, a code error rate measuring device for measuring a code error rate of the modulator output signal, A phase shifter for shifting the phase of the clock signal generated by the clock generator, a central processing unit for adjusting the phase shift amount of the phase shifter, a phase shift amount of the clock signal, and a code error of the modulator output signal corresponding thereto. A data display device for displaying the rate, and measures the code error rate of the modulator output signal at the specified clock timing and when the clock phase is shifted from the specified, and specifies the clock phase as at the specified clock timing. By checking whether the same bit error rate is obtained even when the clock is shifted further, the phase shift of the clock timing can be Located 囲内, and optimal timing detection method characterized by that the modulator operates normally is able to see. A data generator for generating a data signal for a modulator of a two-phase phase shift keying signal wave, a clock generator for generating a clock signal, a code error rate measuring device for measuring a code error rate of the modulator output signal, A phase shifter for shifting the phase of the clock signal generated by the clock generator, a central processing unit for adjusting the phase shift amount of the phase shifter, a phase shift amount of the clock signal, and a code error of the modulator output signal corresponding thereto. A data display device for displaying the rate, wherein the phase of the clock is shifted from the specified value until the bit error rate becomes the worst value, and the phase shift amount of the clock at which the code error rate becomes the worst value is the data 1-bit section length. To determine if the clock timing adjustment in the modulator has been performed as specified. Optimal timing detection method characterized by the.

Images