JP3575231B2 - Digital communication device and communication method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to digital communications, and more particularly to digital communications that include a phase locked loop (PLL) for generating a clock signal.
[0002]
[Prior art]
FIG. 2 shows a configuration of the communication system. The data transmitter 11 and the data receiver 12 are connected by a bus 13. This communication system is, for example, a digital serial communication system of the IEEE 1394 standard. Three or more communication devices can be connected to the bus 13. The data transmitter 11 transmits a packet to the data receiver 12 via the bus 13. The packet includes time information (time stamp) and data. Details of the packet will be described below.
[0003]
FIG. 3A shows sampled digital data, and FIGS. 3B to 3D show the format of a packet when communicating the digital data.
[0004]
FIG. 3A shows a time stamp TS indicating a transmission time and sampling data DT to be transmitted. The time stamp TS is generated, for example, at timings T1, T2, and T3. The data DT is, for example, an audio signal or a video signal, and includes data strings D (1) to D (12).
[0005]
For example, a packet PK1 including data D (1) to D (5) is transmitted at the time of the time stamp T1, a packet PK2 including data D (6) to D (10) is transmitted at the time of the time stamp T2, A packet PK3 including data D (11) and D (12) is transmitted at the time of the time stamp T3.
[0006]
As shown in FIG. 3B, the packet PK1 includes a time stamp T1 and data D (1) to D (5) following the time stamp T1. As shown in FIG. 3C, the packet PK2 is composed of a time stamp T2 and subsequent data D (6) to D (10). As shown in FIG. 3D, the packet PK3 is composed of a time stamp T3 and subsequent data D (11) and D (12). The packets PK1, PK2, and PK3 are sequentially transmitted on the bus 13 (FIG. 2).
[0007]
FIG. 4 shows a configuration of the data transmitter 11 shown in FIG. 2, and FIG. 5 is a timing chart showing the operation.
[0008]
The clock generator 21 generates a high-frequency (for example, about 25 MHz) system clock SCL. The counter 22 sequentially counts the number of clocks of the system clock SCL and outputs a count value TM.
[0009]
The word clock WCL is equivalent to a sampling clock, and has a lower frequency (for example, 44.1 kHz) than the system clock SCL. The D-type flip-flop 23 inputs the word clock WCL to the D terminal, inputs the system clock SCL to the clock terminal, and outputs the clock QCL from the Q terminal. The clock QCL is obtained by quantizing the word clock WCL with the system clock SCL.
[0010]
The latch circuit 24 latches the count value TM at the timing of the clock QCL and outputs it as a time stamp TS. The transmission unit 25 generates a packet PK (FIGS. 3B to 3D) based on the time stamp TS and the digital data DT, and transmits the packet PK on the bus 13 (FIG. 3).
[0011]
FIG. 6 shows the configuration of the data receiver 12 (FIG. 2) according to the prior art.
The packet PK is a packet received from the data transmitter 11 via the bus 13. The receiving unit 4 separates the packet PK into a time stamp TS and data DT.
[0012]
The clock generator 1 generates a high-frequency (for example, about 25 MHz) system clock SCL. The system clock SCL has the same frequency as the system clock SCL generated by the clock generator 21 (FIG. 4), but is not synchronized (that is, the phases are not necessarily the same).
[0013]
The counter 2 sequentially counts the number of clocks of the system clock SCL generated by the clock generator 1, and outputs a count value TM. Note that the counter 2 is synchronized with the counter 22 (FIG. 4). That is, both are reset at the same timing.
[0014]
As shown in FIG. 5, the comparator 3 compares the count value TM with the time stamp TS, and outputs a match signal MT when they match. The phase detector 5 receives the match signal MT and the feedback signal WCL, and detects a phase difference between the two. The voltage controlled oscillator (VCO) 6 receives the phase difference, and corrects and outputs the word clock WCL in a direction to eliminate the phase difference. The word clock WCL is fed back to one input terminal of the phase detector 5.
[0015]
The phase detector 5 and the VCO 6 constitute a phase locked loop (PLL). By repeating this loop, the word clock WCL is settled at the same frequency (for example, 44.1 kHz) as the word clock WCL of the data transmitter 11 (FIG. 4).
[0016]
Since the data receiver 12 can reproduce the word clock WCL having the same frequency as the word clock WCL of the data receiver 11, the data transmitter 11 and the data receiver 12 can use the word clock WCL having an arbitrary frequency. .
[0017]
[Problems to be solved by the invention]
The data receiver 12 has a PLL including the phase detector 5 and the VCO 6. The word clock WCL generated by using the PLL may include jitter and become unstable.
[0018]
An object of the present invention is to provide a digital communication device or communication method including a phase locked loop (PLL) that generates a stable clock.
[0019]
[Means for Solving the Problems]
According to one aspect of the present invention, the receiving unit includes: a first clock generator that generates a receiving system clock; an input terminal that inputs a timing signal synchronized with a transmitting-side system clock; Receiving a system clock and the timing signal, comparing the two, and generating a match signal at a timing at which both match; receiving a word clock for reception and the system clock for reception; A first flip-flop that outputs a word clock for reception at a timing, a word clock for reception output by the first flip-flop and the match signal are input, and a signal corresponding to a phase difference between the two signals is received. An oscillator for feeding back the first flip-flop as a word clock. Communication device is provided.
[0020]
The first flip-flop outputs the receiving word clock at the timing of the receiving system clock. Each of the oscillators generates the word clock for reception in accordance with the phase difference between the clock synchronized with the system clock for reception and the match signal, so that a stable word clock for reception can be generated.
[0021]
According to another aspect of the present invention, (a) a step of inputting a timing signal in a receiving unit, (a-1) a step of generating a receiving system clock, and (a-2) a system of a transmitting side (A-3) receiving the receiving system clock and the timing signal, comparing the two, and generating a match signal at a timing when the two coincide with each other; a-4) Receiving the receiving word clock and the receiving system clock input to the feedback terminal, outputting the receiving word clock at the timing of the receiving system clock, and receiving the receiving word clock and the match signal. And feeding back a signal corresponding to the phase difference between the two to the feedback terminal as the word clock for reception. That a communication method comprising the step (a) is provided.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
The communication device according to the embodiment of the present invention can constitute the same communication system as that of FIG. This communication system is, for example, a digital serial communication system of the IEEE 1394 standard. The data transmitter 11 and the data receiver 12 are connected by a bus 13. Three or more communication devices can be connected to the bus 13. The data transmitter 11 transmits a packet PK (FIGS. 3B to 3D) to the data receiver 12 via the bus 13. The packet PK includes a time stamp TS and data DT. The data DT is, for example, an audio signal or a video signal. The data transmitter 11 has the same configuration as the configuration shown in FIG.
[0023]
FIG. 1 shows a configuration of a data receiver 12 (FIG. 2) according to an embodiment of the present invention. It differs from the data receiver 12 according to the prior art shown in FIG. 6 in that a flip-flop 7 is newly added. By adding the flip-flop 7, the data receiver 12 can generate a stable word clock WCL. Hereinafter, the operation will be described.
[0024]
The packet PK is a packet received from the data transmitter 11 via the bus 13 (FIG. 2). The receiving unit 4 separates the time stamp TS and the data DT based on the packet PK.
[0025]
The clock generator 1 generates a high-frequency (for example, about 25 MHz) system clock SCL. The system clock SCL has the same frequency as the system clock SCL generated by the clock generator 21 (FIG. 4), but is not synchronized (that is, the phases are not necessarily the same).
[0026]
The counter 2 sequentially counts the number of clocks of the system clock SCL generated by the clock generator 1, and outputs a count value TM. The reset of the counter 2 is instructed at the same timing as the counter 22 (FIG. 4). The counter 2 and the counter 22 count the same value within an error range of one clock.
[0027]
In the D flip-flop 7, the word clock WCL is fed back to the D terminal, the system clock SCL is input to the clock terminal, and the clock QCL is output from the Q terminal. The clock QCL is obtained by quantizing the word clock WCL with the system clock SCL.
[0028]
As shown in FIG. 5, the comparator 3 compares the count value TM with the time stamp TS, and outputs a match signal MT when they match. The phase detector 5 receives the match signal MT and the clock QCL and detects a phase difference between the two. The voltage controlled oscillator (VCO) 6 corrects and outputs the word clock WCL in a direction to eliminate the phase difference. The word clock WCL is fed back to the D terminal of the flip-flop 7.
[0029]
The phase detector 5, VCO 6, and flip-flop 7 constitute a phase locked loop (PLL). By repeating this loop, the word clock WCL is settled at the same frequency (for example, 44.1 kHz) as the word clock WCL of the data transmitter 11 (FIG. 4). Since the data receiver 12 can reproduce the word clock WCL having the same frequency as the word clock WCL of the data transmitter 11, the data transmitter 11 and the data receiver 12 can use the word clock WCL having an arbitrary frequency. .
[0030]
In the conventional data receiver 12 (FIG. 6), the word clock WCL is directly fed back to the phase detector 5 without passing through the flip-flop. That is, the word clock WCL is fed back without being quantized by the system clock SCL. The word clock WCL and the match signal MT are input to the phase detector 5. The match signal MT is quantized by the system clock SCL, but the word clock WCL is not quantized by the system clock SCL. In particular, since the word clock WCL has an undefined value at the initial stage, the word clock WCL is not synchronized with the system clock WCL.
[0031]
Since the word clock WCL is input to the phase detector 5 without being quantized by the system clock WCL, it may be difficult for the PLL to generate a stable word clock WCL.
[0032]
In the data receiver 12 according to the present embodiment, since the phase detector 5 inputs the clock QCL quantized by the system clock SCL and the match signal MT, both inputs are synchronized, and the PLL is a stable word clock. WCL can be generated.
[0033]
The flip-flop 7 outputs the clock QCL obtained by quantizing the word clock WCL with the system clock SCL to the phase detector 5, so that the data receiver 12 can generate a stable word clock WCL with little or no jitter. it can.
[0034]
The data receiver 12 according to the present embodiment employs the same logic as the data transmitter 11 to stabilize the operation. That is, the data transmitter 11 shown in FIG. 4 has logic for generating the clock QCL by quantizing the word clock WCL with the system clock SCL in the flip-flop 23. Therefore, in the data receiver 12 (FIG. 1), similarly to the data transmitter 11, the flip-flop 7 includes logic for quantizing the word clock WCL with the system clock SCL to generate the clock QCL.
[0035]
In the above, the data transmitter 11 and the data receiver 12 have been described as separate data communication devices, but one data communication device may include both the data transmitter 11 and the data receiver 12. In that case, data is transmitted from a data transmitter in one data communication device to a data receiver in another data communication device. One data communication device can perform both transmission and reception of data.
[0036]
The data communication device can be applied to other digital communication in addition to IEEE1394.
[0037]
The data communication device is suitable for communication of audio signals or video signals, regardless of the type of data to be communicated.
[0038]
Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
[0039]
【The invention's effect】
As described above, according to the present invention, the oscillator generates the receiving word clock in accordance with the phase difference between the clock synchronized with the receiving system clock and the match signal, so that the stable receiving word clock is generated. Can be generated.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a data receiver according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a communication system.
FIG. 3A is a diagram showing a time stamp and sampling data, and FIGS. 3B to 3D are diagrams showing a format of a communication packet.
FIG. 4 is a diagram showing a configuration of a data transmitter.
FIG. 5 is a timing chart showing operations of the data transmitter and the data receiver.
FIG. 6 is a diagram showing a configuration of a data receiver according to the related art.
[Explanation of symbols]
1 clock generator, 2 counter, 3 comparator, 4 receiver, 5 phase detector, 6 voltage controlled oscillator (VCO), 7 flip-flop, 11 data transmitter, 12 data receiver, 13 bus, 21 clock generator , 22 counter, 23 flip-flop, 24 latch circuit, 25 transmission unit, TS time stamp, DT sampling data, PK packet, SCL system clock, WCL word clock, QCL clock, MT match signal, TM count value

Claims (4)

A receiving unit,
A first clock generator for generating a receiving system clock;
An input terminal for inputting a timing signal synchronized with a transmission-side system clock,
A comparator that receives the reception system clock and the timing signal, compares the two, and generates a match signal at a timing at which both match;
A first flip-flop that receives a receiving word clock and the receiving system clock, and outputs a receiving word clock at the timing of the receiving system clock;
An oscillator that receives a word clock for reception output from the first flip-flop and the match signal, and feeds back a signal corresponding to a phase difference between the two as the word clock for reception to the first flip-flop; A digital communication device having a receiving unit. Further, the transmitting unit,
A second clock generator for generating a transmission system clock;
A second flip-flop that receives the transmission system clock and outputs a transmission word clock at the timing of the transmission system clock;
2. A transmission unit connected to the second flip-flop, the transmission unit comprising: a latch unit that latches the transmission system clock at a timing of a clock output from the second flip-flop and outputs a timing signal. Digital communication device. (A) a step of inputting a timing signal in a receiving unit,
(A-1) generating a receiving system clock;
(A-2) inputting a timing signal synchronized with a system clock on a transmission side;
(A-3) receiving the receiving system clock and the timing signal, comparing the two, and generating a match signal at a timing at which the two match;
(A-4) Receiving the receiving word clock and the receiving system clock input to the feedback terminal, outputting a receiving word clock at the timing of the receiving system clock, and receiving the receiving word clock and the match signal. And feeding back a signal corresponding to the phase difference between the two signals to the feedback terminal as the receiving word clock. Further, (b) a step of outputting a timing signal in the transmission unit,
(B-1) generating a transmission system clock;
(B-2) receiving the transmission system clock and outputting a transmission word clock at the timing of the transmission system clock;
4. The communication according to claim 3, further comprising the step of: (b-3) latching the transmission system clock at the timing of the clock output in the step (b-2) and outputting a timing signal. Method.

Images