JP3572599B2 - Semiconductor relay - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a semiconductor relay, and more particularly, to a semiconductor relay in which an offset voltage generated at both ends of a contact portion of a semiconductor relay is removed.
[0002]
[Prior art]
FIGS. 3A and 3B show a general configuration of a high voltage DMOS (Double Diffused MOS) FET (hereinafter simply referred to as FET) semiconductor relay. FIG. 3A shows the chip layout of the FET and FIG. 4) is a circuit diagram including the LED, the photodiode, the FET, the on-resistance of the FET, the parasitic diode, and the wiring resistance. In these figures, 1 is an LED, and 2 is a voltage output type photodiode array (hereinafter simply referred to as a photodiode) arranged near the LED. The anode-side terminal of the photodiode 2 is connected to a gate wire bonding pad (hereinafter, simply referred to as a gate pad) 3 of FETs Q ₁ and Q ₂ (see FIG. A), and the cathode-side terminal is a source wire bonding pad (hereinafter, referred to as a gate pad). 4 simply referred to as a source pad).
[0003]
Reference numeral 5 denotes a shunt resistor connected between the gate pad 3 and the sources of the FETs Q ₁ and Q _2. The shunt resistor 5 serves as a discharge resistor for discharging the charge stored in the gate when the semiconductor relay changes from the on state to the off state. Function. 6 the drain wire bonding pads of FETs Q _1, 7 is a drain wire bonding pads of FETs Q _2. 6a is the FETs Q _1, 7a is the on-resistance FETQ _2, 6b, 7b are parasitic diodes of these FET, _{R 1} is of _{Q 1,} the resistance of _{R 4} is _{Q 2} of drain lines, _{R 2} is of _{Q 1,} R ₃ the resistance of the source wiring of Q _2, r is the wiring resistance connecting the drain pad of the source pad 4 and Q _2.
[0004]
In such a configuration, when an operating current flows through the LED 1, light is emitted from the LED ₁ , and a voltage corresponding to the intensity of the light is generated in the voltage output type photodiode array 2, and this voltage causes the gates of the FETs Q ₁ and Q ₂ to operate. Is turned on, and the semiconductor relay is turned on.
[0005]
[Problems to be solved by the invention]
By the way, the above-mentioned semiconductor relay is built on a Si substrate, and wiring connecting each electronic element such as LED, photodiode array, FET and the like is formed of Al or the like. However, since it is not a perfect conductor, the sheet resistance is about 30 mΩ / □. have. In an actual FET, the wiring resistance (R ₂ , R ₃ ) of the source connecting the _two FETs Q ₁ and Q ₂ is about 0.1Ω, depending on the pattern.
[0006]
Here, when an operating current (I _F ) of about 5 mA flows through the LED ₁ , a current (I _PD ) of about 10 μA is obtained from the voltage output type photodiode array 2, and the drain wire bonding pads of the FETs Q ₁ and Q ₂ An offset voltage (V _offset ) of about 1 μV is generated between 6 and 7.
[0007]
When the operating current (I _F ) of the LED 1 is increased to operate the semiconductor relay at higher speed, the current (I _PD ) of the diode array 2 is increased, and the gate capacitance of the FET can be quickly charged to realize high-speed operation. since the voltage drop due to _PD and the wiring resistance _{R M} is the offset voltage, the offset voltage _{(V off set)} with the increase in operating current _{(I F)} is also increased. Generally, the absolute maximum rating (I _F ) flowing to the LED is about 50 mA, so the offset voltage is about 10 μV, which is ten times as large.
[0008]
FIG. 4 shows an example in which such a semiconductor relay is applied to, for example, an input switch of a recorder or a data logger. Reference numeral 20 denotes a plurality of semiconductor relays, 21 denotes an amplifier, 22 denotes an A / D converter, and 23 denotes a display unit. In such measuring instruments that input signals at a large number of measurement points, a weak voltage signal such as a temperature signal of a thermocouple may be input. Therefore, when trying to accurately measure a weak signal, there is a problem that an error occurs in the measured value due to the offset voltage as described above.
[0009]
[Means for Solving the Problems]
The present invention has been made to solve the above problems.
In a semiconductor relay having a pair of high breakdown voltage DMOSFETs having a gate and a source connected to each other on the same chip as an LED and a photodiode, and a gate wire bonding pad and a source wire bonding pad, the source wire bonding pad and the gate wire bonding pad are provided. A source shunt resistor is provided between the pair of high-breakdown-voltage DMOSFETs, and the source wire bonding pad is disposed near the junction between the pair of high-breakdown-voltage DMOSFETs to reduce the distance between the source wire bonding pad and the gate wire bonding pad. The present invention is characterized in that a wiring resistance generated between a bonding point between a wire bonding pad and the pair of high breakdown voltage DMOSFETs is reduced to a level that can be regarded as zero .
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
1 (a) and 1 (b) are main part configuration diagrams showing an example of an embodiment of the present invention. FIG. 1 (a) is an enlarged perspective view of an FET chip layout, and FIG. It is a circuit diagram in the case of having done. The same elements as those in FIG. 4 are denoted by the same reference numerals. In Figure 1, Rutotomoni source wire bonding is provided between the gate pad 3 and FETs Q _1, gate shunt resistor 5 which had signed the sources with each other Q ₂ 'pad 3 and source pad 4 and FIG. 3 shown in the conventional example The only difference is that the pads are arranged near the junction between the sources of the pair of high breakdown voltage DMOSFETs .
[0011]
According to the above configuration, the current I _PD generated by photodiode 2 is circulated as the gate pad 3 → shunt resistor 5 → source pad 4 → photodiode 2.
As a result, conventional, photodiode 2 in the resulting current I _PD is the gate pad 3 → shunt resistor 5 → resistance of the source lines of Q ₂ R ₃ → source pad 4 → photodiode offset voltage generator by circulating as 2 Can be eliminated.
[0012]
FIG. 2 shows the relationship between the offset voltage appearing between the contacts of the conventional and the FETs of the semiconductor relay of the present invention. It can be seen that the offset voltage of the semiconductor relay of the present invention is much smaller than that of the conventional example. . The reason why the offset voltage of the semiconductor relay of the present invention is slightly generated as the LED current increases is that this light irradiates the FET as the LED light becomes stronger, and the offset voltage is generated by the current generated between the on-resistance and the parasitic diode. Seems to be caused.
[0013]
Further, in the embodiment of the present invention, the source pad 4 is arranged near the junction of the pair of FETs. Such an arrangement is effective when the drain pads of the FETs Q ₁ and Q ₂ of the semiconductor relay are short-circuited and used with one polarity. That is, the ON resistance R _on of Q _{1 in} the circuit shown in FIG. 3B is R _on = {(6a + R ₁ + R ₂ + R ₃ ) × (7a + R ₄ )} / ｛(6a + R ₁ + R ₂ + R ₃ ) + ( 7a + R ₄ )｝ + r ... ▲ 1 ▼
Becomes
[0014]
Figure 1 of the on-resistance _{R on Q 1} of the present invention shown in (b) 'is _{R on' = {(6a +} R 1 + R 2) × (7a + R 3 + R 4)} / {(6a + R 1 + R 2) + (7a + R 3 + R ₄ )｝ ・ ・ ・ ▲ 2 ▼
(In general, when realizing a low on-resistance semiconductor relay, the chip size is large, the routing of the source wiring is long, and r may be about 10Ω). By reducing the distance to, r can be reduced to a level that can be regarded as zero, as shown in equation (2), and the on-resistance can be reduced even in an equation not including r.
[0015]
【The invention's effect】
As described above in detail, according to the present invention, a semiconductor relay in which a pair of high-breakdown-voltage DMOSFETs whose gates and sources are connected to each other and a gate wire bonding pad and a source wire bonding pad are formed on the same chip as an LED and a photodiode A shunt resistor is provided between the source wire bonding pad and the gate wire bonding pad, and the source wire bonding pad is arranged near a connection point of the pair of high breakdown voltage DMOSFETs; , The wiring resistance generated between the source wire bonding pad and the connection point of the pair of high breakdown voltage DMOSFETs is reduced to a level that can be regarded as zero . As a result, a voltage drop caused by the drain wiring resistance of the conventional FET can be removed, and a semiconductor relay with an offset removed can be realized. Further, since the source wire bonding pad is disposed near the junction of the pair of FETs, the on-resistance can be reduced even when the semiconductor relay is used in one polarity.
[Brief description of the drawings]
FIG. 1 is an enlarged view (a) and a circuit diagram of an FET showing an example of an embodiment of a semiconductor relay of the present invention.
FIG. 2 is a diagram showing a relationship between an offset voltage and an LED operating current of the semiconductor relay of the present invention and a conventional semiconductor relay.
FIG. 3 is an enlarged view (a) and a circuit diagram of an FET showing an example of a conventional semiconductor relay circuit.
FIG. 4 is a main part configuration diagram showing a state where a semiconductor relay is applied to a recorder.
[Explanation of symbols]
1 LED
2 on the photodiode array 3 gate wire bonding pads 4 source wire bonding pads 5 shunt resistor 6 _{Q 1} for the drain wire bonding pads 6a drain parasitic diode 7 _{Q 2} of the on-resistance 6b _{Q 1 Q 1} wire bonding pads 7a _{Q 2} Parasitic diodes Q ₁ , Q _{2 of} resistance 7b Q ₂ High breakdown voltage DMOSFET

Claims (1)

In a semiconductor relay having a pair of high-breakdown-voltage DMOSFETs having a gate and a source connected to each other on the same chip as an LED and a photodiode, and a gate wire bonding pad and a source wire bonding pad, the source wire bonding pad and the gate wire bonding pad are provided. A shunt resistor is provided between the pair of high-breakdown-voltage DMOSFETs, and the source wire bonding pad is disposed near the junction of the pair of high-withstand-voltage DMOSFETs. A semiconductor relay characterized in that a wiring resistance generated between a bonding point of a wire bonding pad and a pair of said high breakdown voltage DMOSFETs is reduced to a level that can be regarded as zero .

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