JP3566311B2 - Block cipher based on pseudo-random nonlinear sequence generator - Google Patents

Abstract

A block-cipher cryptographic device that processes plaintext/encrypted input data with a key signal to provide encrypted/decrypted output data. Such device includes a shift register (10) for receiving input data (13); and data processing means (12), including a pseudorandom nonlinear sequence generator (32), for executing the following data processing routine a selected number of cycles to provide output data (15): processing (18, 22, 30) the contents (16) of said shift register with a key signal (14) to provide initially processed data (28); initializing the pseudorandom nonlinear sequence generator with the initially processed data; running the pseudorandom nonlinear sequence generator to generate a keystream (34); segregating (36, 38) portions of the keystream; processing (44) said segregated portions of said keystream with a portion of the data in the shift register to provide a block of processed data; and shifting said block of processed data into the shift register. To further increase the randomness of the pseudorandom keystream generator, and hence the encryption security, the data processing routine segregates the keystream in accordance with a routine (36) wherein the beginning of said segregated portion is provided at a time related to the beginning of the keystream in response to a duration indication (Y); segregates (38) every nth bit of the keystream from said beginning of said segregated portion for a selected number of segregated bits in response to a frequency indication (n); and provides said initially processed data by first processing (18) said shift register contents and said key signal and then rotating (22) data produced by said first processing in response to a rotation indication (X). The duration indication, the frequency indication and the rotation indication are each separately provided for each of the cycles and may be different for each of the cycles. <IMAGE> <IMAGE>

Description

[0001]
[Industrial applications]
The present invention relates to a block cipher device.
[0002]
[Prior art]
Block ciphers based on the DES (Data Encryption Standard) algorithm are often used where a high degree of cryptographic confidentiality is required. However, currently, encryption / decryption products, including block ciphers based on the DES algorithm, are restricted from being exported from the United States.
[0003]
[Problems to be solved by the invention]
It is an object of the present invention to provide a block cipher that does not use the DES algorithm, but nevertheless provides a sufficiently high degree of cryptographic secrecy in many applications.
[0004]
[Means for Solving the Problems]
The block cipher device of the present invention is a device that processes ordinary text or encrypted input data with a key signal to provide encrypted or decrypted output data. Such an apparatus comprises a shift register for receiving input data and data processing means including a pseudo-random non-linear sequence generator for executing the following data processing routine for a selected number of cycles to provide output data. The data processing routine is
Processing the contents of the shift register with a key signal to output the first processed data;
Initialize the pseudo-random nonlinear sequence generator with the first processed data,
Operate a pseudo-random nonlinear sequence generator to generate a key flow,
Separate part of the key flow,
Processing said separated portion of the key stream with a portion of the data in the shift register to provide a block of processed data;
And processing for shifting the processed block of data into the shift register.
The degree of secrecy increases as the selected number of cycles of execution of the data processing routine increases.
[0005]
To further increase the randomness of the pseudo-random key stream generator, and thus the confidentiality provided by the cryptographic device of the present invention, the data processing routine may be such that the beginning of the separated part is a key stream in response to a period indication. The key stream is separated according to a routine which gives the time associated with the start of the key stream, and for each selected number of bits separated according to the frequency indication, the bits of the key stream from the beginning every nth of said separated part. And giving the first processed data by the first processing of the shift register contents and the key signal, and rotating the data generated by the first processing according to the rotation instruction. The period indication, the frequency indication, and the rotation indication are provided separately for each cycle, and are different for each cycle.
[0006]
Additional features of the invention will be described by way of example with reference to the accompanying drawings.
[0007]
【Example】
Referring to FIG. 1, the encryption device of the preferred embodiment of the present invention shown in the block diagram of FIG. 1A includes an N-bit feedback shift register 10 and a data processing system 12. Except for the parts described below, the data processing system 12 is constituted by firmware in a microprocessor.
[0008]
An encryption device for encrypting a block cipher shown in FIG. 1A processes an N-byte block of ordinary text input data 13 with an M-byte encryption key signal 14 to encrypt the N-byte block. The output data 15 is output. In the preferred embodiment is M = 7, N = 8. The feedback shift register 10 receives a block of normal text input data 13 of N bytes.
[0009]
The data processing system 12 adds the normal text byte 16 to the key signal 14 byte in a first data processing routine 18 as shown in FIG. The byte 16 is processed by the M-byte encryption key signal 14. In another embodiment, this initial data processing routine 18 may be performed by other processing than addition, such as, for example, subtraction or exclusive OR processing (XOR).
[0010]
The M-byte data 20 generated by the first routine 18 is rotated by the data processing system 12 according to the second data processing routine 22 by the number X of bytes according to the rotation instruction X. The relationship between the rotated byte 26 and the first generated byte 20 is shown in Table 1 below for a 3-byte rotation indication with M = 7.
[0011]
Table 1
Byte 20 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7
Byte 26 byte 4 byte 5 byte 6 byte 7 byte 1 byte 2 byte 3
Data processing system 12 then rotates to provide N bytes of data 28 that were initially processed by executing data decompression routine 30 to decompress the other M bytes 26. In the embodiment, at M = 7, N = 8, the Nth byte is generated by performing an exclusive OR (XOR) operation on the M bytes.
[0012]
The pseudo-random non-linear sequence generator 32 included in the data processing system 12 is initialized with N bytes of the first processed data 28 and is operated to generate a key stream 34. In an embodiment, the pseudo-random non-linear sequence generator 32 for generating a key stream is a dynamic feedback constellation scrambling technique (DFAST) key stream generator 32. It is configured in hardware to increase the processing speed of the data processing system 12. A DFAST key flow generator is described in U.S. Patent No. 4,860,353 (David S. Brown). The embodiments of the DFAST key flow generator described herein include a dynamic (or non-linear) feedback shift register and a static (or linear) feedback shift register for receiving input data. The upper N bytes 28 are received in the dynamic feedback shift register of the DFAST key stream generator 32, while the remaining bytes are received in the static feedback shift register of the generator 32. The DFAST key stream generator 32 performs a fast pseudo-random non-linear sequence processing of N bytes 28 to quickly generate a key stream, and then converts a single byte of data that can be fed back for processing in the next cycle. Can be easily separated to produce. In other embodiments, other types of pseudo-random non-linear sequence generators can be used in place of DFAST key flow generator 32.
[0013]
Data processing system 12 then executes a discard routine 36 and a separation routine 38 to separate portions of key stream 34 into single bytes 40. The data processing system 12 separates the key stream 34 in accordance with a discard routine 36, in which the first of the separated portions of the key stream 42 discards the first Y bytes of the key stream 34, thereby responding to the period indication Y It is provided at the time of the beginning of stream 34.
[0014]
Data processing system 12 further separates every nth bit of key stream 42 from the beginning of said separated portion in response to frequency indication n until eight bits are separated to form a single byte 40. To separate the key stream 42.
[0015]
Details of the discard routine 36 and the separation routine 38 will be described with reference to FIG. To execute these routines, the data processing system includes a period indicating counter 48, a frequency indicating counter 50, a bit counter 52, a byte register 54, and an OR gate 55. All three counters 48, 50, 52 are clocked by the same clock signal 56 that clocks the DFAST key flow generator 32. The output of counter 48 is coupled via OR gate 55 to the load input of counter 50. The output of counter 50 is provided to an enable input of counter 52 and an enable input of byte register 54, and is coupled to an input of counter 50 via OR gate 55. The key stream 34 is provided to a data input of a byte register 54.
[0016]
For each cycle of the data processing routine, the period instruction Y is loaded into the period instruction counter 48, and the frequency instruction n is loaded into the frequency instruction counter 50. After the first Y bytes of the key stream 34, a start pulse 60 is output by the period indicating counter 48 to the frequency indicating counter 50, which provides an enable pulse to the bit counter 52 and the byte register 54. Therefore, the byte register 54 can register the simultaneous bits of the key stream 34, and the number of bits registered in the byte register 54 is counted by the bit counter 52. The frequency indicating counter 50 supplies a pulse 62 to the enable input of the byte register 54 and the enable input of the bit counter 52 at every n-th count of the DFAST clock signal 56 until the count of the bit counter 52 reaches 8. Upon reaching 8, a stop pulse 58 is applied to all three counters 48, 50, 52.
[0017]
Referring again to the block cipher apparatus of FIG. 1, the data processing system 12 further executes a routine 44 whereby a single byte 40 formed by separating portions of the key stream 34 is The least-significant byte and the byte of the processed data 46 exclusive-ORed are provided.
[0018]
The bytes of processed data 46 are shifted to the most significant byte position of feedback shift register 10 and the data in shift register 10 is shifted such that the least significant bytes of data are shifted out of shift register 10.
[0019]
This completes one cycle of the data processing routine. The number of cycles to perform single block encryption of plain text input data is selected according to the degree of encryption confidentiality required for a particular application of the encryption device. It must be at least 16 cycles to ensure that any single bit of the key signal or input data affects every bit of the output data. Preferably, more cycles are performed to further increase the confidentiality. The number of cycles is limited by the processing speed of the data processing system 12, which is related to the frequency at which ordinary text input data is provided to the encryption device for encryption.
[0020]
For each cycle of the data processing routine, the rotation instruction X, the period instruction Y, and the frequency instruction n are given separately. Thus, each of these indications can be different in each of the different cycles.
[0021]
In an embodiment, the rotation number X, the period number Y, and the frequency number n for the selected number of cycles and each of the different cycles are preset in the microprocessor hardware. In another embodiment, the rotation indication X, the duration indication Y, and the frequency indication n for a selected number of cycles and / or each of the different cycles are provided as variable inputs to the microprocessor.
After the processing of the selected number of cycles is completed, the encrypted output data 15 is output from the feedback shift register 10.
In another embodiment, the encrypted output data is provided by sending bytes 46 of the processed data to a component (not shown) separate from feedback shift register 10.
[0022]
Referring to FIG. 3, a block diagram of a preferred embodiment of the encryption device for decrypting blocks according to the present invention is the same as the block encryption device described above with reference to FIGS. 1 and 2 except for the following.
The block cipher apparatus shown in FIG. 3 converts an N-byte encrypted input data block 13 'with an M-byte decryption key signal 14 to output an N-byte block of decrypted output data 15'. To process.
The feedback shift register 10 receives a block 13 'of N bytes of encrypted input data.
[0023]
In the data processing routine 44, the single byte 40 formed by separating the portion of the key signal 34 is exclusive ORed with the most significant byte of data in the feedback shift register 10 and the byte of data processed. Give 46. Byte 46 of this processed data is shifted to the least significant byte position in shift register 10 so that the data in shift register 10 is shifted out of shift register 10 with the most significant byte of data.
[0024]
The block cipher device of FIG. 3 decrypts the encrypted data provided by the block cipher device of FIG. 1 and converts such encrypted data to the ordinary data encrypted by the block cipher device of FIG. Convert to text data.
[Brief description of the drawings]
FIG. 1 is a functional block diagram of a block encryption device according to the present invention and a block diagram of a data processing routine executed by a data processing system of the encryption device.
FIG. 2 is a functional block diagram showing details of a discarded and separated function of the encryption device of FIG. 1;
FIG. 3 is a functional block diagram of a block cipher decryption device according to the present invention.

Claims (7)

Encrypted, or a block cipher apparatus for processing ordinary text input data or encrypted input data with a key signal to provide decrypted output data respectively,
A shift register ( 10 ) for receiving input data;
Data processing means ( 12 ) including a pseudo-random nonlinear sequence generator ( 32 ) for executing a data processing routine for a selected number of cycles to output output data ( 15 ) ;
The data processing routine includes:
In order to output the first processed data ( 28 ) , the contents ( 16 ) of the shift register are processed by the key signal ( 14 ) ( 18 , 22 , 30 ) ,
Pseudorandom nonlinear sequence generator initialized by the first processed data,
Operating a pseudo-random nonlinear sequence generator to generate a key stream ( 34 ) ;
Separate the key flow parts ( 36,38 ) ,
The portion of the data in the shift register to provide a block of processed data (46) processing said separated portion of said key stream (44), and
And wherein the shifting of said blocks of data processed into the shift register. Data processing means, by the shifting of the processing blocks of data in only the shift register number said selected cycle apparatus of claim 1, wherein supplying the output data in the shift register. The data processing routine is provided separately for each cycle, and according to a routine that starts the separated portion at a time indicated by a period indication (Y) , which may be different for each cycle. Apparatus according to claim 1, including a process ( 36 ) for separating key stream portions. The routine for separating the key stream portions is provided separately for each cycle, and for each selected number of bits separated according to a frequency indication (n) that may be different for each cycle. 4. The apparatus of claim 3 wherein said separated portion is provided by separating every nth bit of the key stream from the start of said separated portion. The data processing routine is provided separately for each cycle and the separated for a selected number of bits separated according to a frequency indication (n) that may be different for each cycle. The apparatus of claim 1 including separating the key signal portion by separating ( 38 ) every nth bit of the key stream from the beginning of the portion. The data processing routine outputs the first processed data by first processing the contents of the shift register and the key signal, and is then provided separately for each cycle and different for each cycle. The apparatus according to any one of claims 1, 3, and 5, further comprising a step ( 22 ) of rotating data generated by the first processing in response to a rotation instruction (X) that may be performed. 7. The method according to claim 1, wherein the data processing means comprises a dynamic feedback arrangement scrambling technique key stream generator ( 32 ) for generating the key stream. 8. apparatus.

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